kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/ledc_divider' into 'master'
ledc: fix reported error when div_param == 256 Whenever bit_num and freq_hz are such that div_param == 256, the code would flag that as an error. In fact, value 256 of div_param was a valid one (HW requires that div_param >= 1.0, when interpreted as a Q10.8 fixed point value). Changed the if statements a bit to make the logic clearer, and added more descriptive error messages. Also added missing error for the unimplemented case of low speed mode. Reported in https://github.com/igrr/esp32-cam-demo/issues/2 See merge request !247pull/111/merge
commit
7a93422089
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@ -137,29 +137,32 @@ esp_err_t ledc_timer_config(ledc_timer_config_t* timer_conf)
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return ESP_ERR_INVALID_ARG;
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}
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if(timer_num > LEDC_TIMER_3) {
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ESP_LOGE(LEDC_TAG, "Time Select %u", timer_num);
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ESP_LOGE(LEDC_TAG, "invalid timer #%u", timer_num);
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return ESP_ERR_INVALID_ARG;
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}
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esp_err_t ret = ESP_OK;
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uint32_t precision = (0x1 << bit_num); //2**depth
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uint64_t div_param = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision; //8bit fragment
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int timer_clk_src;
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/*Fail ,because the div_num overflow or too small*/
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if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) { //REF TICK
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/*Selet the reference tick*/
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uint32_t precision = (0x1 << bit_num); // 2**depth
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// Try calculating divisor based on LEDC_APB_CLK
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ledc_clk_src_t timer_clk_src = LEDC_APB_CLK;
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// div_param is a Q10.8 fixed point value
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uint64_t div_param = ((uint64_t) LEDC_APB_CLK_HZ << 8) / freq_hz / precision;
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if (div_param < 256) {
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// divisor is too low
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ESP_LOGE(LEDC_TAG, "requested frequency and bit depth can not be achieved, try reducing freq_hz or bit_num. div_param=%d", (uint32_t) div_param);
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ret = ESP_FAIL;
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}
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if (div_param > LEDC_DIV_NUM_HSTIMER0_V) {
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// APB_CLK results in divisor which too high. Try using REF_TICK as clock source.
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timer_clk_src = LEDC_REF_TICK;
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div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision;
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if(div_param <= 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) {
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ESP_LOGE(LEDC_TAG, "div param err,div_param=%u", (uint32_t)div_param);
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if(div_param < 256 || div_param > LEDC_DIV_NUM_HSTIMER0_V) {
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ESP_LOGE(LEDC_TAG, "requested frequency and bit depth can not be achieved, try increasing freq_hz or bit_num. div_param=%d", (uint32_t) div_param);
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ret = ESP_FAIL;
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}
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timer_clk_src = LEDC_REF_TICK;
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} else { //APB TICK
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timer_clk_src = LEDC_APB_CLK;
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}
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/*set timer parameters*/
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/*timer settings decide the clk of counter and the period of PWM*/
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// set timer parameters
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ledc_timer_set(speed_mode, timer_num, div_param, bit_num, timer_clk_src);
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/* reset timer.*/
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// reset timer
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ledc_timer_rst(speed_mode, timer_num);
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return ret;
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}
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@ -174,7 +177,8 @@ esp_err_t ledc_set_pin(int gpio_num, ledc_mode_t speed_mode, ledc_channel_t ledc
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if(speed_mode == LEDC_HIGH_SPEED_MODE) {
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gpio_matrix_out(gpio_num, LEDC_HS_SIG_OUT0_IDX + ledc_channel, 0, 0);
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} else {
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ESP_LOGE(LEDC_TAG, "low speed mode is not implemented");
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return ESP_ERR_NOT_SUPPORTED;
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}
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return ESP_OK;
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}
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