Update the host configuration options file. Update the osi malloc function.

pull/9328/head
GengYuchao 2022-06-17 21:32:27 +08:00
rodzic 9782f86f82
commit 7916f45d58
6 zmienionych plików z 122 dodań i 81 usunięć

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@ -14,6 +14,7 @@
#include "nimble/nimble_port_freertos.h"
#include "esp_nimble_hci.h"
#include "esp_nimble_mem.h"
#include "bt_osi_mem.h"
#include "esp_bt.h"
#include "freertos/semphr.h"
#include "esp_compiler.h"

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@ -22,31 +22,6 @@
#define IRAM_ATTR_64MCPU IRAM_ATTR
#endif
#define BLE_LL_CTRL_PROC_TIMEOUT_MS_N (40000) /* ms */
#define BLE_LL_CFG_NUM_HCI_CMD_PKTS_N (1)
#define BLE_LL_SCHED_ADV_MAX_USECS_N (852)
#define BLE_LL_SCHED_DIRECT_ADV_MAX_USECS_N (502)
#define BLE_LL_SCHED_MAX_ADV_PDU_USECS_N (376)
#define BLE_LL_SUB_VERS_NR_N (0x0000)
#define BLE_LL_JITTER_USECS_N (16)
#define BLE_PHY_MAX_PWR_DBM_N (10)
#define BLE_LL_CONN_DEF_AUTH_PYLD_TMO_N (3000)
#if CONFIG_IDF_TARGET_ESP32H2
#define RTC_FREQ_N (32768) /* in Hz */
#else
#define RTC_FREQ_N (32000) /* in Hz */
#endif
#define BLE_LL_TX_PWR_DBM_N (0)
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
#define NIMBLE_CFG_CONTROLLER 0
@ -1594,18 +1569,6 @@
#define MYNEWT_VAL_BLE_HCI_UART_STOP_BITS (1)
#endif
#ifndef CONFIG_BLE_TX_CCA_ENABLED
#define MYNEWT_VAL_BLE_TX_CCA_ENABLED (0)
#else
#define MYNEWT_VAL_BLE_TX_CCA_ENABLED (CONFIG_BLE_TX_CCA_ENABLED)
#endif
#ifndef CONFIG_BLE_CCA_RSSI_THRESH
#define MYNEWT_VAL_BLE_CCA_RSSI_THRESH (50)
#else
#define MYNEWT_VAL_BLE_CCA_RSSI_THRESH (CONFIG_BLE_CCA_RSSI_THRESH)
#endif
#ifndef MYNEWT_VAL_NEWT_FEATURE_LOGCFG
#define MYNEWT_VAL_NEWT_FEATURE_LOGCFG (1)

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@ -0,0 +1,15 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_err.h"
esp_err_t esp_nimble_init();
esp_err_t esp_nimble_enable(void *host_task);
esp_err_t esp_nimble_disable();
esp_err_t esp_nimble_deinit();

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@ -13,9 +13,12 @@
extern "C" {
#endif
void *nimble_platform_mem_malloc(size_t size);
void *nimble_platform_mem_calloc(size_t n, size_t size);
void nimble_platform_mem_free(void *ptr);
// #pragma message "This file should be replaced with bt_osi_mem.h, used here for compatibility"
#include "bt_osi_mem.h"
#define nimble_platform_mem_malloc bt_osi_mem_malloc
#define nimble_platform_mem_calloc bt_osi_mem_calloc
#define nimble_platform_mem_free bt_osi_mem_free
#ifdef __cplusplus
}

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@ -0,0 +1,100 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_attr.h"
#include "esp_heap_caps.h"
#include "sdkconfig.h"
#include "esp_nimble_mem.h"
#include "host/ble_hs.h"
static TaskHandle_t host_task_h;
extern void ble_hs_deinit(void);
static struct ble_hs_stop_listener stop_listener;
static struct ble_npl_eventq g_eventq_dflt;
static struct ble_npl_sem ble_hs_stop_sem;
static struct ble_npl_event ble_hs_ev_stop;
esp_err_t esp_nimble_init()
{
#if !SOC_ESP_NIMBLE_CONTROLLER
/* Initialize the function pointers for OS porting */
npl_freertos_funcs_init();
npl_freertos_mempool_init();
/* Initialize default event queue */
ble_npl_eventq_init(&g_eventq_dflt);
os_msys_init();
void ble_store_ram_init(void); // Do we need this?
/* XXX Need to have template for store */
ble_store_ram_init();
#endif
/* Initialize the host */
ble_hs_init();
return ESP_OK;
}
esp_err_t esp_nimble_enable(void *host_task)
{
/*
* Create task where NimBLE host will run. It is not strictly necessary to
* have separate task for NimBLE host, but since something needs to handle
* default queue it is just easier to make separate task which does this.
*/
xTaskCreatePinnedToCore(host_task, "nimble_host", NIMBLE_HS_STACK_SIZE,
NULL, (configMAX_PRIORITIES - 4), &host_task_h, NIMBLE_CORE);
return ESP_OK;
}
esp_err_t esp_nimble_disable()
{
esp_err_t err = ESP_OK;
ble_npl_sem_init(&ble_hs_stop_sem, 0);
/* Initiate a host stop procedure. */
rc = ble_hs_stop(&stop_listener, ble_hs_stop_cb,
NULL);
if (rc != 0) {
ble_npl_sem_deinit(&ble_hs_stop_sem);
return rc;
}
/* Wait till the host stop procedure is complete */
ble_npl_sem_pend(&ble_hs_stop_sem, BLE_NPL_TIME_FOREVER);
ble_npl_event_init(&ble_hs_ev_stop, nimble_port_stop_cb,
NULL);
ble_npl_eventq_put(&g_eventq_dflt, &ble_hs_ev_stop);
/* Wait till the event is serviced */
ble_npl_sem_pend(&ble_hs_stop_sem, BLE_NPL_TIME_FOREVER);
ble_npl_sem_deinit(&ble_hs_stop_sem);
return ESP_OK;
}
esp_err_t esp_nimble_deinit()
{
#if !(SOC_ESP_NIMBLE_CONTROLLER && CONFIG_BT_CONTROLLER_ENABLED)
ble_npl_eventq_deinit(&g_eventq_dflt);
#endif
if (host_task_h) {
vTaskDelete(host_task_h);
}
ble_hs_deinit();
return ESP_OK;
}

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@ -1,41 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_attr.h"
#include "esp_heap_caps.h"
#include "sdkconfig.h"
#include "esp_nimble_mem.h"
IRAM_ATTR void *nimble_platform_mem_malloc(size_t size)
{
#ifdef CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL
return heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
#elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_EXTERNAL
return heap_caps_malloc(size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT);
#elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT
return heap_caps_malloc_prefer(size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
#else
return malloc(size);
#endif
}
IRAM_ATTR void *nimble_platform_mem_calloc(size_t n, size_t size)
{
#ifdef CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_INTERNAL
return heap_caps_calloc(n, size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
#elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_EXTERNAL
return heap_caps_calloc(n, size, MALLOC_CAP_SPIRAM|MALLOC_CAP_8BIT);
#elif CONFIG_BT_NIMBLE_MEM_ALLOC_MODE_IRAM_8BIT
return heap_caps_calloc_prefer(n, size, 2, MALLOC_CAP_INTERNAL|MALLOC_CAP_IRAM_8BIT, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT);
#else
return calloc(n, size);
#endif
}
IRAM_ATTR void nimble_platform_mem_free(void *ptr)
{
heap_caps_free(ptr);
}