kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/adds_efuses_to_table_v4.4' into 'release/v4.4'
efuse: Adds ERR_RST_ENABLE efuse for C3 (v4.4) See merge request espressif/esp-idf!18419pull/9239/head
commit
7905f0d3f8
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@ -9,7 +9,7 @@
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#include <assert.h>
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#include <assert.h>
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#include "esp_efuse_table.h"
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#include "esp_efuse_table.h"
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// md5_digest_table 357feb63f27b95519accb97200d894a7
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// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -311,6 +311,10 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
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{EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
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{EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback,
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};
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};
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static const esp_efuse_desc_t ERR_RST_ENABLE[] = {
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{EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers,
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};
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static const esp_efuse_desc_t MAC_FACTORY[] = {
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static const esp_efuse_desc_t MAC_FACTORY[] = {
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{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
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{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
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{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
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{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
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@ -858,6 +862,11 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
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NULL
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NULL
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};
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};
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const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = {
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&ERR_RST_ENABLE[0], // Use BLOCK0 to check error record registers
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
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const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
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&MAC_FACTORY[0], // Factory MAC addr [0]
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&MAC_FACTORY[0], // Factory MAC addr [0]
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&MAC_FACTORY[1], // Factory MAC addr [1]
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&MAC_FACTORY[1], // Factory MAC addr [1]
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@ -95,6 +95,7 @@
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UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
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UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print.
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FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
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FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot
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SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
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SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback
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ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check.
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# EFUSE_RD_REPEAT_DATA4_REG #
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# EFUSE_RD_REPEAT_DATA4_REG #
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Nie można renderować tego pliku, ponieważ zawiera nieoczekiwany znak w wierszu 7 i kolumnie 87.
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@ -9,7 +9,7 @@ extern "C" {
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#endif
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#endif
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// md5_digest_table 357feb63f27b95519accb97200d894a7
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// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -90,6 +90,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
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extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
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extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
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extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
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extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
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extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[];
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extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
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extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
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extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
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@ -256,11 +256,17 @@ extern "C" {
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#define EFUSE_KEY_PURPOSE_2_S 0
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#define EFUSE_KEY_PURPOSE_2_S 0
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#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010)
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#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x010)
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/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
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/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
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/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
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#define EFUSE_ERR_RST_ENABLE (BIT(31))
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#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
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#define EFUSE_ERR_RST_ENABLE_V 0x1
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#define EFUSE_ERR_RST_ENABLE_S 31
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/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
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/*description: Reserved (used for four backups method).*/
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/*description: Reserved (used for four backups method).*/
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#define EFUSE_RPT4_RESERVED1 0x00000003
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#define EFUSE_RPT4_RESERVED1 (BIT(30))
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#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
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#define EFUSE_RPT4_RESERVED1_M (BIT(30))
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#define EFUSE_RPT4_RESERVED1_V 0x3
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#define EFUSE_RPT4_RESERVED1_V 0x1
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#define EFUSE_RPT4_RESERVED1_S 30
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#define EFUSE_RPT4_RESERVED1_S 30
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/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
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/* EFUSE_SECURE_VERSION : R/W ;bitpos:[29:14] ;default: 16'h0 ; */
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/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
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/*description: Secure version (used by ESP-IDF anti-rollback feature).*/
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@ -609,11 +615,17 @@ extern "C" {
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#define EFUSE_KEY_PURPOSE_2_S 0
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#define EFUSE_KEY_PURPOSE_2_S 0
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#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C)
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#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x03C)
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/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[31:30] ;default: 2'h0 ; */
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/* EFUSE_ERR_RST_ENABLE : RO ;bitpos:[31] ;default: 1'h0 ; */
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/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
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#define EFUSE_ERR_RST_ENABLE (BIT(31))
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#define EFUSE_ERR_RST_ENABLE_M (BIT(31))
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#define EFUSE_ERR_RST_ENABLE_V 0x1
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#define EFUSE_ERR_RST_ENABLE_S 31
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/* EFUSE_RPT4_RESERVED1 : RO ;bitpos:[30] ;default: 1'h0 ; */
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/*description: Reserved.*/
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED1 0x00000003
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#define EFUSE_RPT4_RESERVED1 (BIT(30))
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#define EFUSE_RPT4_RESERVED1_M ((EFUSE_RPT4_RESERVED1_V)<<(EFUSE_RPT4_RESERVED1_S))
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#define EFUSE_RPT4_RESERVED1_M (BIT(30))
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#define EFUSE_RPT4_RESERVED1_V 0x3
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#define EFUSE_RPT4_RESERVED1_V 0x1
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#define EFUSE_RPT4_RESERVED1_S 30
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#define EFUSE_RPT4_RESERVED1_S 30
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/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
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/* EFUSE_SECURE_VERSION : RO ;bitpos:[29:14] ;default: 16'h0 ; */
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/*description: The value of SECURE_VERSION.*/
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/*description: The value of SECURE_VERSION.*/
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#define EFUSE_KEY_PURPOSE_2_ERR_S 0
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#define EFUSE_KEY_PURPOSE_2_ERR_S 0
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#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
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#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188)
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/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[31:30] ;default: 2'h0 ; */
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/* EFUSE_ERR_RST_ENABLE_ERR : RO ;bitpos:[31] ;default: 1'h0 ; */
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/*description: Use BLOCK0 to check error record registers, 0 - without check.*/
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#define EFUSE_ERR_RST_ENABLE_ERR (BIT(31))
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#define EFUSE_ERR_RST_ENABLE_ERR_M (BIT(31))
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#define EFUSE_ERR_RST_ENABLE_ERR_V 0x1
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#define EFUSE_ERR_RST_ENABLE_ERR_S 31
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/* EFUSE_RPT4_RESERVED1_ERR : RO ;bitpos:[30] ;default: 1'h0 ; */
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/*description: Reserved.*/
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/*description: Reserved.*/
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#define EFUSE_RPT4_RESERVED1_ERR 0x00000003
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#define EFUSE_RPT4_RESERVED1_ERR (BIT(30))
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#define EFUSE_RPT4_RESERVED1_ERR_M ((EFUSE_RPT4_RESERVED1_ERR_V)<<(EFUSE_RPT4_RESERVED1_ERR_S))
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#define EFUSE_RPT4_RESERVED1_ERR_M (BIT(30))
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#define EFUSE_RPT4_RESERVED1_ERR_V 0x3
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#define EFUSE_RPT4_RESERVED1_ERR_V 0x1
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#define EFUSE_RPT4_RESERVED1_ERR_S 30
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#define EFUSE_RPT4_RESERVED1_ERR_S 30
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/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
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/* EFUSE_SECURE_VERSION_ERR : RO ;bitpos:[29:14] ;default: 16'h0 ; */
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/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
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/*description: If any bit in SECURE_VERSION is 1 then it indicates a programming error.*/
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@ -165,7 +165,8 @@ typedef volatile struct efuse_dev_s {
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uint32_t rpt4_reserved7: 5; /*Reserved.*/
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uint32_t rpt4_reserved7: 5; /*Reserved.*/
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uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
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uint32_t force_send_resume: 1; /*The value of FORCE_SEND_RESUME.*/
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uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
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uint32_t secure_version: 16; /*The value of SECURE_VERSION.*/
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uint32_t rpt4_reserved1: 2; /*Reserved.*/
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uint32_t rpt4_reserved1: 1; /*Reserved.*/
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uint32_t err_rst_enable: 1; /*Use BLOCK0 to check error record registers, 0 - without check.*/
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};
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};
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uint32_t val;
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uint32_t val;
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} rd_repeat_data3;
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} rd_repeat_data3;
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