diff --git a/components/esp_hw_support/mspi_timing_by_mspi_delay.c b/components/esp_hw_support/mspi_timing_by_mspi_delay.c
index 36771d0603..bc88d88783 100644
--- a/components/esp_hw_support/mspi_timing_by_mspi_delay.c
+++ b/components/esp_hw_support/mspi_timing_by_mspi_delay.c
@@ -347,14 +347,21 @@ static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, u
     uint32_t min_freq = big_num;
     rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
 
-    //BBPLL CALIBRATION START
-    regi2c_ctrl_ll_bbpll_calibration_start();
     for (int pll_mhz_tuning = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MIN; pll_mhz_tuning <= MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX; pll_mhz_tuning += 8) {
+        //bbpll calibration start
+        regi2c_ctrl_ll_bbpll_calibration_start();
+
         /**
          * pll_mhz = xtal_mhz * (oc_div + 4) / (oc_ref_div + 1)
          */
         clk_ll_bbpll_set_frequency_for_mspi_tuning(xtal_freq, pll_mhz_tuning, ((pll_mhz_tuning / 4) - 4), 9);
 
+        //wait calibration done
+        while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
+
+        //bbpll calibration stop
+        regi2c_ctrl_ll_bbpll_calibration_stop();
+
         memset(read_data, 0, MSPI_TIMING_TEST_DATA_LEN);
         if (is_flash) {
             mspi_timing_config_flash_read_data(read_data, MSPI_TIMING_FLASH_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN);
@@ -380,15 +387,15 @@ static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, u
 
     //restore PLL config
     clk_ll_bbpll_set_freq_mhz(previous_config.source_freq_mhz);
+    //bbpll calibration start
+    regi2c_ctrl_ll_bbpll_calibration_start();
+    //set pll
     clk_ll_bbpll_set_config(previous_config.source_freq_mhz, xtal_freq);
-
-    //WAIT CALIBRATION DONE
+    //wait calibration done
     while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
-
-    //BBPLL CALIBRATION STOP
+    //bbpll calibration stop
     regi2c_ctrl_ll_bbpll_calibration_stop();
 
-
     *out_max_freq = max_freq;
     *out_min_freq = min_freq;