kopia lustrzana https://github.com/espressif/esp-idf
refactor(spi_slave_hd): refactor append mode dma_desc struct
wanlei
rodzic
25f729c758
commit
751efec8b6
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -89,12 +89,40 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
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spihost[host_id] = host;
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host->int_spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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host->dma_enabled = (config->dma_chan != SPI_DMA_DISABLED);
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host->append_mode = append_mode;
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if (host->dma_enabled) {
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ret = spicommon_dma_chan_alloc(host_id, config->dma_chan, &actual_tx_dma_chan, &actual_rx_dma_chan);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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//Malloc for all the DMA descriptors
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int dma_desc_ct = (bus_config->max_transfer_sz + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED - 1) / DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
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if (dma_desc_ct == 0) {
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dma_desc_ct = 1; //default to 4k when max is not given
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}
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host->hal.dma_desc_num = dma_desc_ct;
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lldesc_t *orig_dmadesc_tx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
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lldesc_t *orig_dmadesc_rx = heap_caps_malloc(sizeof(lldesc_t) * dma_desc_ct, MALLOC_CAP_DMA);
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host->hal.dmadesc_tx = heap_caps_malloc(sizeof(spi_slave_hd_hal_desc_append_t) * dma_desc_ct, MALLOC_CAP_DEFAULT);
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host->hal.dmadesc_rx = heap_caps_malloc(sizeof(spi_slave_hd_hal_desc_append_t) * dma_desc_ct, MALLOC_CAP_DEFAULT);
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if (!(host->hal.dmadesc_tx && host->hal.dmadesc_rx && orig_dmadesc_tx && orig_dmadesc_rx)) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//Pair each desc to each possible trans
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for (int i = 0; i < dma_desc_ct; i ++) {
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host->hal.dmadesc_tx[i].desc = &orig_dmadesc_tx[i];
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host->hal.dmadesc_rx[i].desc = &orig_dmadesc_rx[i];
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}
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//Get the actual SPI bus transaction size in bytes.
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host->max_transfer_sz = dma_desc_ct * DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
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} else {
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//We're limited to non-DMA transfers: the SPI work registers can hold 64 bytes at most.
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host->max_transfer_sz = 0;
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}
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ret = spicommon_bus_initialize_io(host_id, bus_config, SPICOMMON_BUSFLAG_SLAVE | bus_config->flags, &host->flags);
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@ -104,7 +132,6 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
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gpio_set_direction(config->spics_io_num, GPIO_MODE_INPUT);
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spicommon_cs_initialize(host_id, config->spics_io_num, 0,
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!(bus_config->flags & SPICOMMON_BUSFLAG_NATIVE_PINS));
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host->append_mode = append_mode;
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spi_slave_hd_hal_config_t hal_config = {
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.host_id = host_id,
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@ -119,23 +146,6 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
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.rx_lsbfirst = (config->flags & SPI_SLAVE_HD_TXBIT_LSBFIRST),
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};
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if (host->dma_enabled) {
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//Malloc for all the DMA descriptors
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uint32_t total_desc_size = spi_slave_hd_hal_get_total_desc_size(&host->hal, bus_config->max_transfer_sz);
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host->hal.dmadesc_tx = heap_caps_malloc(total_desc_size, MALLOC_CAP_DMA);
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host->hal.dmadesc_rx = heap_caps_malloc(total_desc_size, MALLOC_CAP_DMA);
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if (!host->hal.dmadesc_tx || !host->hal.dmadesc_rx) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//Get the actual SPI bus transaction size in bytes.
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host->max_transfer_sz = spi_salve_hd_hal_get_max_bus_size(&host->hal);
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} else {
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//We're limited to non-DMA transfers: the SPI work registers can hold 64 bytes at most.
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host->max_transfer_sz = 0;
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}
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//Init the hal according to the hal_config set above
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spi_slave_hd_hal_init(&host->hal, &hal_config);
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@ -232,21 +242,21 @@ esp_err_t spi_slave_hd_deinit(spi_host_device_t host_id)
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if (host->rx_ret_queue) vQueueDelete(host->rx_ret_queue);
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if (host->tx_cnting_sem) vSemaphoreDelete(host->tx_cnting_sem);
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if (host->rx_cnting_sem) vSemaphoreDelete(host->rx_cnting_sem);
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if (host) {
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free(host->hal.dmadesc_tx);
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free(host->hal.dmadesc_rx);
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esp_intr_free(host->intr);
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esp_intr_free(host->intr_dma);
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esp_intr_free(host->intr);
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esp_intr_free(host->intr_dma);
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#ifdef CONFIG_PM_ENABLE
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if (host->pm_lock) {
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esp_pm_lock_release(host->pm_lock);
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esp_pm_lock_delete(host->pm_lock);
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}
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#endif
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if (host->pm_lock) {
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esp_pm_lock_release(host->pm_lock);
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esp_pm_lock_delete(host->pm_lock);
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}
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#endif
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spicommon_periph_free(host_id);
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if (host->dma_enabled) {
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free(host->hal.dmadesc_tx->desc);
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free(host->hal.dmadesc_rx->desc);
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free(host->hal.dmadesc_tx);
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free(host->hal.dmadesc_rx);
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spicommon_dma_chan_free(host_id);
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}
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free(host);
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@ -62,7 +62,7 @@ extern "C" {
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* this structure inherits DMA descriptor, with a pointer to the transaction descriptor passed from users.
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*/
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typedef struct {
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lldesc_t desc; ///< DMA descriptor
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lldesc_t *desc; ///< DMA descriptor
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void *arg; ///< This points to the transaction descriptor user passed in
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} spi_slave_hd_hal_desc_append_t;
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@ -105,13 +105,11 @@ typedef struct {
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spi_slave_hd_hal_desc_append_t *tx_cur_desc; ///< Current TX DMA descriptor that could be linked (set up).
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spi_slave_hd_hal_desc_append_t *tx_dma_head; ///< Head of the linked TX DMA descriptors which are not used by hardware
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spi_slave_hd_hal_desc_append_t *tx_dma_tail; ///< Tail of the linked TX DMA descriptors which are not used by hardware
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spi_slave_hd_hal_desc_append_t tx_dummy_head; ///< Dummy descriptor for ``tx_dma_head`` to start
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uint32_t tx_used_desc_cnt; ///< Number of the TX descriptors that have been setup
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uint32_t tx_recycled_desc_cnt; ///< Number of the TX descriptors that could be recycled
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spi_slave_hd_hal_desc_append_t *rx_cur_desc; ///< Current RX DMA descriptor that could be linked (set up).
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spi_slave_hd_hal_desc_append_t *rx_dma_head; ///< Head of the linked RX DMA descriptors which are not used by hardware
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spi_slave_hd_hal_desc_append_t *rx_dma_tail; ///< Tail of the linked RX DMA descriptors which are not used by hardware
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spi_slave_hd_hal_desc_append_t rx_dummy_head; ///< Dummy descriptor for ``rx_dma_head`` to start
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uint32_t rx_used_desc_cnt; ///< Number of the RX descriptors that have been setup
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uint32_t rx_recycled_desc_cnt; ///< Number of the RX descriptors that could be recycled
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@ -129,23 +127,6 @@ typedef struct {
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*/
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void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_hal_config_t *hal_config);
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/**
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* @brief Get the size of one DMA descriptor
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*
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* @param hal Context of the HAL layer
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* @param bus_size SPI bus maximum transfer size, in bytes.
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* @return Total size needed for all the DMA descriptors
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*/
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uint32_t spi_slave_hd_hal_get_total_desc_size(spi_slave_hd_hal_context_t *hal, uint32_t bus_size);
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/**
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* @brief Get the actual bus size
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*
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* @param hal Context of the HAL layer
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* @return Actual bus transaction size
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*/
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uint32_t spi_salve_hd_hal_get_max_bus_size(spi_slave_hd_hal_context_t *hal);
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/**
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* @brief Check and clear signal of one event
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*
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -63,12 +63,10 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h
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hal->tx_dma_chan = hal_config->tx_dma_chan;
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hal->rx_dma_chan = hal_config->rx_dma_chan;
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hal->append_mode = hal_config->append_mode;
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hal->rx_cur_desc = hal->dmadesc_rx;
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hal->tx_cur_desc = hal->dmadesc_tx;
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STAILQ_NEXT(&hal->tx_dummy_head.desc, qe) = &hal->dmadesc_tx->desc;
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hal->tx_dma_head = &hal->tx_dummy_head;
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STAILQ_NEXT(&hal->rx_dummy_head.desc, qe) = &hal->dmadesc_rx->desc;
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hal->rx_dma_head = &hal->rx_dummy_head;
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hal->rx_cur_desc = hal->dmadesc_rx;
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hal->tx_dma_head = hal->dmadesc_tx + hal->dma_desc_num -1;
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hal->rx_dma_head = hal->dmadesc_rx + hal->dma_desc_num -1;
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//Configure slave
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if (hal_config->dma_enabled) {
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@ -119,26 +117,9 @@ void spi_slave_hd_hal_init(spi_slave_hd_hal_context_t *hal, const spi_slave_hd_h
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spi_ll_slave_set_seg_mode(hal->dev, true);
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}
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uint32_t spi_salve_hd_hal_get_max_bus_size(spi_slave_hd_hal_context_t *hal)
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{
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return hal->dma_desc_num * LLDESC_MAX_NUM_PER_DESC;
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}
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uint32_t spi_slave_hd_hal_get_total_desc_size(spi_slave_hd_hal_context_t *hal, uint32_t bus_size)
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{
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//See how many dma descriptors we need
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int dma_desc_ct = (bus_size + LLDESC_MAX_NUM_PER_DESC - 1) / LLDESC_MAX_NUM_PER_DESC;
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if (dma_desc_ct == 0) {
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dma_desc_ct = 1; //default to 4k when max is not given
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}
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hal->dma_desc_num = dma_desc_ct;
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return hal->dma_desc_num * sizeof(spi_slave_hd_hal_desc_append_t);
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}
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void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, size_t len)
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{
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lldesc_setup_link(&hal->dmadesc_rx->desc, out_buf, len, true);
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lldesc_setup_link(hal->dmadesc_rx->desc, out_buf, len, true);
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spi_ll_dma_rx_fifo_reset(hal->dev);
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spi_dma_ll_rx_reset(hal->dma_in, hal->rx_dma_chan);
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@ -147,12 +128,12 @@ void spi_slave_hd_hal_rxdma(spi_slave_hd_hal_context_t *hal, uint8_t *out_buf, s
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD7);
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spi_ll_dma_rx_enable(hal->dev, 1);
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spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, &hal->dmadesc_rx->desc);
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spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, hal->dmadesc_rx->desc);
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}
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void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len)
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{
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lldesc_setup_link(&hal->dmadesc_tx->desc, data, len, false);
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lldesc_setup_link(hal->dmadesc_tx->desc, data, len, false);
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spi_ll_dma_tx_fifo_reset(hal->dev);
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spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan);
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@ -161,7 +142,7 @@ void spi_slave_hd_hal_txdma(spi_slave_hd_hal_context_t *hal, uint8_t *data, size
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spi_ll_clear_intr(hal->dev, SPI_LL_INTR_CMD8);
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spi_ll_dma_tx_enable(hal->dev, 1);
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spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, &hal->dmadesc_tx->desc);
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spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, hal->dmadesc_tx->desc);
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}
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static spi_ll_intr_t get_event_intr(spi_slave_hd_hal_context_t *hal, spi_event_t ev)
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@ -257,66 +238,43 @@ int spi_slave_hd_hal_get_rxlen(spi_slave_hd_hal_context_t *hal)
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int spi_slave_hd_hal_rxdma_seg_get_len(spi_slave_hd_hal_context_t *hal)
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{
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lldesc_t *desc = &hal->dmadesc_rx->desc;
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lldesc_t *desc = hal->dmadesc_rx->desc;
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return lldesc_get_received_len(desc, NULL);
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}
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bool spi_slave_hd_hal_get_tx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans)
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{
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if ((uint32_t)&hal->tx_dma_head->desc == spi_dma_ll_get_out_eof_desc_addr(hal->dma_out, hal->tx_dma_chan)) {
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uint32_t desc_now = spi_dma_ll_get_out_eof_desc_addr(hal->dma_out, hal->tx_dma_chan);
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if ((uint32_t)hal->tx_dma_head->desc == desc_now) {
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return false;
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}
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hal->tx_dma_head = (spi_slave_hd_hal_desc_append_t *)STAILQ_NEXT(&hal->tx_dma_head->desc, qe);
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//find used paired desc-trans by desc addr
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hal->tx_dma_head++;
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if (hal->tx_dma_head >= hal->dmadesc_tx + hal->dma_desc_num) {
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hal->tx_dma_head = hal->dmadesc_tx;
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}
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*out_trans = hal->tx_dma_head->arg;
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hal->tx_recycled_desc_cnt++;
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return true;
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}
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bool spi_slave_hd_hal_get_rx_finished_trans(spi_slave_hd_hal_context_t *hal, void **out_trans, size_t *out_len)
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{
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if ((uint32_t)&hal->rx_dma_head->desc == spi_dma_ll_get_in_suc_eof_desc_addr(hal->dma_in, hal->rx_dma_chan)) {
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uint32_t desc_now = spi_dma_ll_get_in_suc_eof_desc_addr(hal->dma_in, hal->rx_dma_chan);
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if ((uint32_t)hal->rx_dma_head->desc == desc_now) {
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return false;
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}
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hal->rx_dma_head = (spi_slave_hd_hal_desc_append_t *)STAILQ_NEXT(&hal->rx_dma_head->desc, qe);
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*out_trans = hal->rx_dma_head->arg;
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*out_len = hal->rx_dma_head->desc.length;
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hal->rx_recycled_desc_cnt++;
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return true;
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}
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static void spi_slave_hd_hal_link_append_desc(spi_slave_hd_hal_desc_append_t *dmadesc, const void *data, int len, bool isrx, void *arg)
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{
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HAL_ASSERT(len <= LLDESC_MAX_NUM_PER_DESC); //TODO: Add support for transaction with length larger than 4092, IDF-2660
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int n = 0;
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while (len) {
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int dmachunklen = len;
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if (dmachunklen > LLDESC_MAX_NUM_PER_DESC) {
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dmachunklen = LLDESC_MAX_NUM_PER_DESC;
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}
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if (isrx) {
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//Receive needs DMA length rounded to next 32-bit boundary
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dmadesc[n].desc.size = (dmachunklen + 3) & (~3);
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dmadesc[n].desc.length = (dmachunklen + 3) & (~3);
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} else {
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dmadesc[n].desc.size = dmachunklen;
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dmadesc[n].desc.length = dmachunklen;
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}
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dmadesc[n].desc.buf = (uint8_t *)data;
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dmadesc[n].desc.eof = 0;
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dmadesc[n].desc.sosf = 0;
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dmadesc[n].desc.owner = 1;
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dmadesc[n].desc.qe.stqe_next = &dmadesc[n + 1].desc;
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dmadesc[n].arg = arg;
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len -= dmachunklen;
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data += dmachunklen;
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n++;
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//find used paired desc-trans by desc addr
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hal->rx_dma_head++;
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if (hal->rx_dma_head >= hal->dmadesc_rx + hal->dma_desc_num) {
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hal->rx_dma_head = hal->dmadesc_rx;
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}
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dmadesc[n - 1].desc.eof = 1; //Mark last DMA desc as end of stream.
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dmadesc[n - 1].desc.qe.stqe_next = NULL;
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*out_trans = hal->rx_dma_head->arg;
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*out_len = hal->rx_dma_head->desc->length;
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hal->rx_recycled_desc_cnt++;
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return true;
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}
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esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t *data, size_t len, void *arg)
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@ -329,7 +287,8 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
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return ESP_ERR_INVALID_STATE;
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}
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spi_slave_hd_hal_link_append_desc(hal->tx_cur_desc, data, len, false, arg);
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lldesc_setup_link(hal->tx_cur_desc->desc, data, len, false);
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hal->tx_cur_desc->arg = arg;
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if (!hal->tx_dma_started) {
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hal->tx_dma_started = true;
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@ -339,10 +298,10 @@ esp_err_t spi_slave_hd_hal_txdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
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spi_ll_outfifo_empty_clr(hal->dev);
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spi_dma_ll_tx_reset(hal->dma_out, hal->tx_dma_chan);
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spi_ll_dma_tx_enable(hal->dev, 1);
|
||||
spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, &hal->tx_cur_desc->desc);
|
||||
spi_dma_ll_tx_start(hal->dma_out, hal->tx_dma_chan, hal->tx_cur_desc->desc);
|
||||
} else {
|
||||
//there is already a consecutive link
|
||||
STAILQ_NEXT(&hal->tx_dma_tail->desc, qe) = &hal->tx_cur_desc->desc;
|
||||
STAILQ_NEXT(hal->tx_dma_tail->desc, qe) = hal->tx_cur_desc->desc;
|
||||
hal->tx_dma_tail = hal->tx_cur_desc;
|
||||
spi_dma_ll_tx_restart(hal->dma_out, hal->tx_dma_chan);
|
||||
}
|
||||
|
|
@ -369,7 +328,8 @@ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
|
|||
return ESP_ERR_INVALID_STATE;
|
||||
}
|
||||
|
||||
spi_slave_hd_hal_link_append_desc(hal->rx_cur_desc, data, len, false, arg);
|
||||
lldesc_setup_link(hal->rx_cur_desc->desc, data, len, false);
|
||||
hal->rx_cur_desc->arg = arg;
|
||||
|
||||
if (!hal->rx_dma_started) {
|
||||
hal->rx_dma_started = true;
|
||||
|
|
@ -379,10 +339,10 @@ esp_err_t spi_slave_hd_hal_rxdma_append(spi_slave_hd_hal_context_t *hal, uint8_t
|
|||
spi_ll_dma_rx_fifo_reset(hal->dma_in);
|
||||
spi_ll_infifo_full_clr(hal->dev);
|
||||
spi_ll_dma_rx_enable(hal->dev, 1);
|
||||
spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, &hal->rx_cur_desc->desc);
|
||||
spi_dma_ll_rx_start(hal->dma_in, hal->rx_dma_chan, hal->rx_cur_desc->desc);
|
||||
} else {
|
||||
//there is already a consecutive link
|
||||
STAILQ_NEXT(&hal->rx_dma_tail->desc, qe) = &hal->rx_cur_desc->desc;
|
||||
STAILQ_NEXT(hal->rx_dma_tail->desc, qe) = hal->rx_cur_desc->desc;
|
||||
hal->rx_dma_tail = hal->rx_cur_desc;
|
||||
spi_dma_ll_rx_restart(hal->dma_in, hal->rx_dma_chan);
|
||||
}
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue