From 74f010ddfd60c1dcf8696bfd9eaa1587b7e4fcb4 Mon Sep 17 00:00:00 2001 From: Gustavo Henrique Nihei Date: Fri, 21 May 2021 11:15:55 -0300 Subject: [PATCH] spi_slave: Fix MOSI/MISO enable on transaction preparation MOSI and MISO enablement were conditioned to the existence of TX and RX buffers, respectively. This is valid for the SPI Master, but for the SPI Slave the opposite is expected. --- components/hal/spi_slave_hal_iram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/hal/spi_slave_hal_iram.c b/components/hal/spi_slave_hal_iram.c index 5fb3f4dd1a..bf43561478 100644 --- a/components/hal/spi_slave_hal_iram.c +++ b/components/hal/spi_slave_hal_iram.c @@ -71,8 +71,8 @@ void spi_slave_hal_prepare_data(const spi_slave_hal_context_t *hal) spi_ll_slave_set_rx_bitlen(hal->hw, hal->bitlen); spi_ll_slave_set_tx_bitlen(hal->hw, hal->bitlen); - spi_ll_enable_mosi(hal->hw, (hal->tx_buffer == NULL) ? 0 : 1); - spi_ll_enable_miso(hal->hw, (hal->rx_buffer == NULL) ? 0 : 1); + spi_ll_enable_mosi(hal->hw, (hal->rx_buffer == NULL) ? 0 : 1); + spi_ll_enable_miso(hal->hw, (hal->tx_buffer == NULL) ? 0 : 1); } void spi_slave_hal_store_result(spi_slave_hal_context_t *hal)