Merge branch 'bugfix/flash_encyption_80Mflash_40Mram' into 'master'

flash_encryption/psram: fixed the issue that block when flash_encryption_write

See merge request espressif/esp-idf!12177
pull/7261/head
Michael (XIAO Xufeng) 2021-02-05 22:00:26 +08:00
commit 747ac00f9b
6 zmienionych plików z 86 dodań i 2 usunięć

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@ -125,6 +125,7 @@ extern "C" {
//Extra dummy for flash read //Extra dummy for flash read
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2

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@ -507,10 +507,70 @@ out:
} }
#endif // CONFIG_SPI_FLASH_USE_LEGACY_IMPL #endif // CONFIG_SPI_FLASH_USE_LEGACY_IMPL
#if !CONFIG_SPI_FLASH_USE_LEGACY_IMPL
extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
static void IRAM_ATTR flash_rom_init(void)
{
uint32_t freqdiv = 0;
esp_rom_spiflash_read_mode_t read_mode;
#if CONFIG_IDF_TARGET_ESP32
uint32_t dummy_bit = 0;
#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
#endif
#endif//CONFIG_IDF_TARGET_ESP32
#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
freqdiv = 1;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
freqdiv = 2;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
freqdiv = 3;
#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
freqdiv = 4;
#endif
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO
read_mode = ESP_ROM_SPIFLASH_QIO_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT
read_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_DIO
read_mode = ESP_ROM_SPIFLASH_DIO_MODE;
#elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT
read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
#endif
#if CONFIG_IDF_TARGET_ESP32
g_rom_spiflash_dummy_len_plus[1] = dummy_bit;
#else
spi_dummy_len_fix(1, freqdiv);
#endif //CONFIG_IDF_TARGET_ESP32
#if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
spi_common_set_dummy_output(read_mode);
#endif //!CONFIG_IDF_TARGET_ESP32S2
esp_rom_spiflash_config_readmode(read_mode);
esp_rom_spiflash_config_clk(freqdiv, 1);
}
#else
static void IRAM_ATTR flash_rom_init(void)
{
return;
}
#endif // !CONFIG_SPI_FLASH_USE_LEGACY_IMPL
esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size) esp_err_t IRAM_ATTR spi_flash_write_encrypted(size_t dest_addr, const void *src, size_t size)
{ {
esp_err_t err = ESP_OK; esp_err_t err = ESP_OK;
flash_rom_init();
const spi_flash_guard_funcs_t *guard = spi_flash_guard_get(); const spi_flash_guard_funcs_t *guard = spi_flash_guard_get();
CHECK_WRITE_ADDRESS(dest_addr, size); CHECK_WRITE_ADDRESS(dest_addr, size);
if ((dest_addr % 16) != 0) { if ((dest_addr % 16) != 0) {
@ -757,6 +817,7 @@ out:
esp_err_t IRAM_ATTR spi_flash_read_encrypted(size_t src, void *dstv, size_t size) esp_err_t IRAM_ATTR spi_flash_read_encrypted(size_t src, void *dstv, size_t size)
{ {
flash_rom_init();
if (src + size > g_rom_flashchip.chip_size) { if (src + size > g_rom_flashchip.chip_size) {
return ESP_ERR_INVALID_SIZE; return ESP_ERR_INVALID_SIZE;
} }

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@ -462,6 +462,14 @@ UT_020:
- Example_SPI_Multi_device - Example_SPI_Multi_device
- psram - psram
UT_021:
extends: .unit_test_32_template
parallel: 2
tags:
- ESP32_IDF
- psram
- UT_T1_FlashEncryption
UT_022: UT_022:
extends: .unit_test_32_template extends: .unit_test_32_template
tags: tags:

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@ -0,0 +1,14 @@
# This config is for ESP32 only (no ESP32-S2/S3 flash encryption support yet, ESP32-C3 has no psram)
CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=spi_flash
TEST_GROUPS=flash_encryption
CONFIG_SECURE_FLASH_ENC_ENABLED=y
CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT=y
CONFIG_SECURE_BOOT_ALLOW_ROM_BASIC=y
CONFIG_SECURE_BOOT_ALLOW_JTAG=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_DEC=y
CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE=y
CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED=y
CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_ESPTOOLPY_FLASHFREQ_80M=y

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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32" CONFIG_IDF_TARGET="esp32"
TEST_EXCLUDE_COMPONENTS=libsodium bt app_update driver esp32 esp_ipc esp_pm esp_system esp_timer mbedtls spi_flash test_utils heap pthread soc experimental_cpp_component esp-tls TEST_EXCLUDE_COMPONENTS=libsodium bt app_update driver esp32 esp_ipc esp_pm esp_system esp_timer mbedtls spi_flash test_utils heap pthread soc experimental_cpp_component esp-tls freertos sdmmc
CONFIG_ESP32_SPIRAM_SUPPORT=y CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_OCCUPY_NO_HOST=y CONFIG_SPIRAM_OCCUPY_NO_HOST=y

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@ -1,5 +1,5 @@
CONFIG_IDF_TARGET="esp32" CONFIG_IDF_TARGET="esp32"
TEST_COMPONENTS=driver TEST_COMPONENTS=driver freertos sdmmc
CONFIG_ESP32_SPIRAM_SUPPORT=y CONFIG_ESP32_SPIRAM_SUPPORT=y
CONFIG_ESP_INT_WDT_TIMEOUT_MS=800 CONFIG_ESP_INT_WDT_TIMEOUT_MS=800
CONFIG_SPIRAM_OCCUPY_NO_HOST=y CONFIG_SPIRAM_OCCUPY_NO_HOST=y