kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/coverity_scan_fix_driver' into 'master'
fix some driver "bugs" found by Coverity Scan Closes IDF-4776 See merge request espressif/esp-idf!17566pull/8755/head
morris
commit
6be28e832b
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@ -789,7 +789,7 @@ static esp_err_t process_checksum(bootloader_sha256_handle_t sha_handle, uint32_
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length = length - unpadded_length;
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// Verify checksum
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WORD_ALIGNED_ATTR uint8_t buf[16];
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WORD_ALIGNED_ATTR uint8_t buf[16] = {0};
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if (!skip_check_checksum || sha_handle != NULL) {
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CHECK_ERR(bootloader_flash_read(data->start_addr + unpadded_length, buf, length, true));
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}
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@ -3,7 +3,6 @@ idf_build_get_property(target IDF_TARGET)
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set(srcs
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"gpio.c"
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"gptimer.c"
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"timer_legacy.c"
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"i2c.c"
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"ledc.c"
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"legacy_new_driver_coexist.c"
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@ -19,6 +18,9 @@ set(srcs
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"spi_bus_lock.c"
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"uart.c")
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# deprecated source files
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list(APPEND srcs "deprecated/timer_legacy.c")
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set(includes "include" "deprecated")
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if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target}/include")
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list(APPEND includes "${target}/include")
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@ -51,7 +53,7 @@ if(CONFIG_SOC_RMT_SUPPORTED)
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endif()
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if(CONFIG_SOC_PCNT_SUPPORTED)
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list(APPEND srcs "pcnt_legacy.c" "pulse_cnt.c")
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list(APPEND srcs "pulse_cnt.c" "deprecated/pcnt_legacy.c")
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endif()
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if(CONFIG_SOC_SDMMC_HOST_SUPPORTED)
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@ -64,7 +66,7 @@ endif()
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if(CONFIG_SOC_TEMP_SENSOR_SUPPORTED)
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list(APPEND srcs "temperature_sensor.c"
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"rtc_temperature_legacy.c")
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"deprecated/rtc_temperature_legacy.c")
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endif()
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if(CONFIG_SOC_TWAI_SUPPORTED)
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@ -392,7 +392,7 @@ esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
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esp_err_t gpio_reset_pin(gpio_num_t gpio_num)
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{
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assert(gpio_num >= 0 && GPIO_IS_VALID_GPIO(gpio_num));
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assert(GPIO_IS_VALID_GPIO(gpio_num));
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gpio_config_t cfg = {
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.pin_bit_mask = BIT64(gpio_num),
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.mode = GPIO_MODE_DISABLE,
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@ -428,7 +428,7 @@ static esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_sou
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timer_ll_set_clock_prescale(timer->hal.dev, timer_id, prescale);
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timer->resolution_hz = counter_src_hz / prescale; // this is the real resolution
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if (timer->resolution_hz != resolution_hz) {
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ESP_LOGW(TAG, "resolution lost, expect %ul, real %ul", resolution_hz, timer->resolution_hz);
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ESP_LOGW(TAG, "resolution lost, expect %u, real %u", resolution_hz, timer->resolution_hz);
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}
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return ret;
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}
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@ -1210,12 +1210,12 @@ static void i2s_mode_identify(i2s_port_t i2s_num, const i2s_config_t *i2s_config
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static esp_err_t i2s_config_transfer(i2s_port_t i2s_num, const i2s_config_t *i2s_config)
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{
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/* Convert legacy configuration into general part of slot and clock configuration */
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i2s_slot_config_t slot_cfg;
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i2s_slot_config_t slot_cfg = {};
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slot_cfg.mode = p_i2s[i2s_num]->mode;
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slot_cfg.data_bit_width = i2s_config->bits_per_sample;
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slot_cfg.slot_bit_width = (int)i2s_config->bits_per_chan < (int)i2s_config->bits_per_sample ?
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i2s_config->bits_per_sample : i2s_config->bits_per_chan;
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i2s_clk_config_t clk_cfg;
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i2s_clk_config_t clk_cfg = {};
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clk_cfg.sample_rate_hz = i2s_config->sample_rate;
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clk_cfg.mclk_multiple = i2s_config->mclk_multiple == 0 ? I2S_MCLK_MULTIPLE_256 : i2s_config->mclk_multiple;
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clk_cfg.clk_src = I2S_CLK_D2CLK;
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@ -24,9 +24,11 @@ extern "C" {
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#define GPIO_PIN_COUNT (SOC_GPIO_PIN_COUNT)
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/// Check whether it is a valid GPIO number
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#define GPIO_IS_VALID_GPIO(gpio_num) (((1ULL << (gpio_num)) & SOC_GPIO_VALID_GPIO_MASK) != 0)
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#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \
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(((1ULL << (gpio_num)) & SOC_GPIO_VALID_GPIO_MASK) != 0))
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/// Check whether it can be a valid GPIO number of output mode
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#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)
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#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((gpio_num >= 0) && \
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(((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0))
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typedef intr_handle_t gpio_isr_handle_t;
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@ -597,7 +597,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
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{
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LEDC_ARG_CHECK(ledc_conf, "ledc_conf");
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uint32_t speed_mode = ledc_conf->speed_mode;
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uint32_t gpio_num = ledc_conf->gpio_num;
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int gpio_num = ledc_conf->gpio_num;
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uint32_t ledc_channel = ledc_conf->channel;
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uint32_t timer_select = ledc_conf->timer_sel;
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uint32_t intr_type = ledc_conf->intr_type;
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@ -589,7 +589,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par
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uint32_t rmt_source_clk_hz;
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ESP_RETURN_ON_FALSE(rmt_is_channel_number_valid(channel, mode), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
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ESP_RETURN_ON_FALSE(mem_cnt + channel <= 8 && mem_cnt > 0, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
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ESP_RETURN_ON_FALSE(mem_cnt + channel <= SOC_RMT_CHANNELS_PER_GROUP && mem_cnt > 0, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR);
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ESP_RETURN_ON_FALSE(clk_div > 0, ESP_ERR_INVALID_ARG, TAG, RMT_CLK_DIV_ERROR_STR);
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if (mode == RMT_MODE_TX) {
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@ -726,7 +726,6 @@ esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uin
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ESP_RETURN_ON_FALSE(item, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR);
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ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
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/*Each block has 64 x 32 bits of data*/
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uint8_t mem_cnt = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
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ESP_RETURN_ON_FALSE(mem_cnt * RMT_MEM_ITEM_NUM >= item_num, ESP_ERR_INVALID_ARG, TAG, RMT_WR_MEM_OVF_ERROR_STR);
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rmt_fill_memory(channel, item, item_num, mem_offset);
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@ -746,22 +745,6 @@ esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle)
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return esp_intr_free(handle);
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}
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static int IRAM_ATTR rmt_rx_get_mem_len_in_isr(rmt_channel_t channel)
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{
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int block_num = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, channel);
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int item_block_len = block_num * RMT_MEM_ITEM_NUM;
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volatile rmt_item32_t *data = (rmt_item32_t *)RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
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int idx;
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for (idx = 0; idx < item_block_len; idx++) {
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if (data[idx].duration0 == 0) {
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return idx;
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} else if (data[idx].duration1 == 0) {
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return idx + 1;
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}
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}
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return idx;
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}
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static void IRAM_ATTR rmt_driver_isr_default(void *arg)
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{
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uint32_t status = 0;
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@ -849,7 +832,7 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg)
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rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)];
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if (p_rmt) {
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rmt_ll_rx_enable(rmt_contex.hal.regs, channel, false);
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int item_len = rmt_rx_get_mem_len_in_isr(channel);
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int item_len = rmt_ll_rx_get_memory_writer_offset(rmt_contex.hal.regs, channel);
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rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, channel, RMT_LL_MEM_OWNER_SW);
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if (p_rmt->rx_buf) {
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addr = (rmt_item32_t *)RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32;
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@ -1135,6 +1118,8 @@ esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, i
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ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
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ESP_RETURN_ON_FALSE(rmt_item, ESP_FAIL, TAG, RMT_ADDR_ERROR_STR);
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ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR);
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uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
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ESP_RETURN_ON_FALSE(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP, ESP_ERR_INVALID_STATE, TAG, RMT_MEM_CNT_ERROR_STR);
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#if CONFIG_SPIRAM_USE_MALLOC
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if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
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if (!esp_ptr_internal(rmt_item)) {
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@ -1144,9 +1129,8 @@ esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, i
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}
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#endif
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rmt_obj_t *p_rmt = p_rmt_obj[channel];
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int block_num = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
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int item_block_len = block_num * RMT_MEM_ITEM_NUM;
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int item_sub_len = block_num * RMT_MEM_ITEM_NUM / 2;
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int item_block_len = mem_blocks * RMT_MEM_ITEM_NUM;
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int item_sub_len = mem_blocks * RMT_MEM_ITEM_NUM / 2;
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int len_rem = item_num;
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xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
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// fill the memory block first
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@ -1222,8 +1206,9 @@ esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn)
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ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_TRANSLATOR_NULL_STR);
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ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
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ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
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const uint32_t block_size = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) *
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RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
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uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
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ESP_RETURN_ON_FALSE(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP, ESP_ERR_INVALID_STATE, TAG, RMT_MEM_CNT_ERROR_STR);
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const uint32_t block_size = mem_blocks * RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t);
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if (p_rmt_obj[channel]->tx_buf == NULL) {
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#if !CONFIG_SPIRAM_USE_MALLOC
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p_rmt_obj[channel]->tx_buf = (rmt_item32_t *)malloc(block_size);
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@ -1273,6 +1258,8 @@ esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src
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ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR);
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ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR);
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ESP_RETURN_ON_FALSE(p_rmt_obj[channel]->sample_to_rmt, ESP_FAIL, TAG, RMT_TRANSLATOR_UNINIT_STR);
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uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel);
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ESP_RETURN_ON_FALSE(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP, ESP_ERR_INVALID_STATE, TAG, RMT_MEM_CNT_ERROR_STR);
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#if CONFIG_SPIRAM_USE_MALLOC
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if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) {
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if (!esp_ptr_internal(src)) {
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@ -1283,7 +1270,7 @@ esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src
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#endif
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size_t translated_size = 0;
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rmt_obj_t *p_rmt = p_rmt_obj[channel];
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const uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM;
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const uint32_t item_block_len = mem_blocks * RMT_MEM_ITEM_NUM;
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const uint32_t item_sub_len = item_block_len / 2;
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xSemaphoreTake(p_rmt->tx_sem, portMAX_DELAY);
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p_rmt->sample_to_rmt((void *)src, p_rmt->tx_buf, src_size, item_block_len, &translated_size, &p_rmt->tx_len_rem);
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@ -690,7 +690,9 @@ esp_err_t spicommon_bus_free_io_cfg(const spi_bus_config_t *bus_cfg)
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};
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for (int i = 0; i < sizeof(pin_array)/sizeof(int); i ++) {
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const int io = pin_array[i];
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if (io >= 0 && GPIO_IS_VALID_GPIO(io)) gpio_reset_pin(io);
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if (GPIO_IS_VALID_GPIO(io)) {
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gpio_reset_pin(io);
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}
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}
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return ESP_OK;
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}
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@ -717,7 +719,7 @@ void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num,
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void spicommon_cs_free_io(int cs_gpio_num)
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{
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assert(cs_gpio_num>=0 && GPIO_IS_VALID_GPIO(cs_gpio_num));
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assert(GPIO_IS_VALID_GPIO(cs_gpio_num));
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gpio_reset_pin(cs_gpio_num);
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}
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@ -649,6 +649,8 @@ static void SPI_MASTER_ISR_ATTR spi_intr(void *arg)
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// We stay in the ISR to deal with those transactions of desired device, otherwise nothing will be done, check whether we need to resume some other tasks, or just quit the ISR
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resume_task = spi_bus_lock_bg_check_dev_acq(lock, &desired_dev);
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}
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// sanity check
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assert(desired_dev);
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if (!resume_task) {
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bool dev_has_req = spi_bus_lock_bg_check_dev_req(desired_dev);
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@ -733,7 +735,8 @@ static SPI_MASTER_ISR_ATTR void uninstall_priv_desc(spi_trans_priv_t* trans_buf)
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free((void *)trans_buf->buffer_to_send); //force free, ignore const
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}
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// copy data from temporary DMA-capable buffer back to IRAM buffer and free the temporary one.
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if ((void *)trans_buf->buffer_to_rcv != &trans_desc->rx_data[0] &&
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if (trans_buf->buffer_to_rcv &&
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(void *)trans_buf->buffer_to_rcv != &trans_desc->rx_data[0] &&
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trans_buf->buffer_to_rcv != trans_desc->rx_buffer) { // NOLINT(clang-analyzer-unix.Malloc)
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if (trans_desc->flags & SPI_TRANS_USE_RXDATA) {
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memcpy((uint8_t *) & trans_desc->rx_data[0], trans_buf->buffer_to_rcv, (trans_desc->rxlength + 7) / 8);
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@ -370,6 +370,9 @@ static void SPI_SLAVE_ISR_ATTR spi_intr(void *arg)
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//Grab next transaction
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r = xQueueReceiveFromISR(host->trans_queue, &trans, &do_yield);
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if (r) {
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// sanity check
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assert(trans);
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//enable the interrupt again if there is packet to send
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esp_intr_enable(host->intr);
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@ -64,7 +64,7 @@ typedef struct {
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unsigned int hsync_idle_low: 1; /*!< The hsync signal is low in IDLE state */
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unsigned int vsync_idle_low: 1; /*!< The vsync signal is low in IDLE state */
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unsigned int de_idle_high: 1; /*!< The de signal is high in IDLE state */
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unsigned int pclk_active_pos: 1; /*!< Whether the display data is clocked out on the rising edge of PCLK */
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unsigned int pclk_active_neg: 1; /*!< Whether the display data is clocked out on the falling edge of PCLK */
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unsigned int pclk_idle_high: 1; /*!< The PCLK stays at high level in IDLE phase */
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} flags;
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} esp_lcd_rgb_timing_t;
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@ -254,7 +254,7 @@ static esp_err_t panel_io_spi_tx_color(esp_lcd_panel_io_t *io, int lcd_cmd, cons
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ESP_GOTO_ON_ERROR(ret, err, TAG, "spi transmit (polling) command failed");
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// split to chunks if required:
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// the SPI bus has a maximum transaction size determined by SPI_USR_MOSI_DBITLEN's bit width
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// the SPI bus has a maximum transaction size determined by SPI_LL_DATA_MAX_BIT_LEN
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do {
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size_t chunk_size = color_size;
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@ -266,7 +266,7 @@ static esp_err_t rgb_panel_init(esp_lcd_panel_t *panel)
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rgb_panel->timings.pclk_hz = rgb_panel->resolution_hz / pclk_prescale;
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// pixel clock phase and polarity
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lcd_ll_set_clock_idle_level(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_idle_high);
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lcd_ll_set_pixel_clock_edge(rgb_panel->hal.dev, !rgb_panel->timings.flags.pclk_active_pos);
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lcd_ll_set_pixel_clock_edge(rgb_panel->hal.dev, rgb_panel->timings.flags.pclk_active_neg);
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// enable RGB mode and set data width
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lcd_ll_enable_rgb_mode(rgb_panel->hal.dev, true);
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lcd_ll_set_data_width(rgb_panel->hal.dev, rgb_panel->data_width);
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@ -134,13 +134,22 @@ TEST_CASE("lcd_rgb_panel_one_shot_mode", "[lcd]")
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}
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#if CONFIG_LCD_RGB_ISR_IRAM_SAFE
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TEST_LCD_CALLBACK_ATTR static bool test_rgb_panel_count_in_callback(esp_lcd_panel_handle_t panel, esp_lcd_rgb_panel_event_data_t *edata, void *user_ctx)
|
||||
{
|
||||
uint32_t *count = (uint32_t *)user_ctx;
|
||||
*count = *count + 1;
|
||||
return false;
|
||||
}
|
||||
|
||||
TEST_CASE("lcd_rgb_panel_with_nvs_read_write", "[lcd]")
|
||||
{
|
||||
uint8_t *img = malloc(TEST_IMG_SIZE);
|
||||
TEST_ASSERT_NOT_NULL(img);
|
||||
|
||||
uint32_t callback_calls = 0;
|
||||
|
||||
printf("initialize RGB panel with stream mode\r\n");
|
||||
esp_lcd_panel_handle_t panel_handle = test_rgb_panel_initialization(true, NULL, NULL);
|
||||
esp_lcd_panel_handle_t panel_handle = test_rgb_panel_initialization(true, test_rgb_panel_count_in_callback, &callback_calls);
|
||||
printf("flush one clock block to the LCD\r\n");
|
||||
uint8_t color_byte = esp_random() & 0xFF;
|
||||
int x_start = esp_random() % (TEST_LCD_H_RES - 100);
|
||||
|
|
@ -176,6 +185,8 @@ TEST_CASE("lcd_rgb_panel_with_nvs_read_write", "[lcd]")
|
|||
nvs_close(my_handle);
|
||||
TEST_ESP_OK(nvs_flash_deinit());
|
||||
|
||||
TEST_ASSERT(callback_calls > 50);
|
||||
|
||||
printf("delete RGB panel\r\n");
|
||||
TEST_ESP_OK(esp_lcd_panel_del(panel_handle));
|
||||
free(img);
|
||||
|
|
|
|||
|
|
@ -116,10 +116,3 @@ I2C
|
|||
- ``rmt_set_intr_enable_mask`` and ``rmt_clr_intr_enable_mask`` are removed, as the interrupt is handled by the driver, user doesn't need to take care of it.
|
||||
- ``rmt_set_pin`` is removed, as ``rmt_set_gpio`` can do the same thing.
|
||||
- ``rmt_memory_rw_rst`` is removed, user can use ``rmt_tx_memory_reset`` and ``rmt_rx_memory_reset`` for TX and RX channel respectively.
|
||||
|
||||
.. only:: SOC_LCD_RGB_SUPPORTED
|
||||
|
||||
RGB LCD Driver
|
||||
--------------
|
||||
|
||||
- The `pclk_active_neg` in the RGB timing configuration structure :cpp:type:`esp_lcd_rgb_timing_t` has been changed into `pclk_active_pos`. This was made to change the default PCLK sample moment to **falling** edge. From user side, you don't need to explicitly assign `pclk_active_neg = true` anymore.
|
||||
|
|
|
|||
|
|
@ -83,6 +83,6 @@ I (741) example: Display LVGL Scatter Chart
|
|||
* The frame buffer of RGB panel is located in ESP side (unlike other controller based LCDs, where the frame buffer is located in external chip). As the frame buffer usually consumes much RAM (depends on the LCD resolution and color depth), we recommend to put the frame buffer into PSRAM (like what we do in this example). However, putting frame buffer in PSRAM will limit the PCLK to around 12MHz (due to the bandwidth of PSRAM).
|
||||
* LCD screen drift
|
||||
* Slow down the PCLK frequency
|
||||
* Adjust other timing parameters like PCLK clock edge (by `pclk_active_pos`), sync porches like HBP (by `hsync_back_porch`) according to your LCD spec
|
||||
* Adjust other timing parameters like PCLK clock edge (by `pclk_active_neg`), sync porches like HBP (by `hsync_back_porch`) according to your LCD spec
|
||||
|
||||
For any technical queries, please open an [issue] (https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon.
|
||||
|
|
@ -124,6 +124,7 @@ void app_main(void)
|
|||
.vsync_back_porch = 8,
|
||||
.vsync_front_porch = 4,
|
||||
.vsync_pulse_width = 1,
|
||||
.flags.pclk_active_neg = true,
|
||||
},
|
||||
.flags.fb_in_psram = 1, // allocate frame buffer in PSRAM
|
||||
};
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue