From 699742acc65b49e0452ea7a60b9f7139abc2bcbd Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Thu, 21 May 2020 17:09:27 +1000 Subject: [PATCH] esp32s2: Support bootloader_random_enable() --- .../subproject/main/ld/esp32/bootloader.ld | 1 + .../subproject/main/ld/esp32s2/bootloader.ld | 1 + components/bootloader_support/CMakeLists.txt | 1 + components/bootloader_support/component.mk | 7 +- .../src/bootloader_random.c | 186 +----------------- .../src/bootloader_random_esp32.c | 128 ++++++++++++ .../src/bootloader_random_esp32s2.c | 97 +++++++++ components/hal/esp32s2/include/hal/adc_ll.h | 62 +++++- 8 files changed, 294 insertions(+), 189 deletions(-) create mode 100644 components/bootloader_support/src/bootloader_random_esp32.c create mode 100644 components/bootloader_support/src/bootloader_random_esp32s2.c diff --git a/components/bootloader/subproject/main/ld/esp32/bootloader.ld b/components/bootloader/subproject/main/ld/esp32/bootloader.ld index b9538c75c9..304fbc3987 100644 --- a/components/bootloader/subproject/main/ld/esp32/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32/bootloader.ld @@ -42,6 +42,7 @@ SECTIONS *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libbootloader_support.a:bootloader_efuse_esp32.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld index 8dfbbd3ebd..158fcb36cb 100644 --- a/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32s2/bootloader.ld @@ -29,6 +29,7 @@ SECTIONS *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*) + *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) *libbootloader_support.a:bootloader_efuse_esp32s2.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*) *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*) diff --git a/components/bootloader_support/CMakeLists.txt b/components/bootloader_support/CMakeLists.txt index f61c6081e6..9a180ed66c 100644 --- a/components/bootloader_support/CMakeLists.txt +++ b/components/bootloader_support/CMakeLists.txt @@ -5,6 +5,7 @@ set(srcs "src/bootloader_flash.c" "src/bootloader_mem.c" "src/bootloader_random.c" + "src/bootloader_random_${IDF_TARGET}.c" "src/bootloader_utility.c" "src/esp_image_format.c" "src/flash_encrypt.c" diff --git a/components/bootloader_support/component.mk b/components/bootloader_support/component.mk index 1d678b7a0a..17645261e3 100644 --- a/components/bootloader_support/component.mk +++ b/components/bootloader_support/component.mk @@ -24,9 +24,10 @@ COMPONENT_OBJEXCLUDE := src/bootloader_init.o \ endif COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2.o \ - src/bootloader_flash_config_esp32s3.o \ - src/bootloader_efuse_esp32s2.o \ - src/bootloader_efuse_esp32s3.o \ + src/bootloader_flash_config_esp32s3.o \ + src/bootloader_efuse_esp32s2.o \ + src/bootloader_efuse_esp32s3.o \ + src/bootloader_random_esp32s2.o ifndef CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME ifndef CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c index a5a55d0c37..b7376bf15c 100644 --- a/components/bootloader_support/src/bootloader_random.c +++ b/components/bootloader_support/src/bootloader_random.c @@ -1,4 +1,4 @@ -// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -15,16 +15,6 @@ #include "bootloader_random.h" #include "soc/cpu.h" #include "soc/wdev_reg.h" -#include "soc/rtc_periph.h" -#include "soc/sens_periph.h" -#include "soc/syscon_periph.h" -#include "soc/dport_reg.h" -#include "soc/i2s_periph.h" -#include "esp_log.h" -#include "soc/io_mux_reg.h" -#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 -#include "soc/apb_saradc_reg.h" -#endif #ifndef BOOTLOADER_BUILD #include "esp_system.h" @@ -64,177 +54,3 @@ } } #endif // BOOTLOADER_BUILD - -void bootloader_random_enable(void) -{ - /* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is - never disabled while the CPU is running), this is a "belts and braces" type check. - */ -#ifdef BOOTLOADER_BUILD -#if CONFIG_IDF_TARGET_ESP32S3 - SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_RNG_EN); -#else - DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN); -#endif -#else - periph_module_enable(PERIPH_RNG_MODULE); -#endif // BOOTLOADER_BUILD - - /* Enable SAR ADC in test mode to feed ADC readings of the 1.1V - reference via I2S into the RNG entropy input. - - Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M) - in early bootloader startup must have been made. - */ -#if CONFIG_IDF_TARGET_ESP32 - SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S); - SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); - SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); - -#ifdef BOOTLOADER_BUILD - DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); -#else - periph_module_enable(PERIPH_I2S0_MODULE); -#endif // BOOTLOADER_BUILD - CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP); - CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP); -#elif CONFIG_IDF_TARGET_ESP32S2 - /* Disable IO1 digital function for random function. */ - PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U); - PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U); - PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U); - WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF); - - SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); - DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); - CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP); -#elif CONFIG_IDF_TARGET_ESP32S3 - /* Disable IO1 digital function for random function. */ - PIN_INPUT_DISABLE(PERIPHS_IO_MUX_GPIO1_U); - PIN_PULLDWN_DIS(PERIPHS_IO_MUX_GPIO1_U); - PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO1_U); - WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xFFFFFFFF); - - SET_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); - SET_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_I2S0_CLK_EN); - CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); - CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_START_TOP); -#endif - - // Test pattern configuration byte 0xAD: - //--[7:4] channel_sel: 10-->en_test - //--[3:2] bit_width : 3-->12bit - //--[1:0] atten : 1-->3dB attenuation -#if CONFIG_IDF_TARGET_ESP32 - WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); - WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); - WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); - WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); - SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); - SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); - SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); - WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); - WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); - WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); - SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); - SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); -#endif - -#if CONFIG_IDF_TARGET_ESP32 - SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX); - SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S); - SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */ - SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S); - SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S); - SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL); - CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL); - SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S); - SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S); -#elif CONFIG_IDF_TARGET_ESP32S2 - SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_SAR_CLK_DIV, 4, APB_SARADC_SAR_CLK_DIV_S); - SET_PERI_REG_BITS(APB_SARADC_FSM_REG, APB_SARADC_RSTB_WAIT, 8, APB_SARADC_RSTB_WAIT_S); /* was 1 */ - SET_PERI_REG_BITS(APB_SARADC_CTRL_REG, APB_SARADC_WORK_MODE, 0, APB_SARADC_WORK_MODE_S); - SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL); - CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_SAR_SEL); - SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S); - SET_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_DATA_TO_I2S); -#endif -#if !CONFIG_IDF_TARGET_ESP32S3 - CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); - SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); - SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); - SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); - SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); -#endif -} - -void bootloader_random_disable(void) -{ -#if !CONFIG_IDF_TARGET_ESP32S3 - /* Reset some i2s configuration (possibly redundant as we reset entire - I2S peripheral further down). */ - CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); - SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET); - CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET); - CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); - CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); - CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); - CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); -#endif - /* Disable i2s clock */ -#ifdef BOOTLOADER_BUILD -#if CONFIG_IDF_TARGET_ESP32S3 - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_I2S0_CLK_EN); -#else - DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); -#endif -#else - periph_module_disable(PERIPH_I2S0_MODULE); -#endif // BOOTLOADER_BUILD - - /* Restore SYSCON mode registers */ -#if CONFIG_IDF_TARGET_ESP32 - CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); - CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); -#endif - -#if CONFIG_IDF_TARGET_ESP32 - /* Restore SAR ADC mode */ - CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); - CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX - | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); - SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); -#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 - CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL1_REG, SENS_SAR2_EN_TEST); - CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG, APB_SARADC_SAR_SEL | APB_SARADC_DATA_TO_I2S); - SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); -#endif - -#if CONFIG_IDF_TARGET_ESP32 - SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S); -#endif - - /* Reset i2s peripheral */ -#ifdef BOOTLOADER_BUILD -#if CONFIG_IDF_TARGET_ESP32S3 - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_I2S0_RST); - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_I2S0_RST); -#else - DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); - DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); -#endif -#else - periph_module_reset(PERIPH_I2S0_MODULE); -#endif - -#if CONFIG_IDF_TARGET_ESP32 - /* Disable pull supply voltage to SAR ADC */ - CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); - SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S); -#endif -} diff --git a/components/bootloader_support/src/bootloader_random_esp32.c b/components/bootloader_support/src/bootloader_random_esp32.c new file mode 100644 index 0000000000..0a17d764e9 --- /dev/null +++ b/components/bootloader_support/src/bootloader_random_esp32.c @@ -0,0 +1,128 @@ +// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "sdkconfig.h" +#include "bootloader_random.h" +#include "soc/rtc_periph.h" +#include "soc/sens_periph.h" +#include "soc/syscon_periph.h" +#include "soc/dport_reg.h" +#include "soc/i2s_periph.h" +#include "esp_log.h" +#include "soc/io_mux_reg.h" + +#ifndef BOOTLOADER_BUILD +#include "driver/periph_ctrl.h" +#endif + +void bootloader_random_enable(void) +{ + /* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is + never disabled while the CPU is running), this is a "belts and braces" type check. + */ +#ifdef BOOTLOADER_BUILD + DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN); +#else + periph_module_enable(PERIPH_RNG_MODULE); +#endif // BOOTLOADER_BUILD + + /* Enable SAR ADC in test mode to feed ADC readings of the 1.1V + reference via I2S into the RNG entropy input. + + Note: I2S requires the PLL to be running, so the call to rtc_set_cpu_freq(CPU_80M) + in early bootloader startup must have been made. + */ + SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 2, RTC_CNTL_DTEST_RTC_S); + SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); + SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); + +#ifdef BOOTLOADER_BUILD + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); +#else + periph_module_enable(PERIPH_I2S0_MODULE); +#endif // BOOTLOADER_BUILD + CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP); + CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP); + + // Test pattern configuration byte 0xAD: + //--[7:4] channel_sel: 10-->en_test + //--[3:2] bit_width : 3-->12bit + //--[1:0] atten : 1-->3dB attenuation + WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); + WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); + WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); + WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); + SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 3, SENS_FORCE_XPD_SAR_S); + SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); + SET_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); + + SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX); + SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_CLK_DIV, 4, SYSCON_SARADC_SAR_CLK_DIV_S); + SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_RSTB_WAIT, 8, SYSCON_SARADC_RSTB_WAIT_S); /* was 1 */ + SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 10, SYSCON_SARADC_START_WAIT_S); + SET_PERI_REG_BITS(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_WORK_MODE, 0, SYSCON_SARADC_WORK_MODE_S); + SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR_SEL); + CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_SAR_SEL); + SET_PERI_REG_BITS(I2S_SAMPLE_RATE_CONF_REG(0), I2S_RX_BCK_DIV_NUM, 20, I2S_RX_BCK_DIV_NUM_S); + SET_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_DATA_TO_I2S); + + CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); + SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); + SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); + SET_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); + SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); +} + +void bootloader_random_disable(void) +{ + /* Reset some i2s configuration (possibly redundant as we reset entire + I2S peripheral further down). */ + CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_START); + SET_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET); + CLEAR_PERI_REG_MASK(I2S_CONF_REG(0), I2S_RX_RESET); + CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_CAMERA_EN); + CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_LCD_EN); + CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE_TEST_EN); + CLEAR_PERI_REG_MASK(I2S_CONF2_REG(0), I2S_DATA_ENABLE); + + /* Disable i2s clock */ +#ifdef BOOTLOADER_BUILD + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN); +#else + periph_module_disable(PERIPH_I2S0_MODULE); +#endif // BOOTLOADER_BUILD + + /* Restore SYSCON mode registers */ + CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DIG_FORCE); + CLEAR_PERI_REG_MASK(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_DIG_FORCE); + + /* Restore SAR ADC mode */ + CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST); + CLEAR_PERI_REG_MASK(SYSCON_SARADC_CTRL_REG, SYSCON_SARADC_SAR2_MUX + | SYSCON_SARADC_SAR_SEL | SYSCON_SARADC_DATA_TO_I2S); + SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); + + SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S); + + /* Reset i2s peripheral */ +#ifdef BOOTLOADER_BUILD + DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); + DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST); +#else + periph_module_reset(PERIPH_I2S0_MODULE); +#endif + + /* Disable pull supply voltage to SAR ADC */ + CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC); + SET_PERI_REG_BITS(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_DTEST_RTC, 0, RTC_CNTL_DTEST_RTC_S); +} diff --git a/components/bootloader_support/src/bootloader_random_esp32s2.c b/components/bootloader_support/src/bootloader_random_esp32s2.c new file mode 100644 index 0000000000..09380990b3 --- /dev/null +++ b/components/bootloader_support/src/bootloader_random_esp32s2.c @@ -0,0 +1,97 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#include "sdkconfig.h" +#include "bootloader_random.h" +#include "soc/rtc_periph.h" +#include "soc/sens_periph.h" +#include "soc/syscon_periph.h" +#include "soc/dport_reg.h" +#include "soc/i2s_periph.h" +#include "esp_log.h" +#include "soc/io_mux_reg.h" +#include "soc/apb_saradc_reg.h" +#include "regi2c_ctrl.h" +#include "hal/adc_ll.h" + +#ifndef BOOTLOADER_BUILD +#include "driver/periph_ctrl.h" +#endif + +void bootloader_random_enable(void) +{ + /* Ensure the Wifi clock for RNG modiule is enabled following a soft reset. This should always be the case already + (this clock is never disabled while the CPU is running), this is a "belt and braces" type check. + */ +#ifdef BOOTLOADER_BUILD + DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN); +#else + periph_module_enable(PERIPH_RNG_MODULE); +#endif // BOOTLOADER_BUILD + + // Enable SAR ADC to read a disconnected input for additional entropy + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN0_REG,DPORT_APB_SARADC_CLK_EN); + + REG_SET_FIELD(APB_SARADC_APB_ADC_CLKM_CONF_REG, APB_SARADC_CLK_SEL, 2); + + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PD_M); + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_SAR_I2C_FORCE_PU_M); + CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, BIT(18)); + SET_PERI_REG_MASK(ADC_LL_ANA_CONFIG2_REG, BIT(16)); + + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 0x4); + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 0x4); + + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENCAL_REF_ADDR, 1); + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 1); + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0); + + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR1_PATT_LEN, 0); + WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG,0xafffffff); // set adc1 channel & bitwidth & atten + + REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SAR2_PATT_LEN, 0); + WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG,0xafffffff); //set adc2 channel & bitwidth & atten + + SET_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG,SENS_SAR1_DIG_FORCE); + + REG_SET_FIELD(APB_SARADC_CTRL_REG,APB_SARADC_WORK_MODE, 1); + + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_MEAS_NUM_LIMIT); + + REG_SET_FIELD(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 3); + + SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_SEL); + + REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_TARGET, 100); + + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL_REG,APB_SARADC_START_FORCE); + + SET_PERI_REG_MASK(APB_SARADC_CTRL2_REG,APB_SARADC_TIMER_EN); +} + +void bootloader_random_disable(void) +{ + /* Restore internal I2C bus state */ + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR1_DREF_ADDR, 0x1); + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SAR2_DREF_ADDR, 0x1); + + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENCAL_REF_ADDR, 0); + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_TSENS_ADDR, 0); + REGI2C_WRITE_MASK(ADC_LL_I2C_ADC, ADC_LL_SARADC_ENT_RTC_ADDR, 0); + + /* Restore SARADC to default mode */ + CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_MUX_REG, SENS_SAR1_DIG_FORCE); + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN0_REG, DPORT_APB_SARADC_CLK_EN); + SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S); + CLEAR_PERI_REG_MASK(APB_SARADC_CTRL2_REG, APB_SARADC_TIMER_EN); +} diff --git a/components/hal/esp32s2/include/hal/adc_ll.h b/components/hal/esp32s2/include/hal/adc_ll.h index 95daff46f2..530f67e6e0 100644 --- a/components/hal/esp32s2/include/hal/adc_ll.h +++ b/components/hal/esp32s2/include/hal/adc_ll.h @@ -69,6 +69,66 @@ typedef enum { ADC2_CTRL_FORCE_DIG = 6, /*!