From 68608f804c51e41ace6f73c94224d57cdb2df7d2 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Tue, 29 Dec 2020 13:20:24 +0800 Subject: [PATCH] esp32c3: Misc fixes needed to build & run --- .../src/esp32c3/bootloader_esp32c3.c | 3 +- components/driver/CMakeLists.txt | 3 +- components/esp_common/src/task_wdt.c | 7 +- .../esp32c3/gdbstub_target_config.h | 15 + components/esp_pm/CMakeLists.txt | 8 + components/esp_system/CMakeLists.txt | 1 - components/esp_system/intr_alloc.c | 7 + components/esp_system/sleep_modes.c | 4 +- components/hal/CMakeLists.txt | 8 +- components/hal/esp32c3/adc_hal.c | 2 + components/hal/esp32c3/include/hal/i2s_ll.h | 912 ++++++++++++++++++ components/soc/esp32c3/CMakeLists.txt | 1 - components/ulp/CMakeLists.txt | 18 +- components/wifi_provisioning/CMakeLists.txt | 5 + 14 files changed, 976 insertions(+), 18 deletions(-) create mode 100644 components/esp_gdbstub/esp32c3/gdbstub_target_config.h create mode 100644 components/hal/esp32c3/include/hal/i2s_ll.h diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index e3129c84e8..c3eec1e440 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -44,6 +44,7 @@ #include "bootloader_mem.h" #include "regi2c_ctrl.h" #include "bootloader_console.h" +#include "bootloader_flash_priv.h" static const char *TAG = "boot.esp32c3"; @@ -226,7 +227,7 @@ static void wdt_reset_cpu0_info_enable(void) static void wdt_reset_info_dump(int cpu) { // TODO ESP32-C3 IDF-2118 - ESP_LOGE(TAG, "WDT reset info dump is not supported yet", cpu_name); + ESP_LOGE(TAG, "WDT reset info dump is not supported yet"); } static void bootloader_check_wdt_reset(void) diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 83d232bf6e..2c37813d1a 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -66,8 +66,7 @@ endif() if(IDF_TARGET STREQUAL "esp32c3") list(APPEND srcs "spi_slave_hd.c" - "esp32c3/adc.c" - "esp32c3/rtc_tempsensor.c") + "esp32c3/adc.c") endif() idf_component_register(SRCS "${srcs}" diff --git a/components/esp_common/src/task_wdt.c b/components/esp_common/src/task_wdt.c index f2b3957292..5c73e20774 100644 --- a/components/esp_common/src/task_wdt.c +++ b/components/esp_common/src/task_wdt.c @@ -181,15 +181,18 @@ static void task_wdt_isr(void *arg) esp_reset_reason_set_hint(ESP_RST_TASK_WDT); abort(); } else { + +#if !CONFIG_IDF_TARGET_ESP32C3 // TODO ESP32-C3 add backtrace printing support IDF-2285 int current_core = xPortGetCoreID(); //Print backtrace of current core ESP_EARLY_LOGE(TAG, "Print CPU %d (current core) backtrace", current_core); esp_backtrace_print(100); - #if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE //Print backtrace of other core ESP_EARLY_LOGE(TAG, "Print CPU %d backtrace", !current_core); esp_crosscore_int_send_print_backtrace(!current_core); - #endif +#endif +#endif } portEXIT_CRITICAL_ISR(&twdt_spinlock); diff --git a/components/esp_gdbstub/esp32c3/gdbstub_target_config.h b/components/esp_gdbstub/esp32c3/gdbstub_target_config.h new file mode 100644 index 0000000000..527dc5e2da --- /dev/null +++ b/components/esp_gdbstub/esp32c3/gdbstub_target_config.h @@ -0,0 +1,15 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once diff --git a/components/esp_pm/CMakeLists.txt b/components/esp_pm/CMakeLists.txt index b802986ec1..f57c21df69 100644 --- a/components/esp_pm/CMakeLists.txt +++ b/components/esp_pm/CMakeLists.txt @@ -1,3 +1,11 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "esp32c3") + # TODO ESP32-C3 IDF-2107 - include the headers to avoid compile errors, no functions available to link... + idf_component_register(SRCS "pm_impl_riscv_temp.c" INCLUDE_DIRS include) + return() +endif() + + idf_component_register(SRCS "pm_locks.c" "pm_trace.c" "pm_impl.c" INCLUDE_DIRS include LDFRAGMENTS linker.lf) diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index cee7ad3301..3342896fa6 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -3,7 +3,6 @@ idf_component_register(SRCS "intr_alloc.c" "panic.c" "system_api.c" "startup.c" - "sleep_modes.c" "system_time.c" INCLUDE_DIRS include PRIV_REQUIRES spi_flash diff --git a/components/esp_system/intr_alloc.c b/components/esp_system/intr_alloc.c index 603138b23b..d440ca9f24 100644 --- a/components/esp_system/intr_alloc.c +++ b/components/esp_system/intr_alloc.c @@ -551,7 +551,14 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre interrupt_controller_hal_set_int_handler(intr, handler, arg); #endif } +#ifdef __XTENSA__ // TODO ESP32-C3 IDF-2126 if (flags&ESP_INTR_FLAG_EDGE) xthal_set_intclear(1 << intr); +#else + if (flags & ESP_INTR_FLAG_EDGE) { + ESP_INTR_DISABLE(intr); + esprv_intc_int_set_priority(intr, 0); + } +#endif vd->source=source; } if (flags&ESP_INTR_FLAG_IRAM) { diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c index c01bec714f..3aa8b66460 100644 --- a/components/esp_system/sleep_modes.c +++ b/components/esp_system/sleep_modes.c @@ -26,8 +26,6 @@ #include "esp_timer.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "driver/touch_sensor.h" -#include "driver/touch_sensor_common.h" #include "soc/soc_caps.h" #include "driver/rtc_io.h" #include "hal/rtc_io_hal.h" @@ -43,6 +41,8 @@ #include "hal/uart_hal.h" #if SOC_TOUCH_SENSOR_NUM > 0 #include "hal/touch_sensor_hal.h" +#include "driver/touch_sensor.h" +#include "driver/touch_sensor_common.h" #endif #include "hal/clk_gate_ll.h" diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 2c7fff2c4c..e43a4c44f8 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -29,8 +29,6 @@ if(NOT BOOTLOADER_BUILD) "interrupt_controller_hal.c" "sha_hal.c" "aes_hal.c" - "twai_hal.c" - "twai_hal_iram.c" "${target}/interrupt_descriptor_table.c") if(${target} STREQUAL "esp32") @@ -41,6 +39,8 @@ if(NOT BOOTLOADER_BUILD) "pcnt_hal.c" "sdio_slave_hal.c" "touch_sensor_hal.c" + "twai_hal.c" + "twai_hal_iram.c" "esp32/adc_hal.c" "esp32/brownout_hal.c" "esp32/touch_sensor_hal.c") @@ -57,6 +57,8 @@ if(NOT BOOTLOADER_BUILD) "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" "touch_sensor_hal.c" + "twai_hal.c" + "twai_hal_iram.c" "esp32s2/adc_hal.c" "esp32s2/brownout_hal.c" "esp32s2/cp_dma_hal.c" @@ -74,6 +76,8 @@ if(NOT BOOTLOADER_BUILD) "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" "touch_sensor_hal.c" + "twai_hal.c" + "twai_hal_iram.c" "esp32s3/brownout_hal.c" "esp32s3/systimer_hal.c" "esp32s3/touch_sensor_hal.c") diff --git a/components/hal/esp32c3/adc_hal.c b/components/hal/esp32c3/adc_hal.c index 1b417f33e8..b000a6c9d8 100644 --- a/components/hal/esp32c3/adc_hal.c +++ b/components/hal/esp32c3/adc_hal.c @@ -33,6 +33,8 @@ void adc_hal_digi_deinit(void) adc_hal_deinit(); } +uint32_t adc_hal_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd, bool force_cal); + static inline void adc_set_init_code(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) { uint32_t cal_val = adc_hal_calibration(adc_n, channel, atten, true, false); diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h new file mode 100644 index 0000000000..87d0886d0c --- /dev/null +++ b/components/hal/esp32c3/include/hal/i2s_ll.h @@ -0,0 +1,912 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-S3 I2S register operations + +#pragma once + +#include +#include +#include "soc/i2s_periph.h" +#include "hal/i2s_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get I2S hardware instance with giving i2s num +#define I2S_LL_GET_HW(num) (((num) == 0) ? (&I2S0) : NULL) + +#define I2S_INTR_IN_SUC_EOF BIT(9) +#define I2S_INTR_OUT_EOF BIT(12) +#define I2S_INTR_IN_DSCR_ERR BIT(13) +#define I2S_INTR_OUT_DSCR_ERR BIT(14) +#define I2S_INTR_MAX (0xFFFFFFFF) + +/** + * @brief Reset rx fifo + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_fifo_reset = 1; + // hw->conf.rx_fifo_reset = 0; +} + +/** + * @brief Reset tx fifo + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_fifo_reset = 1; + // hw->conf.tx_fifo_reset = 0; +} + +/** + * @brief Enable rx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.in_suc_eof = 1; + // hw->int_ena.in_dscr_err = 1; +} + +/** + * @brief Disable rx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.in_suc_eof = 0; + // hw->int_ena.in_dscr_err = 0; +} + +/** + * @brief Disable tx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.out_eof = 0; + // hw->int_ena.out_dscr_err = 0; +} + +/** + * @brief Enable tx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.out_eof = 1; + // hw->int_ena.out_dscr_err = 1; +} + +/** + * @brief Reset dma in + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->lc_conf.in_rst = 1; + // hw->lc_conf.in_rst = 0; +} + +/** + * @brief Reset dma out + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->lc_conf.out_rst = 1; + // hw->lc_conf.out_rst = 0; +} + +/** + * @brief Reset tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_tx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_reset = 1; + // hw->conf.tx_reset = 0; +} + +/** + * @brief Reset rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_rx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_reset = 1; + // hw->conf.rx_reset = 0; +} + +/** + * @brief Start out link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_out_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->out_link.start = 1; +} + +/** + * @brief Start tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_tx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_start = 1; +} + +/** + * @brief Start in link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_in_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->in_link.start = 1; +} + +/** + * @brief Start rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_rx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_start = 1; +} + +/** + * @brief Stop out link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_out_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->out_link.stop = 1; +} + +/** + * @brief Stop tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_tx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_start = 0; +} + +/** + * @brief Stop in link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_in_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->in_link.stop = 1; +} + +/** + * @brief Stop rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_rx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_start = 0; +} + +/** + * @brief Enable dma + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_dma(i2s_dev_t *hw) +{ + abort(); // FIXME + // //Enable and configure DMA + // typeof(hw->lc_conf) lc_conf; + // lc_conf.val = 0; + // lc_conf.out_eof_mode = 1; + // hw->lc_conf.val = lc_conf.val; +} + +/** + * @brief Get I2S interrupt status + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get interrupt status + */ +static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->int_st.val; +} + +/** + * @brief Clear I2S interrupt status + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to clear interrupt status + */ +static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->int_clr.val = val; +} + +/** + * @brief Get I2S out eof des address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get out eof des address + */ +static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->out_eof_des_addr; +} + +/** + * @brief Get I2S in eof des address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get in eof des address + */ +static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->in_eof_des_addr; +} + +/** + * @brief Get I2S tx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx fifo mode + */ +static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->fifo_conf.tx_fifo_mod; +} + +/** + * @brief Set I2S tx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx fifo mode + */ +static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->fifo_conf.tx_fifo_mod = val; +} + +/** + * @brief Get I2S rx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx fifo mode + */ +static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->fifo_conf.rx_fifo_mod; +} + +/** + * @brief Set I2S rx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx fifo mode + */ +static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->fifo_conf.rx_fifo_mod = val; +} + +/** + * @brief Set I2S tx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx chan mode + */ +static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf_chan.tx_chan_mod = val; +} + +/** + * @brief Set I2S rx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx chan mode + */ +static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf_chan.rx_chan_mod = val; +} + +/** + * @brief Set I2S out link address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set out link address + */ +static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->out_link.addr = val; +} + +/** + * @brief Set I2S in link address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set in link address + */ +static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->in_link.addr = val; +} + +/** + * @brief Set I2S rx eof num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx eof num + */ +static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->rx_eof_num = val; +} + +/** + * @brief Get I2S tx pdm fp + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx pdm fp + */ +static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->pdm_freq_conf.tx_pdm_fp; +} + +/** + * @brief Get I2S tx pdm fs + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx pdm fs + */ +static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->pdm_freq_conf.tx_pdm_fs; +} + +/** + * @brief Set I2S tx pdm fp + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm fp + */ +static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->pdm_freq_conf.tx_pdm_fp = val; +} + +/** + * @brief Set I2S tx pdm fs + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm fs + */ +static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->pdm_freq_conf.tx_pdm_fs = val; +} + +/** + * @brief Get I2S rx sinc dsr 16 en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx sinc dsr 16 en + */ +static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) +{ + abort(); // FIXME + // *val = hw->pdm_conf.rx_sinc_dsr_16_en; +} + +/** + * @brief Set I2S clkm div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div num + */ +static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clkm_div_num = val; +} + +/** + * @brief Set I2S clkm div b + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div b + */ +static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clkm_div_b = val; +} + +/** + * @brief Set I2S clkm div a + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div a + */ +static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clkm_div_a = val; +} + +/** + * @brief Set I2S tx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bck div num + */ +static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.tx_bck_div_num = val; +} + +/** + * @brief Set I2S rx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bck div num + */ +static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.rx_bck_div_num = val; +} + +/** + * @brief Set I2S clk sel + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clk sel + */ +static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clk_sel = (val == 1) ? 1 : 2; +} + +/** + * @brief Set I2S tx bits mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bits mod + */ +static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.tx_bits_mod = val; +} + +/** + * @brief Set I2S rx bits mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bits mod + */ +static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.rx_bits_mod = val; +} + +/** + * @brief Set I2S rx sinc dsr 16 en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx sinc dsr 16 en + */ +static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.rx_sinc_dsr_16_en = val; +} + +/** + * @brief Set I2S dscr en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set dscr en + */ +static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->fifo_conf.dscr_en = val; +} + +/** + * @brief Set I2S lcd en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set lcd en + */ +static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->conf2.lcd_en = val; +} + +/** + * @brief Set I2S camera en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set camera en + */ +static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->conf2.camera_en = val; +} + +/** + * @brief Set I2S pcm2pdm conv en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set pcm2pdm conv en + */ +static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.pcm2pdm_conv_en = val; +} + +/** + * @brief Set I2S TX to MSB Alignment Standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_format_msb_align(i2s_dev_t *hw) +{ +} + + +static inline void i2s_ll_set_rx_format_msb_align(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to PCM long standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_pcm_long(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to PCM long standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to PCM short standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_pcm_short(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to philip standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_format_philip(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to PCM short standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_pcm_short(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to philip standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S pdm2pcm conv en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set pdm2pcm conv en + */ +static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.pdm2pcm_conv_en = val; +} + +/** + * @brief Set I2S rx pdm en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx pdm en + */ +static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.rx_pdm_en = val; +} + +/** + * @brief Set I2S tx pdm en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm en + */ +static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.tx_pdm_en = val; +} + +/** + * @brief Set I2S tx fifo mod force en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx fifo mod force en + */ +static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->fifo_conf.tx_fifo_mod_force_en = val; +} + +/** + * @brief Set I2S rx fifo mod force en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx fifo mod force en + */ +static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->fifo_conf.rx_fifo_mod_force_en = val; +} + +/** + * @brief Set I2S tx right first + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx right first + */ +static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_right_first = val; +} + +/** + * @brief Set I2S rx right first + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx right first + */ +static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_right_first = val; +} + +/** + * @brief Set I2S tx slave mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx slave mod + */ +static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_slave_mod = val; +} + +/** + * @brief Set I2S rx slave mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx slave mod + */ +static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_slave_mod = val; +} + +/** + * @brief Get I2S tx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx msb right + */ +static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->conf.tx_msb_right; +} + +/** + * @brief Get I2S rx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx msb right + */ +static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->conf.rx_msb_right; +} + +/** + * @brief Set I2S tx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx msb right + */ +static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_msb_right = val; +} + +/** + * @brief Set I2S rx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx msb right + */ +static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_msb_right = val; +} + +/** + * @brief Set I2S tx mono + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx mono + */ +static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_mono = val; +} + +/** + * @brief Set I2S rx mono + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx mono + */ +static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_mono = val; +} + +/** + * @brief Set I2S tx sinc osr2 + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx sinc osr2 + */ +static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->pdm_conf.tx_sinc_osr2 = val; +} + +/** + * @brief Set I2S sig loopback + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set sig loopback + */ +static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.sig_loopback = val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/CMakeLists.txt b/components/soc/esp32c3/CMakeLists.txt index f7d0bf36aa..9e53c3042f 100644 --- a/components/soc/esp32c3/CMakeLists.txt +++ b/components/soc/esp32c3/CMakeLists.txt @@ -1,7 +1,6 @@ set(srcs "adc_periph.c" "gpio_periph.c" - "rtc_periph.c" "interrupts.c" "spi_periph.c" "ledc_periph.c" diff --git a/components/ulp/CMakeLists.txt b/components/ulp/CMakeLists.txt index 3b162300b5..a2dcb8abf0 100644 --- a/components/ulp/CMakeLists.txt +++ b/components/ulp/CMakeLists.txt @@ -1,9 +1,13 @@ -set(srcs "ulp.c" - "ulp_macro.c") +idf_build_get_property(target IDF_TARGET) -if(CONFIG_ESP32S2_ULP_COPROC_RISCV) - list(APPEND srcs "ulp_riscv.c") +if(NOT (IDF_TARGET STREQUAL "esp32c3")) + set(srcs "ulp.c" + "ulp_macro.c") + + if(CONFIG_ESP32S2_ULP_COPROC_RISCV) + list(APPEND srcs "ulp_riscv.c") + endif() + + idf_component_register(SRCS ${srcs} + INCLUDE_DIRS include) endif() - -idf_component_register(SRCS ${srcs} - INCLUDE_DIRS include) diff --git a/components/wifi_provisioning/CMakeLists.txt b/components/wifi_provisioning/CMakeLists.txt index bb47508c69..58000d1d02 100644 --- a/components/wifi_provisioning/CMakeLists.txt +++ b/components/wifi_provisioning/CMakeLists.txt @@ -1,3 +1,8 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "esp32c3") + return() +endif() + set(srcs "src/wifi_config.c" "src/wifi_scan.c" "src/manager.c"