Merge branch 'feat/etm_driver_c61' into 'master'

ETM driver support for esp32c61 Closes IDF-9295, IDF-9964, IDF-9318, and IDF-10373 See merge request espressif/esp-idf!34090
2024-10-18 13:11:35 +08:00 · 2024-10-18 13:11:35 +08:00 · 63cf6f93e6
commit 63cf6f93e6
--- a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld
+++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld
@ -9,8 +9,9 @@
 ***************************************/

 /* Functions */
-systimer_hal_init = 0x400003d0;
-systimer_hal_deinit = 0x400003d4;
+/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* systimer_hal_init = 0x400003d0; */
+/* systimer_hal_deinit = 0x400003d4; */
 systimer_hal_set_tick_rate_ops = 0x400003d8;
 systimer_hal_get_counter_value = 0x400003dc;
 systimer_hal_get_time = 0x400003e0;
--- a/components/esp_rom/patches/esp_rom_systimer.c
+++ b/components/esp_rom/patches/esp_rom_systimer.c
@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
 }
 #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200)

-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
 void systimer_hal_init(systimer_hal_context_t *hal)
 {
    hal->dev = &SYSTIMER;
@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal)
    systimer_ll_enable_clock(hal->dev, false);
    hal->dev = NULL;
 }
-#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4
+#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61

 #endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
--- a/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c
+++ b/components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c
@ -51,7 +51,7 @@ TEST_CASE("rtos_systick_etm_event", "[etm]")

    TEST_ESP_OK(esp_etm_channel_enable(etm_channel_a));

-    // should see a 500Hz square wave on the GPIO (if RTOS systick is set to 1000Hz)
+    // should see a 50Hz square wave on the GPIO (if RTOS systick is set to 100Hz)
    vTaskDelay(pdMS_TO_TICKS(1000));

    // delete etm primitives
--- a/components/hal/esp32c5/include/hal/etm_ll.h
+++ b/components/hal/esp32c5/include/hal/etm_ll.h
@ -11,7 +11,6 @@
 #include <stdbool.h>
 #include "hal/assert.h"
 #include "hal/misc.h"
-#include "hal/lp_aon_ll.h"
 #include "soc/soc_etm_struct.h"
 #include "soc/pcr_struct.h"

--- a/components/hal/esp32c6/include/hal/etm_ll.h
+++ b/components/hal/esp32c6/include/hal/etm_ll.h
@ -11,7 +11,6 @@
 #include <stdbool.h>
 #include "hal/assert.h"
 #include "hal/misc.h"
-#include "hal/lp_aon_ll.h"
 #include "soc/soc_etm_struct.h"
 #include "soc/pcr_struct.h"

--- a/components/hal/esp32c61/include/hal/etm_ll.h
+++ b/components/hal/esp32c61/include/hal/etm_ll.h
@ -0,0 +1,117 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "soc/soc_etm_struct.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable the clock for ETM register
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    PCR.etm_conf.etm_clk_en = enable;
+}
+
+/**
+ * @brief Reset the ETM register
+ *
+ * @param group_id Group ID
+ */
+static inline void etm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.etm_conf.etm_rst_en = 1;
+    PCR.etm_conf.etm_rst_en = 0;
+}
+
+/**
+ * @brief Enable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_set.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_set.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Disable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_clr.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_clr.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Check whether the ETM channel is enabled or not
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @return true if the channel is enabled, false otherwise
+ */
+static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        return hw->ch_ena_ad0.val & (1 << chan);
+    } else {
+        return hw->ch_ena_ad1.val & (1 << (chan - 32));
+    }
+}
+
+/**
+ * @brief Set the input event for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param event Event ID
+ */
+static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].eid, chn_evt_id, event);
+}
+
+/**
+ * @brief Set the output task for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param task Task ID
+ */
+static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[chan].tid, chn_task_id, task);
+}
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/hal/esp32c61/include/hal/gpio_etm_ll.h
+++ b/components/hal/esp32c61/include/hal/gpio_etm_ll.h
@ -0,0 +1,136 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "soc/gpio_ext_struct.h"
+#include "soc/soc_etm_source.h"
+
+#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
+#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch))
+#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch))
+
+#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch))
+#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
+#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
+
+#define GPIO_LL_ETM_EVENT_CHANNELS_PER_GROUP    8
+#define GPIO_LL_ETM_TASK_CHANNELS_PER_GROUP     8
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set which GPIO to be bound to the event channel
+ *
+ * @note Different channels can be bound to one GPIO
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Event channel number
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
+{
+    dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num;
+}
+
+/**
+ * @brief Whether to enable the event channel
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Event channel number
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
+{
+    dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable;
+}
+
+/**
+ * @brief Get which GPIO is bound to the event channel
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Event channel number
+ * @return GPIO number
+ */
+static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
+{
+    return dev->etm_event_chn_cfg[chan].etm_chn_event_sel;
+}
+
+/**
+ * @brief Set which GPIO to be bound to the task channel
+ *
+ * @note One channel can be bound to multiple different GPIOs
+ *
+ * @param dev Register base address
+ * @param chan GPIO ETM Task channel number
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
+    reg_val &= ~(0x07 << (g_idx * 6));
+    reg_val |= ((chan & 0x07) << (g_idx * 6));
+    dev->etm_task_pn_cfg[g_p].val = reg_val;
+}
+
+/**
+ * @brief Whether to enable the GPIO to be managed by the task channel
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
+    reg_val &= ~(0x01 << (g_idx * 6 + 5));
+    reg_val |= ((enable & 0x01) << (g_idx * 6 + 5));
+    dev->etm_task_pn_cfg[g_p].val = reg_val;
+}
+
+/**
+ * @brief Check whether a GPIO has been enabled and managed by a task channel
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @return True if enabled, false otherwise
+ */
+static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5));
+}
+
+/**
+ * @brief Get the channel number that the GPIO is bound to
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @return GPIO ETM Task channel number
+ */
+static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num)
+{
+    int g_p = gpio_num / 5;
+    int g_idx = gpio_num % 5;
+    return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07;
+}
+
+#ifdef __cplusplus
+}
+#endif
--- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
@ -131,6 +131,10 @@ config SOC_REG_I2C_SUPPORTED
    bool
    default y

+config SOC_ETM_SUPPORTED
+    bool
+    default y
+
 config SOC_PAU_SUPPORTED
    bool
    default y
@ -267,6 +271,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
    int
    default 2

+config SOC_GDMA_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_GDMA_SUPPORT_SLEEP_RETENTION
    bool
    default y
@ -279,6 +287,10 @@ config SOC_ETM_CHANNELS_PER_GROUP
    int
    default 50

+config SOC_ETM_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
 config SOC_GPIO_PORT
    int
    default 1
@ -295,6 +307,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
    bool
    default y

+config SOC_GPIO_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
    bool
    default y
@ -655,6 +671,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
    bool
    default y

+config SOC_SYSTIMER_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
@ -691,6 +711,10 @@ config SOC_TIMER_SUPPORT_SLEEP_RETENTION
    bool
    default y

+config SOC_TIMER_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_MWDT_SUPPORT_SLEEP_RETENTION
    bool
    default y
--- a/components/soc/esp32c61/include/soc/soc_caps.h
+++ b/components/soc/esp32c61/include/soc/soc_caps.h
@ -56,7 +56,7 @@
 //  \#define SOC_RNG_SUPPORTED               1    //TODO: [ESP32C61] IDF-9236
 #define SOC_MODEM_CLOCK_SUPPORTED       1
 #define SOC_REG_I2C_SUPPORTED           1
-//  \#define SOC_ETM_SUPPORTED               0
+#define SOC_ETM_SUPPORTED               1
 //  \#define SOC_SDIO_SLAVE_SUPPORTED        0
 #define SOC_PAU_SUPPORTED               1
 #define SOC_LIGHT_SLEEP_SUPPORTED       1
@ -148,13 +148,13 @@
 #define SOC_AHB_GDMA_VERSION            2U
 #define SOC_GDMA_NUM_GROUPS_MAX         1U
 #define SOC_GDMA_PAIRS_PER_GROUP_MAX    2
-// \#define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule TODO: IDF-9964
+#define SOC_GDMA_SUPPORT_ETM            1  // Support ETM submodule
 #define SOC_GDMA_SUPPORT_SLEEP_RETENTION    1

 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
 #define SOC_ETM_CHANNELS_PER_GROUP      50  // Number of ETM channels in the group
-// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1   // Support sleep retention
+#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1   // Support sleep retention

 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-C61 has 1 GPIO peripheral
@ -164,7 +164,7 @@
 #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER    1

 // GPIO peripheral has the ETM extension
-//  \#define SOC_GPIO_SUPPORT_ETM          1  //TODO: [ESP32C61] IDF-9318
+#define SOC_GPIO_SUPPORT_ETM          1

 // Target has the full LP IO subsystem
 // On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
@ -340,7 +340,7 @@
 #define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
 #define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
-// #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event
+#define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
@ -354,7 +354,7 @@
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      (1)
 #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   (1)
 #define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
-// #define SOC_TIMER_SUPPORT_ETM             (1)
+#define SOC_TIMER_SUPPORT_ETM             (1)

 /*--------------------------- WATCHDOG CAPS ---------------------------------------*/
 // #define SOC_MWDT_SUPPORT_XTAL              (1)
--- a/components/soc/esp32c61/ld/esp32c61.peripherals.ld
+++ b/components/soc/esp32c61/ld/esp32c61.peripherals.ld
@ -29,6 +29,8 @@ PROVIDE ( ECC                 = 0x6008B000 );
 PROVIDE ( ECDSA               = 0x6008E000 );
 PROVIDE ( IO_MUX              = 0x60090000 );
 PROVIDE ( GPIO                = 0x60091000 );
+PROVIDE ( GPIO_EXT            = 0x60091e00 );
+PROVIDE ( GPIO_ETM            = 0x60091f18 );
 PROVIDE ( TCM_MEM_MONITOR     = 0x60092000 );
 PROVIDE ( PAU                 = 0x60093000 );
 PROVIDE ( HP_SYSTEM           = 0x60095000 );
--- a/components/soc/esp32c61/register/soc/gpio_ext_struct.h
+++ b/components/soc/esp32c61/register/soc/gpio_ext_struct.h
@ -128,6 +128,15 @@ typedef union {
    uint32_t val;
 } gpio_ext_etm_event_chn_cfg_reg_t;

+/** Type of etm_task_pn_cfg register
+ *  GPIO selection register for ETM.
+ *  This register is an abstraction of the following registers:
+ *  gpio_ext_etm_task_p0_cfg_reg_t ~ gpio_ext_etm_task_p4_cfg_reg_t
+ */
+typedef union {
+    uint32_t val;
+} gpio_ext_etm_task_pn_cfg_reg_t;
+
 /** Type of etm_task_p0_cfg register
 *  GPIO selection register 0 for ETM
 */
@ -659,6 +668,11 @@ typedef union {
    uint32_t val;
 } gpio_ext_version_reg_t;

+typedef struct gpio_etm_dev_t {
+    volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
+    uint32_t reserved_138[8];
+    volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[5];
+} gpio_etm_dev_t;

 typedef struct {
    volatile gpio_ext_clock_gate_reg_t clock_gate;
@ -666,13 +680,7 @@ typedef struct {
    volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
    volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
    uint32_t reserved_060[46];
-    volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
-    uint32_t reserved_138[8];
-    volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
-    volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
-    volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
-    volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
-    volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
+    volatile gpio_etm_dev_t etm;
    uint32_t reserved_16c[25];
    volatile gpio_ext_int_raw_reg_t int_raw;
    volatile gpio_ext_int_st_reg_t int_st;
@ -683,6 +691,8 @@ typedef struct {
    volatile gpio_ext_version_reg_t version;
 } gpio_ext_dev_t;

+extern gpio_etm_dev_t GPIO_ETM;
+extern gpio_ext_dev_t GPIO_EXT;

 #ifndef __cplusplus
 _Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
--- a/components/soc/esp32c61/register/soc/soc_etm_struct.h
+++ b/components/soc/esp32c61/register/soc/soc_etm_struct.h
@ -3161,113 +3161,17 @@ typedef union {
 } soc_etm_date_reg_t;


-typedef struct {
+typedef struct soc_etm_dev_t {
    volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
    volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
    volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
    volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
    volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
    volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
-    volatile soc_etm_chn_evt_id_reg_t ch0_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch0_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch1_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch1_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch2_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch2_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch3_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch3_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch4_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch4_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch5_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch5_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch6_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch6_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch7_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch7_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch8_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch8_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch9_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch9_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch10_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch10_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch11_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch11_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch12_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch12_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch13_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch13_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch14_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch14_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch15_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch15_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch16_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch16_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch17_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch17_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch18_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch18_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch19_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch19_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch20_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch20_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch21_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch21_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch22_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch22_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch23_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch23_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch24_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch24_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch25_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch25_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch26_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch26_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch27_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch27_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch28_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch28_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch29_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch29_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch30_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch30_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch31_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch31_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch32_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch32_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch33_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch33_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch34_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch34_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch35_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch35_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch36_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch36_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch37_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch37_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch38_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch38_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch39_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch39_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch40_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch40_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch41_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch41_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch42_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch42_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch43_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch43_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch44_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch44_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch45_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch45_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch46_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch46_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch47_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch47_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch48_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch48_task_id;
-    volatile soc_etm_chn_evt_id_reg_t ch49_evt_id;
-    volatile soc_etm_chn_task_id_reg_t ch49_task_id;
+    volatile struct {
+        soc_etm_chn_evt_id_reg_t eid;
+        soc_etm_chn_task_id_reg_t tid;
+    } channel[50];
    volatile soc_etm_evt_st0_reg_t evt_st0;
    volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
    volatile soc_etm_evt_st1_reg_t evt_st1;
--- a/docs/docs_not_updated/esp32c61.txt
+++ b/docs/docs_not_updated/esp32c61.txt
@ -47,7 +47,6 @@ api-reference/peripherals/usb_host/usb_host_notes_design.rst
 api-reference/peripherals/usb_device.rst
 api-reference/peripherals/sdspi_host.rst
 api-reference/peripherals/dac.rst
-api-reference/peripherals/etm.rst
 api-reference/peripherals/i2s.rst
 api-reference/peripherals/touch_element.rst
 api-reference/peripherals/ppa.rst
--- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
+++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 |
-| ----------------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
+| ----------------- | -------- | -------- | --------- | -------- | -------- |

 # HC-SR04 Example based on GPTimer Capture and ETM

--- a/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py
+++ b/examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py
@ -6,6 +6,7 @@ from pytest_embedded import Dut

@pytest.mark.esp32c5
@pytest.mark.esp32c6
+@pytest.mark.esp32c61
@pytest.mark.esp32h2
@pytest.mark.esp32p4
@pytest.mark.generic