kopia lustrzana https://github.com/espressif/esp-idf
LEDC: improved support for ESP32-C3 and refactored divisor calculation
As ESP32C3 does not have support for REF_TICK source clock, it is now not possible to select it anymore. Auto cfg clock has been improved for all boards.pull/9338/head
rodzic
14b52e9d83
commit
63afc84de5
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@ -17,10 +17,43 @@
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extern "C" {
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#endif
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#define LEDC_APB_CLK_HZ (APB_CLK_FREQ)
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#define LEDC_REF_CLK_HZ (REF_CLK_FREQ)
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#define LEDC_ERR_DUTY (0xFFFFFFFF)
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#define LEDC_ERR_VAL (-1)
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#define LEDC_APB_CLK_HZ (APB_CLK_FREQ)
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#define LEDC_REF_CLK_HZ (REF_CLK_FREQ)
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#define LEDC_ERR_DUTY (0xFFFFFFFF)
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#define LEDC_ERR_VAL (-1)
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/**
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* @brief Configuration parameters of LEDC channel for ledc_channel_config function
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*/
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typedef struct {
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int gpio_num; /*!< the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16 */
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ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
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ledc_channel_t channel; /*!< LEDC channel (0 - 7) */
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ledc_intr_type_t intr_type; /*!< configure interrupt, Fade interrupt enable or Fade interrupt disable */
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ledc_timer_t timer_sel; /*!< Select the timer source of channel (0 - 3) */
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uint32_t duty; /*!< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)] */
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int hpoint; /*!< LEDC channel hpoint value, the max value is 0xfffff */
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struct {
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unsigned int output_invert: 1;/*!< Enable (1) or disable (0) gpio output invert */
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} flags; /*!< LEDC flags */
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} ledc_channel_config_t;
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/**
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* @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function
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*/
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typedef struct {
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ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
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union {
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ledc_timer_bit_t duty_resolution; /*!< LEDC channel duty resolution */
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ledc_timer_bit_t bit_num __attribute__((deprecated)); /*!< Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1 */
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};
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ledc_timer_t timer_num; /*!< The timer source of channel (0 - 3) */
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uint32_t freq_hz; /*!< LEDC timer frequency (Hz) */
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ledc_clk_cfg_t clk_cfg; /*!< Configure LEDC source clock.
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For low speed channels and high speed channels, you can specify the source clock using LEDC_USE_REF_TICK, LEDC_USE_APB_CLK or LEDC_AUTO_CLK.
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For low speed channels, you can also specify the source clock using LEDC_USE_RTC8M_CLK, in this case, all low speed channel's source clock must be RTC8M_CLK*/
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} ledc_timer_config_t;
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typedef intr_handle_t ledc_isr_handle_t;
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@ -62,6 +62,8 @@ static portMUX_TYPE ledc_spinlock = portMUX_INITIALIZER_UNLOCKED;
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#define SLOW_CLK_CYC_CALIBRATE (13)
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#define LEDC_FADE_TOO_SLOW_STR "LEDC FADE TOO SLOW"
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#define LEDC_FADE_TOO_FAST_STR "LEDC FADE TOO FAST"
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#define DIM(array) (sizeof(array)/sizeof(*array))
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#define LEDC_IS_DIV_INVALID(div) ((div) <= LEDC_LL_FRACTIONAL_MAX || (div) > LEDC_TIMER_DIV_NUM_MAX)
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static __attribute__((unused)) const char *LEDC_NOT_INIT = "LEDC is not initialized";
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static __attribute__((unused)) const char *LEDC_FADE_SERVICE_ERR_STR = "LEDC fade service not installed";
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@ -101,10 +103,12 @@ static uint32_t ledc_get_src_clk_freq(ledc_clk_cfg_t clk_cfg)
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uint32_t src_clk_freq = 0;
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if (clk_cfg == LEDC_USE_APB_CLK) {
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src_clk_freq = LEDC_APB_CLK_HZ;
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} else if (clk_cfg == LEDC_USE_REF_TICK) {
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src_clk_freq = LEDC_REF_CLK_HZ;
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} else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
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src_clk_freq = s_ledc_slow_clk_8M;
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#if SOC_LEDC_SUPPORT_REF_TICK
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} else if (clk_cfg == LEDC_USE_REF_TICK) {
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src_clk_freq = LEDC_REF_CLK_HZ;
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#endif
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#if SOC_LEDC_SUPPORT_XTAL_CLOCK
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} else if (clk_cfg == LEDC_USE_XTAL_CLK) {
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src_clk_freq = rtc_clk_xtal_freq_get() * 1000000;
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@ -174,7 +178,11 @@ esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_
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LEDC_CHECK(p_ledc_obj[speed_mode] != NULL, LEDC_NOT_INIT, ESP_ERR_INVALID_STATE);
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portENTER_CRITICAL(&ledc_spinlock);
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ledc_hal_set_clock_divider(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel, clock_divider);
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#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
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/* Clock source can only be configured on boards which support timer-specific
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* source clock. */
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ledc_hal_set_clock_source(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel, clk_src);
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#endif
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ledc_hal_set_duty_resolution(&(p_ledc_obj[speed_mode]->ledc_hal), timer_sel, duty_resolution);
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ledc_ls_timer_update(speed_mode, timer_sel);
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portEXIT_CRITICAL(&ledc_spinlock);
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@ -258,52 +266,211 @@ esp_err_t ledc_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags,
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return ret;
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}
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// Setting the LEDC timer divisor with the given source clock, frequency and resolution.
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static inline uint32_t ledc_calculate_divisor(uint32_t src_clk_freq, int freq_hz, uint32_t precision)
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{
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/**
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* In order to find the right divisor, we need to divide the source clock
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* frequency by the desired frequency. However, two things to note here:
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* - The lowest LEDC_LL_FRACTIONAL_BITS bits of the result are the FRACTIONAL
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* part. The higher bits represent the integer part, this is why we need
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* to right shift the source frequency.
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* - The `precision` parameter represents the granularity of the clock. It
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* **must** be a power of 2. It means that the resulted divisor is
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* a multiplier of `precision`.
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*
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* Let's take a concrete example, we need to generate a 5KHz clock out of
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* a 80MHz clock (APB).
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* If the precision is 1024 (10 bits), the resulted multiplier is:
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* (80000000 << 8) / (5000 * 1024) = 4000 (0xfa0)
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* Let's ignore the fractional part to simplify the exaplanation, so we get
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* a result of 15 (0xf).
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* This can be interpreted as: every 15 "precision" ticks, the resulted
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* clock will go high, where one precision tick is made out of 1024 source
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* clock ticks.
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* Thus, every `15 * 1024` source clock ticks, the resulted clock will go
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* high. */
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return ( (uint64_t) src_clk_freq << LEDC_LL_FRACTIONAL_BITS ) / (freq_hz * precision);
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}
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static inline uint32_t ledc_auto_global_clk_divisor(int freq_hz, uint32_t precision, ledc_clk_cfg_t* clk_target)
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{
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uint32_t div_param = 0;
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uint32_t i = 0;
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uint32_t clk_freq = 0;
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/* This function will go through all the following clock sources to look
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* for a valid divisor which generates the requested frequency. */
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const ledc_clk_cfg_t glb_clks[] = LEDC_LL_GLOBAL_CLOCKS;
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for (i = 0; i < DIM(glb_clks); i++) {
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/* Before calculating the divisor, we need to have the RTC frequency.
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* If it hasn't been mesured yet, try calibrating it now. */
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if (glb_clks[i] == LEDC_SLOW_CLK_RTC8M && s_ledc_slow_clk_8M == 0 && !ledc_slow_clk_calibrate()) {
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ESP_LOGD(LEDC_TAG, "Unable to retrieve RTC clock frequency, skipping it\n");
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continue;
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}
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clk_freq = ledc_get_src_clk_freq(glb_clks[i]);
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div_param = ledc_calculate_divisor(clk_freq, freq_hz, precision);
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/* If the divisor is valid, we can return this value. */
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if (!LEDC_IS_DIV_INVALID(div_param)) {
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*clk_target = glb_clks[i];
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break;
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}
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}
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return div_param;
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}
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#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
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static inline uint32_t ledc_auto_timer_specific_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint32_t precision,
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ledc_clk_src_t* clk_source)
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{
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uint32_t div_param = 0;
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uint32_t i = 0;
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/* Use an anonymous structure, only this function requires it.
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* Get the list of the timer-specific clocks, try to find one for the reuested frequency. */
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const struct { ledc_clk_src_t clk; uint32_t freq; } specific_clks[] = LEDC_LL_TIMER_SPECIFIC_CLOCKS;
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for (i = 0; i < DIM(specific_clks); i++) {
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div_param = ledc_calculate_divisor(specific_clks[i].freq, freq_hz, precision);
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/* If the divisor is valid, we can return this value. */
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if (!LEDC_IS_DIV_INVALID(div_param)) {
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*clk_source = specific_clks[i].clk;
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break;
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}
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}
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#if SOC_LEDC_SUPPORT_HS_MODE
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/* On board that support LEDC high-speed mode, APB clock becomes a timer-
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* specific clock when in high speed mode. Check if it is necessary here
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* to test APB. */
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if (speed_mode == LEDC_HIGH_SPEED_MODE && i == DIM(specific_clks)) {
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/* No divider was found yet, try with APB! */
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div_param = ledc_calculate_divisor(LEDC_APB_CLK_HZ, freq_hz, precision);
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if (!LEDC_IS_DIV_INVALID(div_param)) {
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*clk_source = LEDC_APB_CLK;
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}
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}
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#endif
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return div_param;
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}
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#endif
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/**
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* @brief Try to find the clock with its divisor giving the frequency requested
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* by the caller.
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*/
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static uint32_t ledc_auto_clk_divisor(ledc_mode_t speed_mode, int freq_hz, uint32_t precision,
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ledc_clk_src_t* clk_source, ledc_clk_cfg_t* clk_target)
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{
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uint32_t div_param = 0;
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#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
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/* If the SoC presents timer-specific clock(s), try to achieve the given frequency
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* thanks to it/them.
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* clk_source parameter will returned by this function. */
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div_param = ledc_auto_timer_specific_clk_divisor(speed_mode, freq_hz, precision, clk_source);
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if (!LEDC_IS_DIV_INVALID(div_param)) {
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/* The dividor is valid, no need try any other clock, return directly. */
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return div_param;
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}
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#endif
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/* On ESP32, only low speed channel can use the global clocks. For other
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* chips, there are no high speed channels. */
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if (speed_mode == LEDC_LOW_SPEED_MODE) {
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div_param = ledc_auto_global_clk_divisor(freq_hz, precision, clk_target);
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}
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return div_param;
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}
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/**
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* @brief Function setting the LEDC timer divisor with the given source clock,
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* frequency and resolution. If the clock configuration passed is
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* LEDC_AUTO_CLK, the clock will be determined automatically (if possible).
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*/
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static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_num, ledc_clk_cfg_t clk_cfg, int freq_hz, int duty_resolution)
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{
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uint32_t div_param = 0;
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uint32_t precision = ( 0x1 << duty_resolution );
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ledc_clk_src_t timer_clk_src = LEDC_APB_CLK;
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// Calculate the divisor
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// User specified source clock(RTC8M_CLK) for low speed channel
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if ((speed_mode == LEDC_LOW_SPEED_MODE) && (clk_cfg == LEDC_USE_RTC8M_CLK)) {
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if(s_ledc_slow_clk_8M == 0) {
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if (ledc_slow_clk_calibrate() == false) {
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goto error;
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}
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const uint32_t precision = ( 0x1 << duty_resolution );
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/* This variable represents the timer's mux value. It will be overwritten
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* if a timer-specific clock is used. */
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ledc_clk_src_t timer_clk_src = LEDC_SCLK;
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uint32_t src_clk_freq = 0;
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if (clk_cfg == LEDC_AUTO_CLK) {
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/* User hasn't specified the speed, we should try to guess it. */
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div_param = ledc_auto_clk_divisor(speed_mode, freq_hz, precision, &timer_clk_src, &clk_cfg);
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} else if (clk_cfg == LEDC_USE_RTC8M_CLK) {
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/* User specified source clock(RTC8M_CLK) for low speed channel.
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* Make sure the speed mode is correct. */
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ESP_RETURN_ON_FALSE((speed_mode == LEDC_LOW_SPEED_MODE), ESP_ERR_INVALID_ARG, LEDC_TAG, "RTC clock can only be used in low speed mode");
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/* Before calculating the divisor, we need to have the RTC frequency.
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* If it hasn't been mesured yet, try calibrating it now. */
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if(s_ledc_slow_clk_8M == 0 && ledc_slow_clk_calibrate() == false) {
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goto error;
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}
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div_param = ( (uint64_t) s_ledc_slow_clk_8M << 8 ) / freq_hz / precision;
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/* We have the RTC clock frequency now. */
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div_param = ledc_calculate_divisor(s_ledc_slow_clk_8M, freq_hz, precision);
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} else {
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// Automatically select APB or REF_TICK as the source clock.
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if (clk_cfg == LEDC_AUTO_CLK) {
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// Try calculating divisor based on LEDC_APB_CLK
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div_param = ( (uint64_t) LEDC_APB_CLK_HZ << 8 ) / freq_hz / precision;
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if (div_param > LEDC_TIMER_DIV_NUM_MAX) {
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// APB_CLK results in divisor which too high. Try using REF_TICK as clock source.
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timer_clk_src = LEDC_REF_TICK;
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div_param = ((uint64_t) LEDC_REF_CLK_HZ << 8) / freq_hz / precision;
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} else if (div_param < 256) {
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// divisor is too low
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goto error;
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}
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// User specified source clock(LEDC_APB_CLK_HZ or LEDC_REF_TICK)
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} else {
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timer_clk_src = (clk_cfg == LEDC_USE_REF_TICK) ? LEDC_REF_TICK : LEDC_APB_CLK;
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uint32_t src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
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div_param = ( (uint64_t) src_clk_freq << 8 ) / freq_hz / precision;
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#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
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if (LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(speed_mode, clk_cfg)) {
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/* Currently we can convert a timer specific clock to a source clock that
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* easily because their values are identical in the enumerations (on purpose)
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* If we decide to change the values in the future, we should consider defining
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* a macro/function to convert timer-specific clock to clock source .*/
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timer_clk_src = (ledc_clk_src_t) clk_cfg;
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}
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#endif
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src_clk_freq = ledc_get_src_clk_freq(clk_cfg);
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div_param = ledc_calculate_divisor(src_clk_freq, freq_hz, precision);
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}
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if (div_param < 256 || div_param > LEDC_TIMER_DIV_NUM_MAX) {
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if (LEDC_IS_DIV_INVALID(div_param)) {
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goto error;
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}
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/* The following debug message makes more sense for AUTO mode. */
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ESP_LOGD(LEDC_TAG, "Using clock source %d (in %s mode), divisor: 0x%x\n",
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timer_clk_src, (speed_mode == LEDC_LOW_SPEED_MODE ? "slow" : "fast"), div_param);
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/* The following block configures the global clock.
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* Thus, in theory, this only makes sense when the source clock is LEDC_SCLK
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* and in LOW_SPEED_MODE (as FAST_SPEED_MODE doesn't present any global clock)
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*
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* However, in practice, on modules that support high-speed mode, no matter
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* whether the source clock is a timer-specific one (e.g. REF_TICK) or not,
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* the global clock MUST be configured when in low speed mode.
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* When using high-speed mode, this is not necessary.
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*/
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#if SOC_LEDC_SUPPORT_HS_MODE
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if (speed_mode == LEDC_LOW_SPEED_MODE) {
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#else
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if (timer_clk_src == LEDC_SCLK) {
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#endif
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ESP_LOGD(LEDC_TAG, "In slow speed mode, using clock %d", clk_cfg);
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portENTER_CRITICAL(&ledc_spinlock);
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ledc_hal_set_slow_clk(&(p_ledc_obj[speed_mode]->ledc_hal), clk_cfg);
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portEXIT_CRITICAL(&ledc_spinlock);
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}
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//Set the divisor
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/* The divisor is correct, we can write in the hardware. */
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ledc_timer_set(speed_mode, timer_num, div_param, duty_resolution, timer_clk_src);
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// reset the timer
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/* Reset the timer. */
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ledc_timer_rst(speed_mode, timer_num);
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return ESP_OK;
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error:
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@ -22,6 +22,27 @@
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#include "soc/ledc_struct.h"
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#define LEDC_LL_GET_HW() &LEDC
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#define LEDC_LL_FRACTIONAL_BITS (8)
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#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
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#define LEDC_LL_GLOBAL_CLOCKS { \
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LEDC_USE_APB_CLK, \
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LEDC_USE_RTC8M_CLK, \
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}
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#define LEDC_LL_TIMER_SPECIFIC_CLOCKS \
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{\
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{ \
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.clk = LEDC_REF_TICK, \
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.freq = LEDC_REF_CLK_HZ, \
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} \
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}
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/* On ESP32, APB clock is a timer-specific clock only in fast clock mode */
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#define LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(SPEED, CLK) (\
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((CLK) == LEDC_USE_REF_TICK) || \
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((SPEED) == LEDC_HIGH_SPEED_MODE && (CLK) == LEDC_USE_APB_CLK) \
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)
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#ifdef __cplusplus
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extern "C" {
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@ -26,6 +26,13 @@ extern "C" {
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#endif
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#define LEDC_LL_GET_HW() &LEDC
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#define LEDC_LL_FRACTIONAL_BITS (8)
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#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
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||||
#define LEDC_LL_GLOBAL_CLOCKS { \
|
||||
LEDC_USE_APB_CLK, \
|
||||
LEDC_USE_XTAL_CLK, \
|
||||
LEDC_USE_RTC8M_CLK, \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC low speed timer clock
|
||||
|
@ -155,27 +162,6 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
|
|||
*clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC timer clock source
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param clk_src Timer clock source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t clk_src)
|
||||
{
|
||||
if (clk_src == LEDC_REF_TICK) {
|
||||
//REF_TICK can only be used when APB is selected.
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 1;
|
||||
hw->conf.apb_clk_sel = 1;
|
||||
} else {
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC timer clock source
|
||||
*
|
||||
|
@ -188,11 +174,7 @@ static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mo
|
|||
*/
|
||||
static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
|
||||
{
|
||||
if (hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 1) {
|
||||
*clk_src = LEDC_REF_TICK;
|
||||
} else {
|
||||
*clk_src = LEDC_APB_CLK;
|
||||
}
|
||||
*clk_src = LEDC_APB_CLK;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -26,6 +26,13 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#define LEDC_LL_GET_HW() &LEDC
|
||||
#define LEDC_LL_FRACTIONAL_BITS (8)
|
||||
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
|
||||
#define LEDC_LL_GLOBAL_CLOCKS { \
|
||||
LEDC_USE_APB_CLK, \
|
||||
LEDC_USE_XTAL_CLK, \
|
||||
LEDC_USE_RTC8M_CLK, \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC low speed timer clock
|
||||
|
@ -155,27 +162,6 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
|
|||
*clock_divider = hw->timer_group[speed_mode].timer[timer_sel].conf.clock_divider;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set LEDC timer clock source
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
|
||||
* @param timer_sel LEDC timer index (0-3), select from ledc_timer_t
|
||||
* @param clk_src Timer clock source
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t clk_src)
|
||||
{
|
||||
if (clk_src == LEDC_REF_TICK) {
|
||||
//REF_TICK can only be used when APB is selected.
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 1;
|
||||
hw->conf.apb_clk_sel = 1;
|
||||
} else {
|
||||
hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get LEDC timer clock source
|
||||
*
|
||||
|
@ -188,11 +174,7 @@ static inline void ledc_ll_set_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mo
|
|||
*/
|
||||
static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
|
||||
{
|
||||
if (hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 1) {
|
||||
*clk_src = LEDC_REF_TICK;
|
||||
} else {
|
||||
*clk_src = LEDC_APB_CLK;
|
||||
}
|
||||
*clk_src = LEDC_APB_CLK;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -26,6 +26,22 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#define LEDC_LL_GET_HW() &LEDC
|
||||
#define LEDC_LL_FRACTIONAL_BITS (8)
|
||||
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
|
||||
#define LEDC_LL_GLOBAL_CLOCKS { \
|
||||
LEDC_USE_APB_CLK, \
|
||||
LEDC_USE_XTAL_CLK, \
|
||||
LEDC_USE_RTC8M_CLK, \
|
||||
}
|
||||
#define LEDC_LL_TIMER_SPECIFIC_CLOCKS \
|
||||
{\
|
||||
{ \
|
||||
.clk = LEDC_REF_TICK, \
|
||||
.freq = LEDC_REF_CLK_HZ, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(SPEED, CLK) ((CLK) == LEDC_USE_REF_TICK)
|
||||
|
||||
/**
|
||||
* @brief Set LEDC low speed timer clock
|
||||
|
|
|
@ -26,6 +26,22 @@ extern "C" {
|
|||
#endif
|
||||
|
||||
#define LEDC_LL_GET_HW() &LEDC
|
||||
#define LEDC_LL_FRACTIONAL_BITS (8)
|
||||
#define LEDC_LL_FRACTIONAL_MAX ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
|
||||
#define LEDC_LL_GLOBAL_CLOCKS { \
|
||||
LEDC_USE_APB_CLK, \
|
||||
LEDC_USE_XTAL_CLK, \
|
||||
LEDC_USE_RTC8M_CLK, \
|
||||
}
|
||||
#define LEDC_LL_TIMER_SPECIFIC_CLOCKS \
|
||||
{\
|
||||
{ \
|
||||
.clk = LEDC_REF_TICK, \
|
||||
.freq = LEDC_REF_CLK_HZ, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define LEDC_LL_IS_TIMER_SPECIFIC_CLOCK(SPEED, CLK) ((CLK) == LEDC_USE_REF_TICK)
|
||||
|
||||
/**
|
||||
* @brief Set LEDC low speed timer clock
|
||||
|
|
|
@ -1,16 +1,8 @@
|
|||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
|
@ -50,11 +42,19 @@ typedef enum {
|
|||
#endif
|
||||
} ledc_slow_clk_sel_t;
|
||||
|
||||
/**
|
||||
* In theory, the following enumeration shall be placed in LEDC driver's header.
|
||||
* However, as the next enumeration, `ledc_clk_src_t`, makes the use of some of
|
||||
* these values and to avoid mutual inclusion of the headers, we must define it
|
||||
* here.
|
||||
*/
|
||||
typedef enum {
|
||||
LEDC_AUTO_CLK = 0, /*!< The driver will automatically select the source clock(REF_TICK or APB) based on the giving resolution and duty parameter when init the timer*/
|
||||
LEDC_USE_REF_TICK, /*!< LEDC timer select REF_TICK clock as source clock*/
|
||||
LEDC_USE_APB_CLK, /*!< LEDC timer select APB clock as source clock*/
|
||||
LEDC_USE_RTC8M_CLK, /*!< LEDC timer select RTC8M_CLK as source clock. Only for low speed channels and this parameter must be the same for all low speed channels*/
|
||||
#if SOC_LEDC_SUPPORT_REF_TICK
|
||||
LEDC_USE_REF_TICK, /*!< LEDC timer select REF_TICK clock as source clock*/
|
||||
#endif
|
||||
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
|
||||
LEDC_USE_XTAL_CLK, /*!< LEDC timer select XTAL clock as source clock*/
|
||||
#endif
|
||||
|
@ -64,11 +64,13 @@ typedef enum {
|
|||
LEDC_AUTO_CLK in the driver, as these enums have very similar names and user may pass
|
||||
one of these by mistake. */
|
||||
typedef enum {
|
||||
#if SOC_LEDC_SUPPORT_REF_TICK
|
||||
LEDC_REF_TICK = LEDC_USE_REF_TICK, /*!< LEDC timer clock divided from reference tick (1Mhz) */
|
||||
#endif
|
||||
LEDC_APB_CLK = LEDC_USE_APB_CLK, /*!< LEDC timer clock divided from APB clock (80Mhz) */
|
||||
LEDC_SCLK = LEDC_USE_APB_CLK /*!< Selecting this value for LEDC_TICK_SEL_TIMER let the hardware take its source clock from LEDC_APB_CLK_SEL */
|
||||
} ledc_clk_src_t;
|
||||
|
||||
|
||||
typedef enum {
|
||||
LEDC_TIMER_0 = 0, /*!< LEDC timer 0 */
|
||||
LEDC_TIMER_1, /*!< LEDC timer 1 */
|
||||
|
@ -123,39 +125,6 @@ typedef enum {
|
|||
LEDC_FADE_MAX,
|
||||
} ledc_fade_mode_t;
|
||||
|
||||
/**
|
||||
* @brief Configuration parameters of LEDC channel for ledc_channel_config function
|
||||
*/
|
||||
typedef struct {
|
||||
int gpio_num; /*!< the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16 */
|
||||
ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
|
||||
ledc_channel_t channel; /*!< LEDC channel (0 - 7) */
|
||||
ledc_intr_type_t intr_type; /*!< configure interrupt, Fade interrupt enable or Fade interrupt disable */
|
||||
ledc_timer_t timer_sel; /*!< Select the timer source of channel (0 - 3) */
|
||||
uint32_t duty; /*!< LEDC channel duty, the range of duty setting is [0, (2**duty_resolution)] */
|
||||
int hpoint; /*!< LEDC channel hpoint value, the max value is 0xfffff */
|
||||
struct {
|
||||
unsigned int output_invert: 1;/*!< Enable (1) or disable (0) gpio output invert */
|
||||
} flags; /*!< LEDC flags */
|
||||
|
||||
} ledc_channel_config_t;
|
||||
|
||||
/**
|
||||
* @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function
|
||||
*/
|
||||
typedef struct {
|
||||
ledc_mode_t speed_mode; /*!< LEDC speed speed_mode, high-speed mode or low-speed mode */
|
||||
union {
|
||||
ledc_timer_bit_t duty_resolution; /*!< LEDC channel duty resolution */
|
||||
ledc_timer_bit_t bit_num __attribute__((deprecated)); /*!< Deprecated in ESP-IDF 3.0. This is an alias to 'duty_resolution' for backward compatibility with ESP-IDF 2.1 */
|
||||
};
|
||||
ledc_timer_t timer_num; /*!< The timer source of channel (0 - 3) */
|
||||
uint32_t freq_hz; /*!< LEDC timer frequency (Hz) */
|
||||
ledc_clk_cfg_t clk_cfg; /*!< Configure LEDC source clock.
|
||||
For low speed channels and high speed channels, you can specify the source clock using LEDC_USE_REF_TICK, LEDC_USE_APB_CLK or LEDC_AUTO_CLK.
|
||||
For low speed channels, you can also specify the source clock using LEDC_USE_RTC8M_CLK, in this case, all low speed channel's source clock must be RTC8M_CLK*/
|
||||
} ledc_timer_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1,16 +1,8 @@
|
|||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for LEDC (common part)
|
||||
|
||||
|
@ -25,37 +17,73 @@ void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode)
|
|||
hal->speed_mode = speed_mode;
|
||||
}
|
||||
|
||||
static inline ledc_clk_cfg_t ledc_hal_get_slow_clock_helper(ledc_hal_context_t *hal)
|
||||
{
|
||||
ledc_slow_clk_sel_t slow_clk = LEDC_SLOW_CLK_APB;
|
||||
|
||||
ledc_hal_get_slow_clk_sel(hal, &slow_clk);
|
||||
|
||||
switch (slow_clk) {
|
||||
case LEDC_SLOW_CLK_RTC8M:
|
||||
return LEDC_USE_RTC8M_CLK;
|
||||
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
|
||||
case LEDC_SLOW_CLK_XTAL:
|
||||
return LEDC_USE_XTAL_CLK;
|
||||
#endif
|
||||
default:
|
||||
return LEDC_USE_APB_CLK;
|
||||
}
|
||||
}
|
||||
|
||||
void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg)
|
||||
{
|
||||
ledc_clk_src_t clk_src = LEDC_APB_CLK;
|
||||
/* Use the following variable to retrieve the clock source used by the LEDC
|
||||
* hardware controler. */
|
||||
ledc_clk_src_t clk_src;
|
||||
|
||||
/* Clock configuration to return to the driver. */
|
||||
ledc_clk_cfg_t driver_clk = LEDC_USE_APB_CLK;
|
||||
|
||||
/* Get the timer-specific mux value. */
|
||||
ledc_hal_get_clock_source(hal, timer_sel, &clk_src);
|
||||
#if SOC_LEDC_SUPPORT_REF_TICK
|
||||
if (clk_src == LEDC_REF_TICK) {
|
||||
*clk_cfg = LEDC_USE_REF_TICK;
|
||||
} else {
|
||||
*clk_cfg = LEDC_USE_APB_CLK;
|
||||
if (hal->speed_mode == LEDC_LOW_SPEED_MODE) {
|
||||
ledc_slow_clk_sel_t slow_clk = LEDC_SLOW_CLK_APB;
|
||||
ledc_hal_get_slow_clk_sel(hal, &slow_clk);
|
||||
if (slow_clk == LEDC_SLOW_CLK_RTC8M) {
|
||||
*clk_cfg = LEDC_USE_RTC8M_CLK;
|
||||
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
|
||||
} else if (slow_clk == LEDC_SLOW_CLK_XTAL) {
|
||||
*clk_cfg = LEDC_USE_XTAL_CLK;
|
||||
driver_clk = LEDC_USE_REF_TICK;
|
||||
} else
|
||||
#endif
|
||||
}
|
||||
}
|
||||
/* If the timer-specific mux is not set to REF_TICK, it either means that:
|
||||
* - The controler is in fast mode, and thus using APB clock (driver_clk
|
||||
* variable's default value)
|
||||
* - The controler is in slow mode and so, using a global clock,
|
||||
* so we have to retrieve that clock here.
|
||||
*/
|
||||
if (hal->speed_mode == LEDC_LOW_SPEED_MODE) {
|
||||
/* If the source clock used by LEDC hardware is not REF_TICKS, it is
|
||||
* necessary to retrieve the global clock source used. */
|
||||
driver_clk = ledc_hal_get_slow_clock_helper(hal);
|
||||
}
|
||||
|
||||
*clk_cfg = driver_clk;
|
||||
}
|
||||
|
||||
void ledc_hal_set_slow_clk(ledc_hal_context_t *hal, ledc_clk_cfg_t clk_cfg)
|
||||
{
|
||||
// For low speed channels, if RTC_8MCLK is used as the source clock, the `slow_clk_sel` register should be cleared, otherwise it should be set.
|
||||
ledc_slow_clk_sel_t slow_clk_sel = LEDC_SLOW_CLK_APB;
|
||||
ledc_slow_clk_sel_t slow_clk_sel;
|
||||
|
||||
switch (clk_cfg) {
|
||||
case LEDC_USE_RTC8M_CLK:
|
||||
slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
|
||||
break;
|
||||
#if SOC_LEDC_SUPPORT_XTAL_CLOCK
|
||||
slow_clk_sel = (clk_cfg == LEDC_USE_RTC8M_CLK) ? LEDC_SLOW_CLK_RTC8M :
|
||||
((clk_cfg == LEDC_USE_XTAL_CLK) ? LEDC_SLOW_CLK_XTAL : LEDC_SLOW_CLK_APB);
|
||||
#else
|
||||
slow_clk_sel = (clk_cfg == LEDC_USE_RTC8M_CLK) ? LEDC_SLOW_CLK_RTC8M : LEDC_SLOW_CLK_APB;
|
||||
case LEDC_USE_XTAL_CLK:
|
||||
slow_clk_sel = LEDC_SLOW_CLK_XTAL;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
slow_clk_sel = LEDC_SLOW_CLK_APB;
|
||||
break;
|
||||
}
|
||||
|
||||
ledc_hal_set_slow_clk_sel(hal, slow_clk_sel);
|
||||
}
|
||||
|
|
|
@ -167,7 +167,8 @@
|
|||
#define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_SUPPORT_HS_MODE (1)
|
||||
#define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX (1)
|
||||
#define SOC_LEDC_SUPPORT_REF_TICK (1)
|
||||
#define SOC_LEDC_SUPPORT_HS_MODE (1)
|
||||
#define SOC_LEDC_CHANNEL_NUM (8)
|
||||
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (20)
|
||||
|
|
|
@ -1,16 +1,9 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_LEDC_STRUCT_H_
|
||||
#define _SOC_LEDC_STRUCT_H_
|
||||
#ifdef __cplusplus
|
||||
|
@ -84,7 +77,7 @@ typedef volatile struct ledc_dev_s {
|
|||
uint32_t clock_divider: 18;
|
||||
uint32_t pause: 1;
|
||||
uint32_t rst: 1;
|
||||
uint32_t tick_sel: 1;
|
||||
uint32_t reserved24: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
|
|
|
@ -1,16 +1,8 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_LEDC_STRUCT_H_
|
||||
#define _SOC_LEDC_STRUCT_H_
|
||||
#ifdef __cplusplus
|
||||
|
@ -84,7 +76,7 @@ typedef volatile struct ledc_dev_s {
|
|||
uint32_t clock_divider: 18;
|
||||
uint32_t pause: 1;
|
||||
uint32_t rst: 1;
|
||||
uint32_t tick_sel: 1;
|
||||
uint32_t reserved24: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
|
|
|
@ -157,6 +157,8 @@
|
|||
#define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
#define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX (1)
|
||||
#define SOC_LEDC_SUPPORT_REF_TICK (1)
|
||||
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
|
||||
#define SOC_LEDC_CHANNEL_NUM (8)
|
||||
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
|
||||
|
|
|
@ -1,15 +1,8 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
|
@ -17,6 +10,8 @@
|
|||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SOC_LEDC_HAS_TIMER_SPECIFIC_MUX (1)
|
||||
#define SOC_LEDC_SUPPORT_REF_TICK (1)
|
||||
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
|
||||
#define SOC_LEDC_CHANNEL_NUM 8
|
||||
#define SOC_LEDC_TIMER_BIT_WIDE_NUM (14)
|
||||
|
|
Ładowanie…
Reference in New Issue