kopia lustrzana https://github.com/espressif/esp-idf
rodzic
1877a9fcd8
commit
62ee29250e
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@ -18,7 +18,7 @@
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#include "soc/rtc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/efuse_periph.h"
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#include "soc/gpio_reg.h"
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#include "soc/gpio_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "i2c_rtc_clk.h"
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#include "i2c_rtc_clk.h"
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@ -197,31 +197,26 @@ rtc_vddsdio_config_t rtc_vddsdio_get_config()
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result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
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result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
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result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
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result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
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return result;
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return result;
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}
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} else {
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// TODO: rtc_vddsdio_get_config: implement efuse part for esp32s2beta - IDF-749
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#if 0
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uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
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if (efuse_reg & EFUSE_RD_SDIO_FORCE) {
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// Get configuration from EFUSE
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result.force = 0;
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result.force = 0;
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result.enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S;
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}
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result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S;
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uint32_t efuse_reg = REG_READ(EFUSE_RD_REPEAT_DATA1_REG);
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//DREFH/M/L eFuse are used for EFUSE_ADC_VREF instead. Therefore tuning
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if (efuse_reg & EFUSE_SDIO_FORCE) {
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//will only be available on older chips that don't have EFUSE_ADC_VREF
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// Get configuration from EFUSE
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if(REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG ,EFUSE_RD_BLK3_PART_RESERVE) == 0){
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result.enable = (efuse_reg & EFUSE_SDIO_XPD_M) >> EFUSE_SDIO_XPD_S;
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//BLK3_PART_RESERVE indicates the presence of EFUSE_ADC_VREF
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result.tieh = (efuse_reg & EFUSE_SDIO_TIEH_M) >> EFUSE_SDIO_TIEH_S;
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// in this case, DREFH/M/L are also set from EFUSE
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result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S;
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result.drefm = (efuse_reg & EFUSE_SDIO_DREFM_M) >> EFUSE_SDIO_DREFM_S;
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result.drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) >> EFUSE_RD_SDIO_DREFM_S;
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result.drefl = (efuse_reg & EFUSE_SDIO_DREFL_M) >> EFUSE_SDIO_DREFL_S;
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result.drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) >> EFUSE_RD_SDIO_DREFL_S;
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}
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efuse_reg = REG_READ(EFUSE_RD_REPEAT_DATA0_REG);
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result.drefh = (efuse_reg & EFUSE_SDIO_DREFH_M) >> EFUSE_SDIO_DREFH_S;
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return result;
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return result;
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}
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}
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#endif
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// Otherwise, VDD_SDIO is controlled by bootstrapping pin
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// Otherwise, VDD_SDIO is controlled by bootstrapping pin
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uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
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uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
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result.force = 0;
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result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
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result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
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result.enable = 1;
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result.enable = 1;
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return result;
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return result;
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