From 4acfe1a91a6434f14b88b43c06deee59189f5465 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Mon, 17 Oct 2022 16:04:58 +0800 Subject: [PATCH] ulp-riscv: always force COCPU clock on S3 The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU --- components/ulp/ulp_riscv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/components/ulp/ulp_riscv.c b/components/ulp/ulp_riscv.c index 2c56ca119e..6e39254206 100644 --- a/components/ulp/ulp_riscv.c +++ b/components/ulp/ulp_riscv.c @@ -56,12 +56,15 @@ esp_err_t ulp_riscv_run(void) return ESP_OK; #elif CONFIG_IDF_TARGET_ESP32S3 /* Reset COCPU when power on. */ - SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); esp_rom_delay_us(20); - CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); + /* The coprocessor cpu trap signal doesnt have a stable reset value, + force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ + SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); + + /* Disable ULP timer */ CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); /* wait for at least 1 RTC_SLOW_CLK cycle */