kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/rtcio_increase_size_v4.4' into 'release/v4.4'
sleep: fixed ext1 cannot wakeup via RTCIO >= 18 issue (v4.4) See merge request espressif/esp-idf!17201pull/8460/head
commit
5f56bbd2d0
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@ -140,7 +140,7 @@ typedef struct {
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uint64_t sleep_duration;
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uint32_t wakeup_triggers : 15;
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uint32_t ext1_trigger_mode : 1;
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uint32_t ext1_rtc_gpio_mask : 18;
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uint32_t ext1_rtc_gpio_mask : 22; //22 is the maximum RTCIO number in all chips
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uint32_t ext0_trigger_level : 1;
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uint32_t ext0_rtc_gpio_num : 5;
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uint32_t gpio_wakeup_mask : 6;
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@ -152,6 +152,9 @@ typedef struct {
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uint64_t rtc_ticks_at_sleep_start;
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} sleep_config_t;
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_Static_assert(22 >= SOC_RTCIO_PIN_COUNT, "Chip has more RTCIOs than 22, should increase ext1_rtc_gpio_mask field size");
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static sleep_config_t s_config = {
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.pd_options = {
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ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO,
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@ -175,7 +175,7 @@
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
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* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
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#define SOC_RTCIO_PIN_COUNT 0
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#define SOC_RTCIO_PIN_COUNT (0U)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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@ -163,7 +163,7 @@
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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/* No dedicated RTCIO subsystem on ESP32-C3. RTC functions are still supported
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* for hold, wake & 32kHz crystal functions - via rtc_cntl_reg */
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#define SOC_RTCIO_PIN_COUNT 0
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#define SOC_RTCIO_PIN_COUNT (0U)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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