diff --git a/components/esp_hw_support/cpu_util.c b/components/esp_hw_support/cpu_util.c
index 847695d368..bd01235d6c 100644
--- a/components/esp_hw_support/cpu_util.c
+++ b/components/esp_hw_support/cpu_util.c
@@ -81,7 +81,8 @@ bool IRAM_ATTR esp_cpu_in_ocd_debug_mode(void)
 #if CONFIG_ESP32_DEBUG_OCDAWARE || \
     CONFIG_ESP32S2_DEBUG_OCDAWARE || \
     CONFIG_ESP32S3_DEBUG_OCDAWARE || \
-    CONFIG_ESP32C3_DEBUG_OCDAWARE
+    CONFIG_ESP32C3_DEBUG_OCDAWARE || \
+    CONFIG_ESP32H2_DEBUG_OCDAWARE
     return cpu_ll_is_debugger_attached();
 #else
     return false; // Always return false if "OCD aware" is disabled
diff --git a/components/esp_hw_support/esp_clk.c b/components/esp_hw_support/esp_clk.c
index 4d23b7b799..8328b4d05e 100644
--- a/components/esp_hw_support/esp_clk.c
+++ b/components/esp_hw_support/esp_clk.c
@@ -36,6 +36,10 @@
 #include "esp32c3/rom/rtc.h"
 #include "esp32c3/clk.h"
 #include "esp32c3/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/rtc.h"
+#include "esp32h2/clk.h"
+#include "esp32h2/rtc.h"
 #endif
 
 #define MHZ (1000000)
@@ -53,7 +57,7 @@ static RTC_DATA_ATTR uint64_t s_esp_rtc_time_us = 0, s_rtc_last_ticks = 0;
 
 inline static int IRAM_ATTR s_get_cpu_freq_mhz(void)
 {
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
     return ets_get_cpu_frequency();
 #else
     return g_ticks_per_us_pro;
@@ -75,7 +79,7 @@ int IRAM_ATTR esp_clk_xtal_freq(void)
     return rtc_clk_xtal_freq_get() * MHZ;
 }
 
-#ifndef CONFIG_IDF_TARGET_ESP32C3
+#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
 void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
 {
     /* Update scale factors used by esp_rom_delay_us */
diff --git a/components/esp_hw_support/hw_random.c b/components/esp_hw_support/hw_random.c
index 76ee21d8ad..05b60b4028 100644
--- a/components/esp_hw_support/hw_random.c
+++ b/components/esp_hw_support/hw_random.c
@@ -29,6 +29,8 @@
 #include "esp32s3/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/clk.h"
 #endif
 
 uint32_t IRAM_ATTR esp_random(void)
diff --git a/components/esp_hw_support/include/esp_chip_info.h b/components/esp_hw_support/include/esp_chip_info.h
index 35b191ac25..d04dcaf424 100644
--- a/components/esp_hw_support/include/esp_chip_info.h
+++ b/components/esp_hw_support/include/esp_chip_info.h
@@ -32,6 +32,7 @@ typedef enum {
     CHIP_ESP32S2 = 2, //!< ESP32-S2
     CHIP_ESP32S3 = 4, //!< ESP32-S3
     CHIP_ESP32C3 = 5, //!< ESP32-C3
+    CHIP_ESP32H2 = 6, //!< ESP32-H2
 } esp_chip_model_t;
 
 /* Chip feature flags, used in esp_chip_info_t */
@@ -39,6 +40,7 @@ typedef enum {
 #define CHIP_FEATURE_WIFI_BGN       BIT(1)      //!< Chip has 2.4GHz WiFi
 #define CHIP_FEATURE_BLE            BIT(4)      //!< Chip has Bluetooth LE
 #define CHIP_FEATURE_BT             BIT(5)      //!< Chip has Bluetooth Classic
+#define CHIP_FEATURE_IEEE802154     BIT(6)      //!< Chip has IEEE 802.15.4
 
 /**
  * @brief The structure represents information about the chip
diff --git a/components/esp_hw_support/include/esp_mac.h b/components/esp_hw_support/include/esp_mac.h
index 698ccaa6e2..0d23d0142a 100644
--- a/components/esp_hw_support/include/esp_mac.h
+++ b/components/esp_hw_support/include/esp_mac.h
@@ -26,6 +26,7 @@ typedef enum {
     ESP_MAC_WIFI_SOFTAP,
     ESP_MAC_BT,
     ESP_MAC_ETH,
+    ESP_MAC_IEEE802154,
 } esp_mac_type_t;
 
 /** @cond */
@@ -39,6 +40,8 @@ typedef enum {
 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S3_UNIVERSAL_MAC_ADDRESSES
 #elif CONFIG_IDF_TARGET_ESP32C3
 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32H2_UNIVERSAL_MAC_ADDRESSES
 #endif
 /** @endcond */
 
diff --git a/components/esp_hw_support/include/soc_log.h b/components/esp_hw_support/include/soc_log.h
index 894f0962ce..ea2ecce8f8 100644
--- a/components/esp_hw_support/include/soc_log.h
+++ b/components/esp_hw_support/include/soc_log.h
@@ -41,6 +41,8 @@
 #include "esp32s3/rom/ets_sys.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/ets_sys.h"
 #endif
 
 #define SOC_LOGE(tag, fmt, ...) esp_rom_printf("%s(err): " fmt, tag, ##__VA_ARGS__)
diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf
index f0d4a3cceb..9d3b3354b0 100644
--- a/components/esp_hw_support/linker.lf
+++ b/components/esp_hw_support/linker.lf
@@ -9,5 +9,5 @@ entries:
     rtc_pm (noflash_text)
     rtc_sleep (noflash_text)
     rtc_time (noflash_text)
-    if IDF_TARGET_ESP32C3 = n:
+    if IDF_TARGET_ESP32C3 = n && IDF_TARGET_ESP32H2 = n:
         rtc_wdt (noflash_text)
diff --git a/components/esp_hw_support/port/esp32h2/CMakeLists.txt b/components/esp_hw_support/port/esp32h2/CMakeLists.txt
index 99b1f7929b..98a188b679 100644
--- a/components/esp_hw_support/port/esp32h2/CMakeLists.txt
+++ b/components/esp_hw_support/port/esp32h2/CMakeLists.txt
@@ -1,4 +1,4 @@
-set(srcs "cpu_util_esp32c3.c"
+set(srcs "cpu_util_esp32h2.c"
          "rtc_clk_init.c"
          "rtc_clk.c"
          "rtc_init.c"
diff --git a/components/esp_hw_support/port/esp32h2/Kconfig.mac b/components/esp_hw_support/port/esp32h2/Kconfig.mac
index ea53535782..4135169df0 100644
--- a/components/esp_hw_support/port/esp32h2/Kconfig.mac
+++ b/components/esp_hw_support/port/esp32h2/Kconfig.mac
@@ -1,43 +1,18 @@
-choice ESP32C3_UNIVERSAL_MAC_ADDRESSES
+# ESP32H2-TODO: IDF-3390
+choice ESP32H2_UNIVERSAL_MAC_ADDRESSES
     bool "Number of universally administered (by IEEE) MAC address"
-    default ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
+    default ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
     help
         Configure the number of universally administered (by IEEE) MAC addresses.
-
         During initialization, MAC addresses for each network interface are generated or derived from a
         single base MAC address.
 
-        If the number of universal MAC addresses is four, all four interfaces (WiFi station, WiFi softap,
-        Bluetooth and Ethernet) receive a universally administered MAC address. These are generated
-        sequentially by adding 0, 1, 2 and 3 (respectively) to the final octet of the base MAC address.
-
-        If the number of universal MAC addresses is two, only two interfaces (WiFi station and Bluetooth)
-        receive a universally administered MAC address. These are generated sequentially by adding 0
-        and 1 (respectively) to the base MAC address. The remaining two interfaces (WiFi softap and Ethernet)
-        receive local MAC addresses. These are derived from the universal WiFi station and Bluetooth MAC
-        addresses, respectively.
-
-        When using the default (Espressif-assigned) base MAC address, either setting can be used. When using
-        a custom universal MAC address range, the correct setting will depend on the allocation of MAC
-        addresses in this range (either 2 or 4 per device.)
-
-        Note that ESP32-C3 has no integrated Ethernet MAC. Although it's possible to use the esp_read_mac()
-        API to return a MAC for Ethernet, this can only be used with an external MAC peripheral.
-
-    config ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
+    config ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
         bool "Two"
-        select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
+        select ESP_MAC_ADDR_UNIVERSE_IEEE802154
         select ESP_MAC_ADDR_UNIVERSE_BT
-
-    config ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
-        bool "Four"
-        select ESP_MAC_ADDR_UNIVERSE_WIFI_STA
-        select ESP_MAC_ADDR_UNIVERSE_WIFI_AP
-        select ESP_MAC_ADDR_UNIVERSE_BT
-        select ESP_MAC_ADDR_UNIVERSE_ETH
 endchoice
 
-config ESP32C3_UNIVERSAL_MAC_ADDRESSES
+config ESP32H2_UNIVERSAL_MAC_ADDRESSES
     int
-    default 2 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_TWO
-    default 4 if ESP32C3_UNIVERSAL_MAC_ADDRESSES_FOUR
+    default 2 if ESP32H2_UNIVERSAL_MAC_ADDRESSES_TWO
diff --git a/components/esp_hw_support/port/esp32h2/chip_info.c b/components/esp_hw_support/port/esp32h2/chip_info.c
index ffd37a23c0..5664ca34b6 100644
--- a/components/esp_hw_support/port/esp32h2/chip_info.c
+++ b/components/esp_hw_support/port/esp32h2/chip_info.c
@@ -19,8 +19,8 @@
 void esp_chip_info(esp_chip_info_t *out_info)
 {
     memset(out_info, 0, sizeof(*out_info));
-    out_info->model = CHIP_ESP32C3;
+    out_info->model = CHIP_ESP32H2;
     out_info->revision = esp_efuse_get_chip_ver();
     out_info->cores = 1;
-    out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
+    out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;
 }
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk.c b/components/esp_hw_support/port/esp32h2/rtc_clk.c
index f47848a523..805c378458 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_clk.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_clk.c
@@ -18,10 +18,10 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "sdkconfig.h"
-#include "esp32c3/rom/ets_sys.h"
-#include "esp32c3/rom/rtc.h"
-#include "esp32c3/rom/uart.h"
-#include "esp32c3/rom/gpio.h"
+#include "esp32h2/rom/ets_sys.h"
+#include "esp32h2/rom/rtc.h"
+#include "esp32h2/rom/uart.h"
+#include "esp32h2/rom/gpio.h"
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/efuse_reg.h"
@@ -93,32 +93,34 @@ bool rtc_clk_32k_enabled(void)
 void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
 {
     if (clk_8m_en) {
-        CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
+        // CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); // ESP32H2-TODO: IDF-3396
         /* no need to wait once enabled by software */
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
         esp_rom_delay_us(DELAY_8M_ENABLE);
     } else {
-        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
+        // SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
         REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
     }
     /* d256 should be independent configured with 8M
      * Maybe we can split this function into 8m and dmd256
      */
     if (d256_en) {
-        CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
+        // CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
     } else {
-        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
+        // SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
     }
 }
 
 bool rtc_clk_8m_enabled(void)
 {
-    return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
+    return false;
+    // return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0; // ESP32H2-TODO: IDF-3396
 }
 
 bool rtc_clk_8md256_enabled(void)
 {
-    return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
+    return false;
+    // return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0; // ESP32H2-TODO: IDF-3396
 }
 
 void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
@@ -191,7 +193,7 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
     SET_PERI_REG_MASK(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
     if (pll_freq == RTC_PLL_FREQ_480M) {
         /* Set this register to let the digital part know 480M PLL is used */
-        SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
+        // SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); // ESP32H2-TODO: IDF-3396
         /* Configure 480M PLL */
         switch (xtal_freq) {
         case RTC_XTAL_FREQ_40M:
@@ -225,7 +227,7 @@ void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
         REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
     } else {
         /* Clear this register to let the digital part know 320M PLL is used */
-        CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
+        // CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); // ESP32H2-TODO: IDF-3396
         /* Configure 320M PLL */
         switch (xtal_freq) {
         case RTC_XTAL_FREQ_40M:
@@ -289,7 +291,7 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
         SOC_LOGE(TAG, "invalid frequency");
         abort();
     }
-    REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf);
+    // REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf); // ESP32H2-TODO: IDF-3396
     REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0);
     REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
     rtc_clk_apb_freq_update(80 * MHZ);
@@ -375,21 +377,11 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
     }
     break;
     case DPORT_SOC_CLK_SEL_PLL: {
-        source = RTC_CPU_FREQ_SRC_PLL;
-        uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL);
-        uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
-        source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M;
-        if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) {
-            div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4;
-            freq_mhz = 80;
-        } else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) {
-            div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2;
-            div = 3;
-            freq_mhz = 160;
-        } else {
-            SOC_LOGE(TAG, "unsupported frequency configuration");
-            abort();
-        }
+        // ESP32H2-TODO: IDF-3396
+        source = 0;
+        div = 0;
+        source_freq_mhz = 0;
+        freq_mhz = 0;
         break;
     }
     case DPORT_SOC_CLK_SEL_8M:
diff --git a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c
index ca9dd74cba..3cf971437a 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_clk_init.c
@@ -16,9 +16,9 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <stdlib.h>
-#include "esp32c3/rom/ets_sys.h"
-#include "esp32c3/rom/rtc.h"
-#include "esp32c3/rom/uart.h"
+#include "esp32h2/rom/ets_sys.h"
+#include "esp32h2/rom/rtc.h"
+#include "esp32h2/rom/uart.h"
 #include "soc/rtc.h"
 #include "soc/rtc_periph.h"
 #include "soc/efuse_periph.h"
diff --git a/components/esp_hw_support/port/esp32h2/rtc_init.c b/components/esp_hw_support/port/esp32h2/rtc_init.c
index 7a33720bea..89c0b1a5d1 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_init.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_init.c
@@ -31,7 +31,6 @@ static const char *TAG = "rtc_init";
 
 static void set_ocode_by_efuse(int calib_version);
 static void calibrate_ocode(void);
-static void set_rtc_dig_dbias(void);
 
 void rtc_init(rtc_config_t cfg)
 {
@@ -56,21 +55,7 @@ void rtc_init(rtc_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
     REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
 
-    if (cfg.cali_ocode) {
-        uint32_t rtc_calib_version = 0;
-        esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
-        if (err != ESP_OK) {
-            rtc_calib_version = 0;
-            SOC_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
-        }
-        if (rtc_calib_version == 1) {
-            set_ocode_by_efuse(rtc_calib_version);
-        } else {
-            calibrate_ocode();
-        }
-    }
-
-    set_rtc_dig_dbias();
+    // set_rtc_dig_dbias(); // ESP32H2-TODO: IDF-3396
 
     if (cfg.clkctl_init) {
         //clear CMMU clock force on
@@ -255,85 +240,3 @@ static void calibrate_ocode(void)
     }
     rtc_clk_cpu_freq_set_config(&old_config);
 }
-
-static uint32_t get_dig_dbias_by_efuse(uint8_t chip_version)
-{
-    assert(chip_version >= 3);
-    uint32_t dig_dbias = 28;
-    esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_DIG_DBIAS_HVT, &dig_dbias, 5);
-    if (err != ESP_OK) {
-        dig_dbias = 28;
-        SOC_LOGW(TAG, "efuse read fail, set default dig_dbias value: %d\n", dig_dbias);
-    }
-    return dig_dbias;
-}
-
-uint32_t get_rtc_dbias_by_efuse(uint8_t chip_version, uint32_t dig_dbias)
-{
-    assert(chip_version >= 3);
-    uint32_t rtc_dbias = 0;
-    signed int k_rtc_ldo = 0, k_dig_ldo = 0, v_rtc_bias20 = 0, v_dig_bias20 = 0;
-    esp_err_t err0 = esp_efuse_read_field_blob(ESP_EFUSE_K_RTC_LDO, &k_rtc_ldo, 7);
-    esp_err_t err1 = esp_efuse_read_field_blob(ESP_EFUSE_K_DIG_LDO, &k_dig_ldo, 7);
-    esp_err_t err2 = esp_efuse_read_field_blob(ESP_EFUSE_V_RTC_DBIAS20, &v_rtc_bias20, 8);
-    esp_err_t err3 = esp_efuse_read_field_blob(ESP_EFUSE_V_DIG_DBIAS20, &v_dig_bias20, 8);
-    if ((err0 != ESP_OK) | (err1 != ESP_OK) | (err2 != ESP_OK) | (err3 != ESP_OK)) {
-        k_rtc_ldo = 0;
-        k_dig_ldo = 0;
-        v_rtc_bias20 = 0;
-        v_dig_bias20 = 0;
-        SOC_LOGW(TAG, "efuse read fail, k_rtc_ldo: %d, k_dig_ldo: %d, v_rtc_bias20: %d,  v_dig_bias20: %d\n", k_rtc_ldo, k_dig_ldo, v_rtc_bias20, v_dig_bias20);
-    }
-
-    k_rtc_ldo =  ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): k_rtc_ldo;
-    k_dig_ldo =  ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
-    v_rtc_bias20 =  ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
-    v_dig_bias20 =  ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
-
-    uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
-    uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
-    signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
-    signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
-    uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
-    uint32_t v_rtc_nearest_1v15_mul10000 = 0;
-    for (rtc_dbias = 15; rtc_dbias < 32; rtc_dbias++) {
-        v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
-        if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250)
-            break;
-    }
-    return rtc_dbias;
-}
-
-static void set_rtc_dig_dbias()
-{
-    /*
-    1. a reasonable dig_dbias which by scaning pvt to make 160 CPU run successful stored in efuse;
-    2. also we store some value in efuse, include:
-        k_rtc_ldo (slope of rtc voltage & rtc_dbias);
-        k_dig_ldo (slope of digital voltage & digital_dbias);
-        v_rtc_bias20 (rtc voltage when rtc dbais is 20);
-        v_dig_bias20 (digital voltage when digital dbais is 20).
-    3. a reasonable rtc_dbias can be calculated by a certion formula.
-    */
-    uint32_t rtc_dbias = 28, dig_dbias = 28;
-    uint8_t chip_version = esp_efuse_get_chip_ver();
-    if (chip_version >= 3) {
-        dig_dbias = get_dig_dbias_by_efuse(chip_version);
-        if (dig_dbias != 0) {
-            if (dig_dbias + 4 > 28) {
-                dig_dbias = 28;
-            } else {
-                dig_dbias += 4;
-            }
-            rtc_dbias = get_rtc_dbias_by_efuse(chip_version, dig_dbias); // already burn dig_dbias in efuse
-        } else {
-            dig_dbias = 28;
-            SOC_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in chip version: 0%d\n", chip_version);
-        }
-    }
-    else {
-        SOC_LOGD(TAG, "chip_version is less than 3, not burn core voltage in efuse\n");
-    }
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, rtc_dbias);
-    REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, dig_dbias);
-}
diff --git a/components/esp_hw_support/port/esp32h2/rtc_sleep.c b/components/esp_hw_support/port/esp32h2/rtc_sleep.c
index 1cdc56f2d3..cb61062412 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_sleep.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_sleep.c
@@ -26,8 +26,8 @@
 #include "soc/timer_group_reg.h"
 #include "soc/system_reg.h"
 #include "soc/rtc.h"
-#include "esp32c3/rom/ets_sys.h"
-#include "esp32c3/rom/rtc.h"
+#include "esp32h2/rom/ets_sys.h"
+#include "esp32h2/rom/rtc.h"
 #include "regi2c_ctrl.h"
 #include "esp_efuse.h"
 
@@ -97,11 +97,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
         REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
         CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
         unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
-    #if CONFIG_ESP32C3_REV_MIN < 3
-        if (esp_efuse_get_chip_ver() < 3) {
-            atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */
-        }
-    #endif
+
         REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, atten_deep_sleep);
         SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
         CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
diff --git a/components/esp_hw_support/port/esp32h2/rtc_time.c b/components/esp_hw_support/port/esp32h2/rtc_time.c
index 7792d5cf13..22ffb959c7 100644
--- a/components/esp_hw_support/port/esp32h2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_time.c
@@ -13,7 +13,7 @@
 // limitations under the License.
 
 #include <stdint.h>
-#include "esp32c3/rom/ets_sys.h"
+#include "esp32h2/rom/ets_sys.h"
 #include "soc/rtc.h"
 #include "soc/rtc_cntl_reg.h"
 #include "soc/timer_group_reg.h"
@@ -39,7 +39,7 @@
  */
 uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
 {
-    /* On ESP32C3, choosing RTC_CAL_RTC_MUX results in calibration of
+    /* On ESP32H2, choosing RTC_CAL_RTC_MUX results in calibration of
      * the 150k RTC clock regardless of the currenlty selected SLOW_CLK.
      * On the ESP32, it used the currently selected SLOW_CLK.
      * The following code emulates ESP32 behavior:
@@ -59,7 +59,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
     }
 
     if (cal_clk == RTC_CAL_8MD256) {
-        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
+        // SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); // ESP32H2-TODO: IDF-3396
     }
     /* Prepare calibration */
     REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
@@ -110,7 +110,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
 
     if (cal_clk == RTC_CAL_8MD256) {
-        CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
+        // CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN); // ESP32H2-TODO: IDF-3396
     }
 
     return cal_val;
diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c
index 9c1562de7b..fe9c7f3220 100644
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@@ -72,6 +72,12 @@
 #include "esp32c3/rom/rtc.h"
 #include "soc/extmem_reg.h"
 #include "esp_heap_caps.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/clk.h"
+#include "esp32h2/rom/cache.h"
+#include "esp32h2/rom/rtc.h"
+#include "soc/extmem_reg.h"
+#include "esp_heap_caps.h"
 #endif
 
 // If light sleep time is less than that, don't power down flash
@@ -99,12 +105,17 @@
 #define DEFAULT_CPU_FREQ_MHZ                CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
 #define DEFAULT_SLEEP_OUT_OVERHEAD_US       (105)
 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (37)
+#elif CONFIG_IDF_TARGET_ESP32H2
+#define DEFAULT_CPU_FREQ_MHZ                CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ
+#define DEFAULT_SLEEP_OUT_OVERHEAD_US       (105)
+#define DEFAULT_HARDWARE_OUT_OVERHEAD_US    (37)
 #endif
 
 #define LIGHT_SLEEP_TIME_OVERHEAD_US        DEFAULT_HARDWARE_OUT_OVERHEAD_US
 #if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS)   || \
     defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS) || \
     defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS) || \
+    defined(CONFIG_ESP32H2_RTC_CLK_SRC_EXT_CRYS) || \
     defined(CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS)
 #define DEEP_SLEEP_TIME_OVERHEAD_US         (650 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
 #else
diff --git a/components/esp_hw_support/test/test_rtc_clk.c b/components/esp_hw_support/test/test_rtc_clk.c
index 8d0496efdb..b2f0ef25f2 100644
--- a/components/esp_hw_support/test/test_rtc_clk.c
+++ b/components/esp_hw_support/test/test_rtc_clk.c
@@ -38,6 +38,10 @@
 #include "esp32c3/rtc.h"
 #include "esp32c3/clk.h"
 #include "esp32c3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rtc.h"
+#include "esp32h2/clk.h"
+#include "esp32h2/rom/rtc.h"
 #endif
 
 extern void rtc_clk_select_rtc_slow_clk(void);
diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt
index c1607cbf68..257ae1e65d 100644
--- a/components/esp_system/CMakeLists.txt
+++ b/components/esp_system/CMakeLists.txt
@@ -22,7 +22,7 @@ else()
             "task_wdt.c"
             "ubsan.c")
 
-    if(NOT (${target} STREQUAL "esp32c3") )
+    if(NOT (${target} STREQUAL "esp32c3") AND NOT (${target} STREQUAL "esp32h2"))
         list(APPEND srcs  "dbg_stubs.c")
     endif()
 
diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig
index d43a0d9ad2..fcf347461a 100644
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@@ -77,6 +77,7 @@ menu "ESP System Settings"
         default y if IDF_TARGET_ESP32S2
         default y if IDF_TARGET_ESP32C3
         default y if IDF_TARGET_ESP32S3
+        default y if IDF_TARGET_ESP32H2
 
     config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
         bool "Enable RTC fast memory for dynamic allocations"
@@ -84,6 +85,7 @@ menu "ESP System Settings"
         default y if IDF_TARGET_ESP32S2
         default y if IDF_TARGET_ESP32C3
         default n if IDF_TARGET_ESP32S3  # TODO
+        default y if IDF_TARGET_ESP32H2
         depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
         help
             This config option allows to add RTC fast memory region to system heap with capability
@@ -95,7 +97,7 @@ menu "ESP System Settings"
 
         config ESP_SYSTEM_MEMPROT_FEATURE
             bool "Enable memory protection"
-            depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S2
+            depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32H2
             default "y"
             help
                 If enabled, the permission control module watches all the memory access and fires the panic handler
@@ -208,7 +210,7 @@ menu "ESP System Settings"
 
     config ESP_CONSOLE_MULTIPLE_UART
         bool
-        default y if !IDF_TARGET_ESP32C3
+        default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2
 
     choice ESP_CONSOLE_UART_NUM
         prompt "UART peripheral to use for console output (0-1)"
diff --git a/components/esp_system/crosscore_int.c b/components/esp_system/crosscore_int.c
index 113e935706..1ee177fe98 100644
--- a/components/esp_system/crosscore_int.c
+++ b/components/esp_system/crosscore_int.c
@@ -24,14 +24,14 @@
 
 #if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
 #include "soc/dport_reg.h"
-#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2
 #include "soc/system_reg.h"
 #endif
 
 #define REASON_YIELD            BIT(0)
 #define REASON_FREQ_SWITCH      BIT(1)
 
-#if !CONFIG_IDF_TARGET_ESP32C3
+#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
 #define REASON_PRINT_BACKTRACE  BIT(2)
 #endif
 
@@ -67,7 +67,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
     } else {
         WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
     }
-#elif CONFIG_IDF_TARGET_ESP32C3
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
     WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
 #endif
 
@@ -87,7 +87,7 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
          * to allow DFS features without the extra latency of the ISR hook.
          */
     }
-#if !CONFIG_IDF_TARGET_ESP32C3 // IDF-2986
+#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 // IDF-2986
     if (my_reason_val & REASON_PRINT_BACKTRACE) {
         esp_backtrace_print(100);
     }
@@ -134,7 +134,7 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
     } else {
         WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
     }
-#elif CONFIG_IDF_TARGET_ESP32C3
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
     WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
 #endif
 }
@@ -149,7 +149,7 @@ void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
     esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
 }
 
-#if !CONFIG_IDF_TARGET_ESP32C3
+#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
 void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
 {
     esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
diff --git a/components/esp_system/esp_system.c b/components/esp_system/esp_system.c
index d645b47f95..4a3e725bbd 100644
--- a/components/esp_system/esp_system.c
+++ b/components/esp_system/esp_system.c
@@ -28,6 +28,8 @@
 #include "esp32s3/memprot.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/memprot.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/memprot.h"
 #endif
 
 #define SHUTDOWN_HANDLERS_NO 4
diff --git a/components/esp_system/fpga_overrides.c b/components/esp_system/fpga_overrides.c
index 5f222e7aef..acb1fb38e4 100644
--- a/components/esp_system/fpga_overrides.c
+++ b/components/esp_system/fpga_overrides.c
@@ -44,6 +44,8 @@ void bootloader_clock_configure(void)
     uint32_t xtal_freq_mhz = 40;
 #ifdef CONFIG_IDF_TARGET_ESP32S2
     uint32_t apb_freq_hz = 20000000;
+#elif CONFIG_IDF_TARGET_ESP32S2H2
+    uint32_t apb_freq_hz = 32000000;
 #else
     uint32_t apb_freq_hz = 40000000;
 #endif // CONFIG_IDF_TARGET_ESP32S2
diff --git a/components/esp_system/include/esp_private/crosscore_int.h b/components/esp_system/include/esp_private/crosscore_int.h
index 1d6ec809b9..aea75644b1 100644
--- a/components/esp_system/include/esp_private/crosscore_int.h
+++ b/components/esp_system/include/esp_private/crosscore_int.h
@@ -57,7 +57,7 @@ void esp_crosscore_int_send_yield(int core_id);
 void esp_crosscore_int_send_freq_switch(int core_id);
 
 
-#if !CONFIG_IDF_TARGET_ESP32C3
+#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2
 /**
  * Send an interrupt to a CPU indicating it should print its current backtrace
  *
diff --git a/components/esp_system/port/arch/riscv/panic_arch.c b/components/esp_system/port/arch/riscv/panic_arch.c
index 2ae38dea6b..5418aceb7b 100644
--- a/components/esp_system/port/arch/riscv/panic_arch.c
+++ b/components/esp_system/port/arch/riscv/panic_arch.c
@@ -21,7 +21,11 @@
 #include "cache_err_int.h"
 
 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
+#if CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/memprot.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/memprot.h"
+#endif
 #endif
 
 #define DIM(array) (sizeof(array)/sizeof(*array))
diff --git a/components/esp_system/port/brownout.c b/components/esp_system/port/brownout.c
index f65d31de5e..c8f72f300f 100644
--- a/components/esp_system/port/brownout.c
+++ b/components/esp_system/port/brownout.c
@@ -39,6 +39,8 @@
 #define BROWNOUT_DET_LVL CONFIG_ESP32S3_BROWNOUT_DET_LVL
 #elif defined(CONFIG_ESP32C3_BROWNOUT_DET_LVL)
 #define BROWNOUT_DET_LVL CONFIG_ESP32C3_BROWNOUT_DET_LVL
+#elif defined(CONFIG_ESP32H2_BROWNOUT_DET_LVL)
+#define BROWNOUT_DET_LVL CONFIG_ESP32H2_BROWNOUT_DET_LVL
 #else
 #define BROWNOUT_DET_LVL 0
 #endif
diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c
index b166e72eef..3adf0bc978 100644
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@@ -61,6 +61,12 @@
 #include "esp32c3/rom/rtc.h"
 #include "soc/cache_memory.h"
 #include "esp32c3/memprot.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rtc.h"
+#include "esp32h2/rom/cache.h"
+#include "esp32h2/rom/rtc.h"
+#include "soc/cache_memory.h"
+#include "esp32h2/memprot.h"
 #endif
 
 #include "spi_flash_private.h"
@@ -93,6 +99,8 @@
 #include "esp32s3/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rom/spi_flash.h"
 #endif
 #endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
 
@@ -353,14 +361,14 @@ void IRAM_ATTR call_start_cpu0(void)
     Cache_Resume_DCache(0);
 #endif // CONFIG_IDF_TARGET_ESP32S3
 
-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
     /* Configure the Cache MMU size for instruction and rodata in flash. */
     extern uint32_t Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
     extern int _rodata_reserved_start;
     uint32_t rodata_reserved_start_align = (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
     uint32_t cache_mmu_irom_size = ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * sizeof(uint32_t);
     Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
-#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#endif // CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
 
 #if CONFIG_ESPTOOLPY_OCT_FLASH
     bool efuse_opflash_en = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA3_REG, EFUSE_FLASH_TYPE);
@@ -483,7 +491,7 @@ void IRAM_ATTR call_start_cpu0(void)
 
 #ifdef CONFIG_ESP_CONSOLE_UART
     uint32_t clock_hz = rtc_clk_apb_freq_get();
-#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
+#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
     clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM
 #endif
     esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
diff --git a/components/esp_system/port/panic_handler.c b/components/esp_system/port/panic_handler.c
index 560e9ef8ea..d8993f8721 100644
--- a/components/esp_system/port/panic_handler.c
+++ b/components/esp_system/port/panic_handler.c
@@ -38,6 +38,8 @@
 #include "esp32s3/memprot.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/memprot.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/memprot.h"
 #endif
 
 #include "esp_private/panic_internal.h"
diff --git a/components/esp_system/port/soc/esp32h2/apb_backup_dma.c b/components/esp_system/port/soc/esp32h2/apb_backup_dma.c
index 24b0ad0e04..f41b32decf 100644
--- a/components/esp_system/port/soc/esp32h2/apb_backup_dma.c
+++ b/components/esp_system/port/soc/esp32h2/apb_backup_dma.c
@@ -19,7 +19,7 @@
 #include "esp_attr.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/portmacro.h"
-#include "esp32c3/rom/apb_backup_dma.h"
+#include "esp32h2/rom/apb_backup_dma.h"
 
 static portMUX_TYPE s_apb_backup_dma_mutex = portMUX_INITIALIZER_UNLOCKED;
 
diff --git a/components/esp_system/port/soc/esp32h2/cache_err_int.c b/components/esp_system/port/soc/esp32h2/cache_err_int.c
index 20cf2be2a2..cf70e63f71 100644
--- a/components/esp_system/port/soc/esp32h2/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32h2/cache_err_int.c
@@ -18,7 +18,7 @@
  to panic the CPU, which from a debugging perspective is better than grabbing bad
  data from the bus.
 */
-#include "esp32c3/rom/ets_sys.h"
+#include "esp32h2/rom/ets_sys.h"
 #include "esp_attr.h"
 #include "esp_intr_alloc.h"
 #include "soc/extmem_reg.h"
@@ -49,7 +49,7 @@ void esp_cache_err_int_init(void)
      *     4. icache preload configurations fault
      *     5. icache sync configuration fault
      *
-     * [1]: On ESP32C3 boards, the caches are shared but buses are still
+     * [1]: On ESP32H2 boards, the caches are shared but buses are still
      * distinct. So, we have an ibus and a dbus sharing the same cache.
      * This error can occur if the dbus performs a request but the icache
      * (or simply cache) is disabled.
diff --git a/components/esp_system/port/soc/esp32h2/clk.c b/components/esp_system/port/soc/esp32h2/clk.c
index ca993ddf4c..210e9af52d 100644
--- a/components/esp_system/port/soc/esp32h2/clk.c
+++ b/components/esp_system/port/soc/esp32h2/clk.c
@@ -19,11 +19,11 @@
 #include "sdkconfig.h"
 #include "esp_attr.h"
 #include "esp_log.h"
-#include "esp32c3/clk.h"
+#include "esp32h2/clk.h"
 #include "esp_clk_internal.h"
-#include "esp32c3/rom/ets_sys.h"
-#include "esp32c3/rom/uart.h"
-#include "esp32c3/rom/rtc.h"
+#include "esp32h2/rom/ets_sys.h"
+#include "esp32h2/rom/uart.h"
+#include "esp32h2/rom/rtc.h"
 #include "soc/system_reg.h"
 #include "soc/dport_access.h"
 #include "soc/soc.h"
@@ -41,7 +41,7 @@
  * Larger values increase startup delay. Smaller values may cause false positive
  * detection (i.e. oscillator runs for a few cycles and then stops).
  */
-#define SLOW_CLK_CAL_CYCLES     CONFIG_ESP32C3_RTC_CLK_CAL_CYCLES
+#define SLOW_CLK_CAL_CYCLES     CONFIG_ESP32H2_RTC_CLK_CAL_CYCLES
 
 #define MHZ (1000000)
 
@@ -102,11 +102,11 @@ static const char *TAG = "clk";
     wdt_hal_write_protect_enable(&rtc_wdt_ctx);
 #endif
 
-#if defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS)
+#if defined(CONFIG_ESP32H2_RTC_CLK_SRC_EXT_CRYS)
     select_rtc_slow_clk(SLOW_CLK_32K_XTAL);
-#elif defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_OSC)
+#elif defined(CONFIG_ESP32H2_RTC_CLK_SRC_EXT_OSC)
     select_rtc_slow_clk(SLOW_CLK_32K_EXT_OSC);
-#elif defined(CONFIG_ESP32C3_RTC_CLK_SRC_INT_8MD256)
+#elif defined(CONFIG_ESP32H2_RTC_CLK_SRC_INT_8MD256)
     select_rtc_slow_clk(SLOW_CLK_8MD256);
 #else
     select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
@@ -124,7 +124,7 @@ static const char *TAG = "clk";
     rtc_cpu_freq_config_t old_config, new_config;
     rtc_clk_cpu_freq_get_config(&old_config);
     const uint32_t old_freq_mhz = old_config.freq_mhz;
-    const uint32_t new_freq_mhz = CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ;
+    const uint32_t new_freq_mhz = CONFIG_ESP32H2_DEFAULT_CPU_FREQ_MHZ;
 
     bool res = rtc_clk_cpu_freq_mhz_to_config(new_freq_mhz, &new_config);
     assert(res);
@@ -235,7 +235,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
        ) {
         common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
         hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
-        wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
     } else {
         common_perip_clk = SYSTEM_WDG_CLK_EN |
                            SYSTEM_I2S0_CLK_EN |
@@ -262,10 +261,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
                              SYSTEM_CRYPTO_SHA_CLK_EN |
                              SYSTEM_CRYPTO_RSA_CLK_EN;
-        wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
-                           SYSTEM_WIFI_CLK_BT_EN_M |
-                           SYSTEM_WIFI_CLK_UNUSED_BIT5 |
-                           SYSTEM_WIFI_CLK_UNUSED_BIT12;
     }
 
     //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
@@ -307,15 +302,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
     CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
     SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
 
-    /* Disable WiFi/BT/SDIO clocks. */
-    CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
-    SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
-
-    /* Set WiFi light sleep clock source to RTC slow clock */
-    REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
-    CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
-    SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
-
     /* Enable RNG clock. */
     periph_module_enable(PERIPH_RNG_MODULE);
 }
diff --git a/components/esp_system/port/soc/esp32h2/reset_reason.c b/components/esp_system/port/soc/esp32h2/reset_reason.c
index 7487eb682a..d2aecd5a2c 100644
--- a/components/esp_system/port/soc/esp32h2/reset_reason.c
+++ b/components/esp_system/port/soc/esp32h2/reset_reason.c
@@ -13,7 +13,7 @@
 // limitations under the License.
 
 #include "esp_system.h"
-#include "esp32c3/rom/rtc.h"
+#include "esp32h2/rom/rtc.h"
 #include "esp_private/system_internal.h"
 #include "soc/rtc_periph.h"
 
diff --git a/components/esp_system/port/soc/esp32h2/system_internal.c b/components/esp_system/port/soc/esp32h2/system_internal.c
index 2dd27c0bf6..e280343136 100644
--- a/components/esp_system/port/soc/esp32h2/system_internal.c
+++ b/components/esp_system/port/soc/esp32h2/system_internal.c
@@ -33,8 +33,8 @@
 #include "hal/wdt_hal.h"
 #include "cache_err_int.h"
 
-#include "esp32c3/rom/cache.h"
-#include "esp32c3/rom/rtc.h"
+#include "esp32h2/rom/cache.h"
+#include "esp32h2/rom/rtc.h"
 
 /* "inner" restart function for after RTOS, interrupts & anything else on this
  * core are already stopped. Stalls other core, resets hardware,
@@ -92,17 +92,6 @@ void IRAM_ATTR esp_restart_noos(void)
     WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
     WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
 
-    // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
-    SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
-                      SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST |
-                      SYSTEM_BT_RST | SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST |
-                      SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
-                      SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | BLE_REG_REST_BIT
-                      |BLE_PWR_REG_REST_BIT | BLE_BB_REG_REST_BIT);
-
-
-    REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
-
     // Reset timer/spi/uart
     SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
                       SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST);
diff --git a/components/esp_system/sdkconfig.rename b/components/esp_system/sdkconfig.rename
index 5d113edd17..5dad89fa8f 100644
--- a/components/esp_system/sdkconfig.rename
+++ b/components/esp_system/sdkconfig.rename
@@ -14,6 +14,8 @@ CONFIG_ESP32S2_MEMPROT_FEATURE                          CONFIG_ESP_SYSTEM_MEMPRO
 CONFIG_ESP32S2_MEMPROT_FEATURE_LOCK                     CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
 CONFIG_ESP32C3_MEMPROT_FEATURE                          CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 CONFIG_ESP32C3_MEMPROT_FEATURE_LOCK                     CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
+CONFIG_ESP32H2_MEMPROT_FEATURE                          CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
+CONFIG_ESP32H2_MEMPROT_FEATURE_LOCK                     CONFIG_ESP_SYSTEM_MEMPROT_FEATURE_LOCK
 
 CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES                  CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES
 
diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c
index 93f7fc69f7..32cb377ed5 100644
--- a/components/esp_system/startup.c
+++ b/components/esp_system/startup.c
@@ -77,6 +77,8 @@
 #include "esp32s3/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/clk.h"
 #endif
 /***********************************************/
 
@@ -264,7 +266,8 @@ static void do_core_init(void)
 #if CONFIG_ESP32_BROWNOUT_DET   || \
     CONFIG_ESP32S2_BROWNOUT_DET || \
     CONFIG_ESP32S3_BROWNOUT_DET || \
-    CONFIG_ESP32C3_BROWNOUT_DET
+    CONFIG_ESP32C3_BROWNOUT_DET || \
+    CONFIG_ESP32H2_BROWNOUT_DET
     // [refactor-todo] leads to call chain rtc_is_register (driver) -> esp_intr_alloc (esp32/esp32s2) ->
     // malloc (newlib) -> heap_caps_malloc (heap), so heap must be at least initialized
     esp_brownout_init();
diff --git a/components/esp_system/system_time.c b/components/esp_system/system_time.c
index d8c16415fd..3c508ce73f 100644
--- a/components/esp_system/system_time.c
+++ b/components/esp_system/system_time.c
@@ -29,6 +29,8 @@
 #include "esp32s3/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/rtc.h"
 #endif
 
 #include "esp_private/startup_internal.h"
diff --git a/components/esp_system/task_wdt.c b/components/esp_system/task_wdt.c
index 26d716b452..4a08d85d45 100644
--- a/components/esp_system/task_wdt.c
+++ b/components/esp_system/task_wdt.c
@@ -184,7 +184,7 @@ static void task_wdt_isr(void *arg)
         abort();
     } else {
 
-#if !CONFIG_IDF_TARGET_ESP32C3 // TODO: ESP32-C3 IDF-2986
+#if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 // TODO: ESP32-C3 IDF-2986
         int current_core = xPortGetCoreID();
         //Print backtrace of current core
         ESP_EARLY_LOGE(TAG, "Print CPU %d (current core) backtrace", current_core);
diff --git a/components/esp_system/test/test_reset_reason.c b/components/esp_system/test/test_reset_reason.c
index 6f874590ba..3bcde7bf36 100644
--- a/components/esp_system/test/test_reset_reason.c
+++ b/components/esp_system/test/test_reset_reason.c
@@ -49,7 +49,7 @@ static RTC_SLOW_ATTR uint32_t s_rtc_force_slow_val;
 #define BROWNOUT            "BROWN_OUT_RST"
 #define STORE_ERROR         "StoreProhibited"
 
-#elif CONFIG_IDF_TARGET_ESP32C3
+#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
 #define DEEPSLEEP           "DSLEEP"
 #define LOAD_STORE_ERROR    "Store access fault"
 #define RESET               "RTC_SW_CPU_RST"
diff --git a/components/esp_system/test/test_sleep.c b/components/esp_system/test/test_sleep.c
index 0871cefd87..553754b36d 100644
--- a/components/esp_system/test/test_sleep.c
+++ b/components/esp_system/test/test_sleep.c
@@ -34,6 +34,9 @@
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/clk.h"
 #include "esp32c3/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/clk.h"
+#include "esp32h2/rom/rtc.h"
 #endif
 
 #define ESP_EXT0_WAKEUP_LEVEL_LOW 0
diff --git a/components/esp_system/test/test_system_time.c b/components/esp_system/test/test_system_time.c
index 7cd23cc1e5..24d28de489 100644
--- a/components/esp_system/test/test_system_time.c
+++ b/components/esp_system/test/test_system_time.c
@@ -11,6 +11,8 @@
 #include "esp32s3/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32H2
+#include "esp32h2/clk.h"
 #endif
 
 TEST_CASE("Test effect of rtc clk calibration compensation on system time", "[esp_system]")