kopia lustrzana https://github.com/espressif/esp-idf
fix(mbedtls/crypto_shared_gdma): Enable AXI-DMA enable external memory AES-ECC access
- When external memory encryption is enabled, set the aes_ecc bit of AXI-DMA to enable memory accesspull/13854/head
harshal.patil
rodzic
e2f6920c4f
commit
5dfbc47192
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@ -273,6 +273,14 @@ static inline void axi_dma_ll_rx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
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dev->in[channel].conf.in_conf0.in_etm_en_chn = enable;
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}
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/**
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* @brief Whether to enable the mean access ecc or aes domain
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*/
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static inline void axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->in[channel].conf.in_conf0.in_ecc_aec_en_chn = enable;
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}
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///////////////////////////////////// TX /////////////////////////////////////////
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/**
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* @brief Get DMA TX channel interrupt status word
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@ -471,6 +479,14 @@ static inline void axi_dma_ll_tx_enable_etm_task(axi_dma_dev_t *dev, uint32_t ch
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dev->out[channel].conf.out_conf0.out_etm_en_chn = enable;
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}
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/**
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* @brief Whether to enable the mean access ecc or aes domain
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*/
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static inline void axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(axi_dma_dev_t *dev, uint32_t channel, bool enable)
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{
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dev->out[channel].conf.out_conf0.out_ecc_aec_en_chn = enable;
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}
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///////////////////////////////////// CRC-TX /////////////////////////////////////////
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/**
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@ -201,6 +201,9 @@ if(SHA_PERIPHERAL_TYPE STREQUAL "dma" OR AES_PERIPHERAL_TYPE STREQUAL "dma")
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target_link_libraries(mbedcrypto PRIVATE idf::esp_mm)
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if(CONFIG_SOC_SHA_GDMA OR CONFIG_SOC_AES_GDMA)
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target_sources(mbedcrypto PRIVATE "${COMPONENT_DIR}/port/crypto_shared_gdma/esp_crypto_shared_gdma.c")
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if(CONFIG_SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT)
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target_link_libraries(mbedcrypto PRIVATE idf::spi_flash idf::bootloader_support)
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endif()
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endif()
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endif()
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@ -16,6 +16,8 @@
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#include "esp_memory_utils.h"
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#include "esp_private/esp_cache_private.h"
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#include "esp_private/periph_ctrl.h"
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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#if CONFIG_PM_ENABLE
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#include "esp_pm.h"
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@ -36,10 +38,19 @@
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#include "aes/esp_aes_gcm.h"
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#endif
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#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
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#include "esp_flash_encrypt.h"
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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/* Max size of each chunk to process when output buffer is in unaligned external ram
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must be a multiple of block size
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*/
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#if (CONFIG_IDF_TARGET_ESP32P4 && CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
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/* As P4 has larger memory than other targets, thus we can support a larger chunk write size */
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#define AES_MAX_CHUNK_WRITE_SIZE 8*1024
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#else
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#define AES_MAX_CHUNK_WRITE_SIZE 1600
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#endif
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/* Input over this length will yield and wait for interrupt instead of
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busy-waiting, 30000 bytes is approx 0.5 ms */
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@ -163,6 +174,26 @@ static int esp_aes_dma_wait_complete(bool use_intr, crypto_dma_desc_t *output_de
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return 0;
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}
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static inline size_t get_cache_line_size(const void *addr)
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{
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esp_err_t ret = ESP_FAIL;
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size_t cache_line_size = 0;
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#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
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if (esp_ptr_external_ram(addr)) {
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ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_line_size);
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} else
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#endif
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{
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ret = esp_cache_get_alignment(MALLOC_CAP_DMA, &cache_line_size);
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}
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if (ret != ESP_OK) {
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return 0;
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}
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return cache_line_size;
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}
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/* Output buffers in external ram needs to be 16-byte aligned and DMA can't access input in the iCache mem range,
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reallocate them into internal memory and encrypt in chunks to avoid
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@ -176,13 +207,29 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
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size_t chunk_len;
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int ret = 0;
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int offset = 0;
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uint32_t heap_caps = 0;
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unsigned char *input_buf = NULL;
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unsigned char *output_buf = NULL;
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const unsigned char *dma_input;
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chunk_len = MIN(AES_MAX_CHUNK_WRITE_SIZE, len);
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size_t input_alignment = 1;
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size_t output_alignment = 1;
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/* When AES-DMA operations are carried out using external memory with external memory encryption enabled,
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we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned. */
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#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
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if (esp_flash_encryption_enabled()) {
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if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
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input_alignment = MAX(get_cache_line_size(input), SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT);
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output_alignment = MAX(get_cache_line_size(output), SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT);
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}
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}
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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if (realloc_input) {
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input_buf = heap_caps_malloc(chunk_len, MALLOC_CAP_DMA);
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heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(input) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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input_buf = heap_caps_aligned_alloc(input_alignment, chunk_len, heap_caps);
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if (input_buf == NULL) {
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mbedtls_platform_zeroize(output, len);
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@ -192,7 +239,8 @@ static int esp_aes_process_dma_ext_ram(esp_aes_context *ctx, const unsigned char
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}
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if (realloc_output) {
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output_buf = heap_caps_malloc(chunk_len, MALLOC_CAP_DMA);
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heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(output) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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output_buf = heap_caps_aligned_alloc(output_alignment, chunk_len, heap_caps);
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if (output_buf == NULL) {
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mbedtls_platform_zeroize(output, len);
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@ -284,27 +332,6 @@ static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_
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return ptr;
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}
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static inline size_t get_cache_line_size(const void *addr)
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{
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esp_err_t ret = ESP_FAIL;
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size_t cache_line_size = 0;
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#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
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if (esp_ptr_external_ram(addr)) {
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ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_line_size);
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} else
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#endif
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{
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ret = esp_cache_get_alignment(MALLOC_CAP_DMA, &cache_line_size);
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}
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if (ret != ESP_OK) {
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return 0;
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}
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return cache_line_size;
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}
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static inline esp_err_t dma_desc_link(crypto_dma_desc_t *dmadesc, size_t crypto_dma_desc_num, size_t cache_line_size)
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{
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esp_err_t ret = ESP_OK;
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@ -404,7 +431,7 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
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dma_descs_needed = (unaligned_start_bytes ? 1 : 0) + dma_desc_get_required_num(aligned_block_bytes, max_desc_size) + (unaligned_end_bytes ? 1 : 0);
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/* Allocate memory for DMA descriptors of total size aligned up to a multiple of cache line size */
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dma_descriptors = (crypto_dma_desc_t *) aes_dma_calloc(dma_descs_needed, sizeof(crypto_dma_desc_t), MALLOC_CAP_DMA, NULL);
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dma_descriptors = (crypto_dma_desc_t *) aes_dma_calloc(dma_descs_needed, sizeof(crypto_dma_desc_t), MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, NULL);
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if (dma_descriptors == NULL) {
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ESP_LOGE(TAG, "Failed to allocate memory for the array of DMA descriptors");
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return ESP_FAIL;
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@ -413,7 +440,7 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
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size_t populated_dma_descs = 0;
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if (unaligned_start_bytes) {
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start_alignment_stream_buffer = aes_dma_calloc(alignment_buffer_size, sizeof(uint8_t), AES_DMA_ALLOC_CAPS, NULL);
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start_alignment_stream_buffer = aes_dma_calloc(alignment_buffer_size, sizeof(uint8_t), AES_DMA_ALLOC_CAPS | (esp_ptr_external_ram(buffer) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_INTERNAL) , NULL);
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if (start_alignment_stream_buffer == NULL) {
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ESP_LOGE(TAG, "Failed to allocate memory for start alignment buffer");
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return ESP_FAIL;
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@ -435,7 +462,7 @@ static esp_err_t generate_descriptor_list(const uint8_t *buffer, const size_t le
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}
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if (unaligned_end_bytes) {
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end_alignment_stream_buffer = aes_dma_calloc(alignment_buffer_size, sizeof(uint8_t), AES_DMA_ALLOC_CAPS, NULL);
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end_alignment_stream_buffer = aes_dma_calloc(alignment_buffer_size, sizeof(uint8_t), AES_DMA_ALLOC_CAPS | (esp_ptr_external_ram(buffer) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_INTERNAL), NULL);
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if (end_alignment_stream_buffer == NULL) {
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ESP_LOGE(TAG, "Failed to allocate memory for end alignment buffer");
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return ESP_FAIL;
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@ -499,6 +526,20 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
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return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH;
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}
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#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
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if (esp_flash_encryption_enabled()) {
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if (esp_ptr_external_ram(input) || esp_ptr_external_ram(output) || esp_ptr_in_drom(input) || esp_ptr_in_drom(output)) {
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if (((intptr_t)(input) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
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input_needs_realloc = true;
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}
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if (((intptr_t)(output) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
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output_needs_realloc = true;
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}
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}
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}
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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/* DMA cannot access memory in the iCache range, copy input to internal ram */
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if (!s_check_dma_capable(input)) {
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input_needs_realloc = true;
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -13,7 +13,13 @@
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#include "esp_cache.h"
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#include "esp_crypto_dma.h"
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#include "esp_crypto_lock.h"
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#include "esp_memory_utils.h"
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
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#include "esp_flash_encrypt.h"
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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#if SOC_AHB_GDMA_VERSION == 1
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#include "hal/gdma_ll.h"
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@ -140,6 +146,22 @@ esp_err_t esp_crypto_shared_gdma_start(const lldesc_t *input, const lldesc_t *ou
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return ESP_OK;
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}
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/* The external memory ecc-aes access must be enabled when there exists
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at least one buffer in the DMA descriptors that resides in external memory. */
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#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
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static bool check_dma_descs_need_ext_mem_ecc_aes_access(const crypto_dma_desc_t *dmadesc)
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{
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crypto_dma_desc_t* desc = (crypto_dma_desc_t*) dmadesc;
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while (desc) {
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if (esp_ptr_in_drom(desc->buffer) || esp_ptr_external_ram(desc->buffer)) {
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return true;
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}
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desc = desc->next;
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}
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return false;
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}
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, const crypto_dma_desc_t *output, gdma_trigger_peripheral_t peripheral)
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{
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int rx_ch_id = 0;
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@ -173,6 +195,23 @@ esp_err_t esp_crypto_shared_gdma_start_axi_ahb(const crypto_dma_desc_t *input, c
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axi_dma_ll_rx_reset_channel(&AXI_DMA, rx_ch_id);
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#endif /* SOC_AHB_GDMA_VERSION */
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/* When GDMA operations are carried out using external memory with external memory encryption enabled,
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we need to enable AXI-DMA's AES-ECC mean access bit. */
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#if (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT)
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if (esp_flash_encryption_enabled()) {
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int tx_ch_id = 0;
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gdma_get_channel_id(tx_channel, &tx_ch_id);
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if (check_dma_descs_need_ext_mem_ecc_aes_access(input) || check_dma_descs_need_ext_mem_ecc_aes_access(output)) {
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axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(&AXI_DMA, rx_ch_id, true);
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axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(&AXI_DMA, tx_ch_id, true);
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} else {
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axi_dma_ll_rx_enable_ext_mem_ecc_aes_access(&AXI_DMA, rx_ch_id, false);
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axi_dma_ll_tx_enable_ext_mem_ecc_aes_access(&AXI_DMA, tx_ch_id, false);
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}
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}
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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gdma_start(tx_channel, (intptr_t)input);
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gdma_start(rx_channel, (intptr_t)output);
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@ -53,6 +53,11 @@
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#include "hal/sha_ll.h"
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#include "soc/soc_caps.h"
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#include "esp_sha_dma_priv.h"
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#include "sdkconfig.h"
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#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
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#include "esp_flash_encrypt.h"
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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#if SOC_SHA_GDMA
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#define SHA_LOCK() esp_crypto_sha_aes_lock_acquire()
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@ -168,6 +173,63 @@ static void esp_sha_block_mode(esp_sha_type sha_type, const uint8_t *input, uint
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static DRAM_ATTR crypto_dma_desc_t s_dma_descr_input;
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static DRAM_ATTR crypto_dma_desc_t s_dma_descr_buf;
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static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block);
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#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
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static esp_err_t esp_sha_dma_process_ext(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block,
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bool realloc_input, bool realloc_buf)
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{
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int ret = ESP_FAIL;
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void *input_copy = NULL;
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void *buf_copy = NULL;
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const void *dma_input = NULL;
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const void *dma_buf = NULL;
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uint32_t heap_caps = 0;
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if (realloc_input) {
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heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(input) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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input_copy = heap_caps_aligned_alloc(SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT, ilen, heap_caps);
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if (input_copy == NULL) {
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ESP_LOGE(TAG, "Failed to allocate aligned SPIRAM memory");
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return ret;
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}
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memcpy(input_copy, input, ilen);
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dma_input = input_copy;
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} else {
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dma_input = input;
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}
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if (realloc_buf) {
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heap_caps = MALLOC_CAP_8BIT | (esp_ptr_external_ram(buf) ? MALLOC_CAP_SPIRAM : MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL);
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buf_copy = heap_caps_aligned_alloc(SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT, buf_len, heap_caps);
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if (buf_copy == NULL) {
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ESP_LOGE(TAG, "Failed to allocate aligned internal memory");
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return ret;
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}
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memcpy(buf_copy, buf, buf_len);
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dma_buf = buf_copy;
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} else {
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dma_buf = buf;
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}
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ret = esp_sha_dma_process(sha_type, dma_input, ilen, dma_buf, buf_len, is_first_block);
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if (realloc_input) {
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free(input_copy);
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}
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if (realloc_buf) {
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free(buf_copy);
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}
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return ret;
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}
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#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
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/* Performs SHA on multiple blocks at a time */
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static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, uint32_t ilen,
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const void *buf, uint32_t buf_len, bool is_first_block)
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@ -179,6 +241,29 @@ static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, u
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memset(&s_dma_descr_input, 0, sizeof(crypto_dma_desc_t));
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memset(&s_dma_descr_buf, 0, sizeof(crypto_dma_desc_t));
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/* When SHA-DMA operations are carried out using external memory with external memory encryption enabled,
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we need to make sure that the addresses and the sizes of the buffers on which the DMA operates are 16 byte-aligned. */
|
||||
#ifdef SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
|
||||
if (esp_flash_encryption_enabled()) {
|
||||
if (esp_ptr_external_ram(input) || esp_ptr_external_ram(buf) || esp_ptr_in_drom(input) || esp_ptr_in_drom(buf)) {
|
||||
bool input_needs_realloc = false;
|
||||
bool buf_needs_realloc = false;
|
||||
|
||||
if (ilen && ((intptr_t)(input) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
input_needs_realloc = true;
|
||||
}
|
||||
|
||||
if (buf_len && ((intptr_t)(buf) & (SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT - 1)) != 0) {
|
||||
buf_needs_realloc = true;
|
||||
}
|
||||
|
||||
if (input_needs_realloc || buf_needs_realloc) {
|
||||
return esp_sha_dma_process_ext(sha_type, input, ilen, buf, buf_len, is_first_block, input_needs_realloc, buf_needs_realloc);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT */
|
||||
|
||||
/* DMA descriptor for Memory to DMA-SHA transfer */
|
||||
if (ilen) {
|
||||
s_dma_descr_input.dw0.length = ilen;
|
||||
|
|
@ -188,7 +273,7 @@ static esp_err_t esp_sha_dma_process(esp_sha_type sha_type, const void *input, u
|
|||
s_dma_descr_input.buffer = (void *) input;
|
||||
dma_descr_head = &s_dma_descr_input;
|
||||
}
|
||||
/* Check after input to overide head if there is any buf*/
|
||||
/* Check after input to override head if there is any buf*/
|
||||
if (buf_len) {
|
||||
s_dma_descr_buf.dw0.length = buf_len;
|
||||
s_dma_descr_buf.dw0.size = buf_len;
|
||||
|
|
|
|||
|
|
@ -491,6 +491,10 @@ config SOC_GDMA_SUPPORT_ETM
|
|||
bool
|
||||
default y
|
||||
|
||||
config SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_DMA2D_GROUPS
|
||||
int
|
||||
default 1
|
||||
|
|
|
|||
|
|
@ -193,6 +193,7 @@
|
|||
#define SOC_AXI_GDMA_SUPPORT_PSRAM 1
|
||||
#define SOC_GDMA_SUPPORT_ETM 1
|
||||
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
|
||||
#define SOC_AXI_DMA_EXT_MEM_ENC_ALIGNMENT (16)
|
||||
|
||||
/*-------------------------- 2D-DMA CAPS -------------------------------------*/
|
||||
#define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups
|
||||
|
|
|
|||
Ładowanie…
Reference in New Issue