From 5d184dcfe067b8e1ed5d04ea6fdbfff89bfd473d Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Mon, 5 Jul 2021 16:55:43 +0800 Subject: [PATCH] soc: update S3 memory layout --- components/esp32c3/ld/esp32c3.ld | 4 +- components/esp32s3/ld/esp32s3.ld | 4 +- components/soc/esp32s3/include/soc/soc.h | 70 ++++++++++++++++-------- 3 files changed, 50 insertions(+), 28 deletions(-) diff --git a/components/esp32c3/ld/esp32c3.ld b/components/esp32c3/ld/esp32c3.ld index 63a26c4276..bc7e6a8ae1 100644 --- a/components/esp32c3/ld/esp32c3.ld +++ b/components/esp32c3/ld/esp32c3.ld @@ -46,7 +46,7 @@ MEMORY #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* Flash mapped instruction data */ - iram0_2_seg (RX) : org = 0x42000020, len = 0x8000000-0x20 + iram0_2_seg (RX) : org = 0x42000020, len = 0x800000-0x20 /** * (0x20 offset above is a convenience for the app binary image generation. @@ -65,7 +65,7 @@ MEMORY #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* Flash mapped constant data */ - drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20 + drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20 /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS diff --git a/components/esp32s3/ld/esp32s3.ld b/components/esp32s3/ld/esp32s3.ld index e6c3c7bce2..bd54875e82 100644 --- a/components/esp32s3/ld/esp32s3.ld +++ b/components/esp32s3/ld/esp32s3.ld @@ -46,7 +46,7 @@ MEMORY #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* Flash mapped instruction data */ - iram0_2_seg (RX) : org = 0x42000020, len = 0x8000000-0x20 + iram0_2_seg (RX) : org = 0x42000020, len = 0x2000000-0x20 /** * (0x20 offset above is a convenience for the app binary image generation. @@ -65,7 +65,7 @@ MEMORY #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS /* Flash mapped constant data */ - drom0_0_seg (R) : org = 0x3C000020, len = 0x8000000-0x20 + drom0_0_seg (R) : org = 0x3C000020, len = 0x2000000-0x20 /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 20832a12e0..c5db076731 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -26,53 +26,45 @@ #define PRO_CPUID (0xcdcd) #define APP_CPUID (0xabab) -#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space - -#define DR_REG_SYSTEM_BASE 0x600c0000 -#define DR_REG_SENSITIVE_BASE 0x600c1000 -#define DR_REG_INTERRUPT_BASE 0x600c2000 -#define DR_REG_EXTMEM_BASE 0x600c4000 -#define DR_REG_MMU_TABLE 0x600c5000 -#define DR_REG_ITAG_TABLE 0x600c6000 -#define DR_REG_DTAG_TABLE 0x600c8000 -#define DR_REG_AES_BASE 0x6003a000 -#define DR_REG_SHA_BASE 0x6003b000 -#define DR_REG_RSA_BASE 0x6003c000 -#define DR_REG_HMAC_BASE 0x6003e000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define DR_REG_GDMA_BASE 0x6003f000 -#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 -#define DR_REG_WORLD_CNTL_BASE 0x600d0000 -#define DR_REG_DPORT_END 0x600d3FFC #define DR_REG_UART_BASE 0x60000000 #define DR_REG_SPI1_BASE 0x60002000 #define DR_REG_SPI0_BASE 0x60003000 #define DR_REG_GPIO_BASE 0x60004000 #define DR_REG_GPIO_SD_BASE 0x60004f00 + #define DR_REG_FE2_BASE 0x60005000 #define DR_REG_FE_BASE 0x60006000 -#define DR_REG_FRC_TIMER_BASE 0x60007000 + +#define DR_REG_EFUSE_BASE 0x60007000 #define DR_REG_RTCCNTL_BASE 0x60008000 #define DR_REG_RTCIO_BASE 0x60008400 #define DR_REG_SENS_BASE 0x60008800 #define DR_REG_RTC_I2C_BASE 0x60008C00 #define DR_REG_IO_MUX_BASE 0x60009000 + #define DR_REG_HINF_BASE 0x6000B000 #define DR_REG_UHCI1_BASE 0x6000C000 + #define DR_REG_I2S_BASE 0x6000F000 #define DR_REG_UART1_BASE 0x60010000 + #define DR_REG_BT_BASE 0x60011000 + #define DR_REG_I2C_EXT_BASE 0x60013000 #define DR_REG_UHCI0_BASE 0x60014000 + #define DR_REG_SLCHOST_BASE 0x60015000 + #define DR_REG_RMT_BASE 0x60016000 #define DR_REG_PCNT_BASE 0x60017000 + #define DR_REG_SLC_BASE 0x60018000 + #define DR_REG_LEDC_BASE 0x60019000 -#define DR_REG_EFUSE_BASE 0x60007000 + #define DR_REG_NRX_BASE 0x6001CC00 #define DR_REG_BB_BASE 0x6001D000 + #define DR_REG_PWM0_BASE 0x6001E000 #define DR_REG_TIMERGROUP0_BASE 0x6001F000 #define DR_REG_TIMERGROUP1_BASE 0x60020000 @@ -81,20 +73,45 @@ #define DR_REG_SPI2_BASE 0x60024000 #define DR_REG_SPI3_BASE 0x60025000 #define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ #define DR_REG_I2C1_EXT_BASE 0x60027000 #define DR_REG_SDMMC_BASE 0x60028000 + #define DR_REG_PERI_BACKUP_BASE 0x6002A000 + #define DR_REG_TWAI_BASE 0x6002B000 #define DR_REG_PWM1_BASE 0x6002C000 #define DR_REG_I2S1_BASE 0x6002D000 #define DR_REG_UART2_BASE 0x6002E000 -#define DR_REG_SPI4_BASE 0x60037000 + #define DR_REG_USB_DEVICE_BASE 0x60038000 #define DR_REG_USB_WRAP_BASE 0x60039000 +#define DR_REG_AES_BASE 0x6003A000 +#define DR_REG_SHA_BASE 0x6003B000 +#define DR_REG_RSA_BASE 0x6003C000 +#define DR_REG_HMAC_BASE 0x6003E000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 +#define DR_REG_GDMA_BASE 0x6003F000 #define DR_REG_APB_SARADC_BASE 0x60040000 #define DR_REG_LCD_CAM_BASE 0x60041000 +#define DR_REG_SYSTEM_BASE 0x600C0000 +#define DR_REG_SENSITIVE_BASE 0x600C1000 +#define DR_REG_INTERRUPT_BASE 0x600C2000 + +/* Cache configuration */ +#define DR_REG_EXTMEM_BASE 0x600C4000 +#define DR_REG_MMU_TABLE 0x600C5000 +#define DR_REG_ITAG_TABLE 0x600C6000 +#define DR_REG_DTAG_TABLE 0x600C8000 + +#define DR_REG_EXT_MEM_ENC 0x600CC000 + +#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 +#define DR_REG_WORLD_CNTL_BASE 0x600D0000 +#define DR_REG_DPORT_END 0x600D3FFC + + #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) @@ -233,23 +250,28 @@ #define SOC_DROM_LOW 0x3C000000 #define SOC_DROM_HIGH 0x3D000000 #define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH 0x42800000 +#define SOC_IROM_HIGH 0x44000000 #define SOC_IRAM_LOW 0x40370000 #define SOC_IRAM_HIGH 0x403E0000 #define SOC_DRAM_LOW 0x3FC88000 #define SOC_DRAM_HIGH 0x3FD00000 + #define SOC_RTC_IRAM_LOW 0x600FE000 #define SOC_RTC_IRAM_HIGH 0x60100000 #define SOC_RTC_DRAM_LOW 0x600FE000 #define SOC_RTC_DRAM_HIGH 0x60100000 + #define SOC_RTC_DATA_LOW 0x50000000 #define SOC_RTC_DATA_HIGH 0x50002000 + #define SOC_EXTRAM_DATA_LOW 0x3D000000 #define SOC_EXTRAM_DATA_HIGH 0x3E000000 #define SOC_IROM_MASK_LOW 0x40000000 #define SOC_IROM_MASK_HIGH 0x4001A100 #define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. #define SOC_DIRAM_IRAM_LOW 0x40378000