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Merge branch 'bugfix/random_en_dis_for_app' into 'master' 

bootloader_support: Fix using shared CLK_EN and RST_EN regs for random

See merge request espressif/esp-idf!6198
pull/4251/head
Angus Gratton 2019-10-23 13:18:01 +08:00
rodzic b216e3b5c8 0c44f8ccbd
commit 5bec9fb010
3 zmienionych plików z 21 dodań i 7 usunięć
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18
components/bootloader_support/src/bootloader_random.c
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@ -23,6 +23,7 @@
#ifndef BOOTLOADER_BUILD
#include "esp_system.h"
#include "driver/periph_ctrl.h"
void bootloader_fill_random(void *buffer, size_t length)
{
@ -65,7 +66,11 @@ void bootloader_random_enable(void)
/* Ensure the hardware RNG is enabled following a soft reset. This should always be the case already (this clock is
never disabled while the CPU is running), this is a "belts and braces" type check.
*/
#ifdef BOOTLOADER_BUILD
DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_RNG_EN);
#else
periph_module_enable(PERIPH_RNG_MODULE);
#endif // BOOTLOADER_BUILD
/* Enable SAR ADC in test mode to feed ADC readings of the 1.1V
reference via I2S into the RNG entropy input.
@ -77,7 +82,11 @@ void bootloader_random_enable(void)
SET_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);
SET_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_SAR2_EN_TEST);
#ifdef BOOTLOADER_BUILD
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
#else
periph_module_enable(PERIPH_I2S0_MODULE);
#endif // BOOTLOADER_BUILD
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_FORCE_START_TOP);
CLEAR_PERI_REG_MASK(SENS_SAR_START_FORCE_REG, SENS_ULP_CP_START_TOP);
// Test pattern configuration byte 0xAD:
@ -115,8 +124,11 @@ void bootloader_random_enable(void)
void bootloader_random_disable(void)
{
/* Disable i2s clock */
#ifdef BOOTLOADER_BUILD
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
#else
periph_module_disable(PERIPH_I2S0_MODULE);
#endif // BOOTLOADER_BUILD
/* Reset some i2s configuration (possibly redundant as we reset entire
I2S peripheral further down). */
@ -138,8 +150,12 @@ void bootloader_random_disable(void)
SET_PERI_REG_BITS(SYSCON_SARADC_FSM_REG, SYSCON_SARADC_START_WAIT, 8, SYSCON_SARADC_START_WAIT_S);
/* Reset i2s peripheral */
#ifdef BOOTLOADER_BUILD
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
#else
periph_module_reset(PERIPH_I2S0_MODULE);
#endif
/* Disable pull supply voltage to SAR ADC */
CLEAR_PERI_REG_MASK(RTC_CNTL_TEST_MUX_REG, RTC_CNTL_ENT_RTC);

5
components/esp32/test/test_ahb_arb.c
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@ -5,7 +5,7 @@
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/lldesc.h"
#include "esp32/rom/gpio.h"
#include "driver/periph_ctrl.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -33,8 +33,7 @@ the point where they happened to do what I want.
static void lcdIfaceInit(void)
{
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
periph_module_enable(PERIPH_I2S0_MODULE);
//Init pins to i2s functions
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable

5
components/esp32/test/test_unal_dma.c
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@ -6,7 +6,7 @@
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/lldesc.h"
#include "esp32/rom/gpio.h"
#include "driver/periph_ctrl.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -29,8 +29,7 @@ static volatile lldesc_t dmaDesc[2];
static void dmaMemcpy(void *in, void *out, int len)
{
volatile int i;
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_I2S0_CLK_EN);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_I2S0_RST);
periph_module_enable(PERIPH_I2S0_MODULE);
//Init pins to i2s functions
SET_PERI_REG_MASK(GPIO_ENABLE_W1TS_REG, (1 << 11) | (1 << 3) | (1 << 0) | (1 << 2) | (1 << 5) | (1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); //ENABLE GPIO oe_enable