kopia lustrzana https://github.com/espressif/esp-idf
uart: fix uart_tx_wait_idle to wait for fifo empty
In some cases, when data was just written into UART FIFO, transmitter state could be still zero while the FIFO did contain some data. This resulted in uart_tx_wait_idle occasionally returning before all the data was sent out. Fix by checking both UART transmitter state and TX FIFO count.pull/2683/head
rodzic
88625a2501
commit
508fb79a26
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@ -267,9 +267,11 @@ void uart_tx_flush(uint8_t uart_no);
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* here for compatibility.
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*/
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static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) {
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while(REG_GET_FIELD(UART_STATUS_REG(uart_no), UART_ST_UTX_OUT)) {
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;
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}
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uint32_t status;
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do {
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status = READ_PERI_REG(UART_STATUS_REG(uart_no));
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/* either tx count or state is non-zero */
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} while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0);
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}
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/**
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@ -159,7 +159,9 @@ static void IRAM_ATTR suspend_uarts()
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{
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for (int i = 0; i < 3; ++i) {
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REG_SET_BIT(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF);
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uart_tx_wait_idle(i);
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while (REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT) != 0) {
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;
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}
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}
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}
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