kopia lustrzana https://github.com/espressif/esp-idf
soc/esp32s3: merge gpio caps into soc_caps.h
rodzic
4995e24199
commit
4efab0d0ff
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@ -18,6 +18,8 @@
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#include "hal/rtc_io_types.h"
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#include "hal/gpio_types.h"
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#define RTCIO_LL_PIN_FUNC 0
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#ifdef __cplusplus
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extern "C" {
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#endif
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@ -1,40 +0,0 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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// ESP32-S3 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1)
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#define SOC_GPIO_PIN_COUNT (49)
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// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
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// Force hold is a new function of ESP32-S3
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#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
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// 0~48 except from 22~25 are valid
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#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
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// No GPIO is input only
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
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// Support to configure slept status
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#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
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#ifdef __cplusplus
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}
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#endif
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@ -1,21 +0,0 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#define SOC_RTCIO_PIN_COUNT 22
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#define RTCIO_LL_PIN_FUNC 0
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#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
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#define SOC_RTCIO_HOLD_SUPPORTED 1
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#define SOC_RTCIO_WAKE_SUPPORTED 1
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@ -95,7 +95,22 @@
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#define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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#include "gpio_caps.h"
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// ESP32-S3 has 1 GPIO peripheral
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#define SOC_GPIO_PORT (1U)
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#define SOC_GPIO_PIN_COUNT (49)
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// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
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// Force hold is a new function of ESP32-S3
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#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
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// 0~48 except from 22~25 are valid
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#define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
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// No GPIO is input only
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#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK)
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// Support to configure slept status
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#define SOC_GPIO_SUPPORT_SLP_SWITCH (1)
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/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
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#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
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@ -175,7 +190,10 @@
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#define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3)
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/*-------------------------- RTCIO CAPS --------------------------------------*/
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#include "rtc_io_caps.h"
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#define SOC_RTCIO_PIN_COUNT 22
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#define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1
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#define SOC_RTCIO_HOLD_SUPPORTED 1
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#define SOC_RTCIO_WAKE_SUPPORTED 1
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/*-------------------------- SIGMA DELTA CAPS --------------------------------*/
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#define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral
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