kopia lustrzana https://github.com/espressif/esp-idf
ulp-riscv: always force COCPU clock on S3
The coprocessor cpu trap signal doesnt have a stable reset value, force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPUpull/10244/head
rodzic
755ce1077d
commit
4acfe1a91a
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@ -56,12 +56,15 @@ esp_err_t ulp_riscv_run(void)
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return ESP_OK;
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#elif CONFIG_IDF_TARGET_ESP32S3
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/* Reset COCPU when power on. */
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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esp_rom_delay_us(20);
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
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/* The coprocessor cpu trap signal doesnt have a stable reset value,
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force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
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SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
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/* Disable ULP timer */
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CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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/* wait for at least 1 RTC_SLOW_CLK cycle */
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