kopia lustrzana https://github.com/espressif/esp-idf
driver(uart): fix uart module reset issue
On ESP32, due to fifo reset issue, UART2 will work incorrectly if reset the fifo of UART1(TX fifo and RX fifo). The software can workaround the RX fifo reset issue, while the TX fifo reset issue can not. When UART2 is used and UART1 is used as the log output port, a software reset can reproduce this issue. So we should reset the UART memory before the software reset to solve this problem.pull/5452/head
rodzic
b52ed2d2a5
commit
46713a5275
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@ -632,8 +632,6 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
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uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), UART_TX_IDLE_NUM_DEFAULT);
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uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh);
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UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock));
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// The module reset do not reset TX and RX memory.
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// reset FIFO to avoid garbage data remained in the FIFO.
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uart_hal_rxfifo_rst(&(uart_context[uart_num].hal));
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uart_hal_txfifo_rst(&(uart_context[uart_num].hal));
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return ESP_OK;
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@ -111,7 +111,8 @@ void IRAM_ATTR esp_restart_noos(void)
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// Reset timer/spi/uart
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST);
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//UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
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DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
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DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
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// Set CPU back to XTAL source, no PLL, same as hard reset
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@ -150,6 +150,7 @@ void uart_hal_write_txfifo(uart_hal_context_t *hal, const uint8_t *buf, uint32_t
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/**
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* @brief Reset the UART txfifo
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* @note On ESP32, this function is reserved for UART1 and UART2.
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*
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* @param hal Context of the HAL layer
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*
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@ -219,14 +219,20 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
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/**
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* @brief Reset the UART hw txfifo.
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*
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* Note: Due to hardware issue, reset UART1's txfifo will also reset UART2's txfifo.
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* So reserve this function for UART1 and UART2. Please do DPORT reset for UART and its memory at chip startup
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* to ensure the TX FIFO is reset correctly at the beginning.
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*
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* @param hw Beginning address of the peripheral registers.
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*
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* @return None
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*/
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static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
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{
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hw->conf0.txfifo_rst = 1;
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hw->conf0.txfifo_rst = 0;
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if (hw == &UART0) {
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hw->conf0.txfifo_rst = 1;
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hw->conf0.txfifo_rst = 0;
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}
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}
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/**
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