Merge branch 'feature/iram_data_bss' into 'master'

esp32: IRAM_DATA_ATTR and IRAM_BSS_ATTR introduced

See merge request espressif/esp-idf!8377

components/esp32/cpu_start.c

@@ -98,6 +98,10 @@ extern int _bss_start;
 extern int _bss_end;
 extern int _rtc_bss_start;
 extern int _rtc_bss_end;
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+extern int _iram_bss_start;
+extern int _iram_bss_end;
+#endif
 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
 extern int _ext_ram_bss_start;
 extern int _ext_ram_bss_end;
@@ -157,6 +161,11 @@ void IRAM_ATTR call_start_cpu0(void)
     //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
     memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
 
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    // Clear IRAM BSS
+    memset(&_iram_bss_start, 0, (&_iram_bss_end - &_iram_bss_start) * sizeof(_iram_bss_start));
+#endif
+
     /* Unless waking from deep sleep (implying RTC memory is intact), clear RTC bss */
     if (rst_reas[0] != DEEPSLEEP_RESET) {
         memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));

components/esp32/ld/esp32.project.ld.in

@@ -160,7 +160,6 @@ SECTIONS
 
     mapping[iram0_text]
 
-    _iram_text_end = ABSOLUTE(.);
   } > iram0_0_seg
 
   .dram0.data :
@@ -338,9 +337,31 @@ SECTIONS
   .iram0.text_end (NOLOAD) :
   {
     . = ALIGN (4);
-    _iram_end = ABSOLUTE(.);
+    _iram_text_end = ABSOLUTE(.);
   } > iram0_0_seg
 
+  .iram0.data :
+  {
+    . = ALIGN(4);
+    _iram_data_start = ABSOLUTE(.);
+
+    mapping[iram0_data]
+
+    _iram_data_end = ABSOLUTE(.);
+  } > iram0_0_seg
+
+  .iram0.bss (NOLOAD) :
+  {
+    . = ALIGN(4);
+    _iram_bss_start = ABSOLUTE(.);
+
+    mapping[iram0_bss]
+
+    _iram_bss_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _iram_end = ABSOLUTE(.);
+   } > iram0_0_seg
+
   /* Marks the end of data, bss and possibly rodata  */
   .dram0.heap_start (NOLOAD) :
   {
@@ -349,7 +370,7 @@ SECTIONS
   } > dram0_0_seg
 }
 
-ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
+ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
           "IRAM0 segment data does not fit.")
 
 ASSERT(((_heap_start - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)),

components/esp32/ld/esp32_fragments.lf

@@ -40,6 +40,14 @@ entries:
 entries:
     .iram1+
 
+[sections:iram_data]
+entries:
+    .iram.data+
+
+[sections:iram_bss]
+entries:
+    .iram.bss+
+
 [sections:dram]
 entries:
     .dram1+
@@ -64,6 +72,8 @@ entries:
     bss -> dram0_bss
     common -> dram0_bss
     iram -> iram0_text
+    iram_data -> iram0_data
+    iram_bss -> iram0_bss
     dram -> dram0_data
     rtc_text -> rtc_text
     rtc_data -> rtc_data

components/xtensa/include/esp_attr.h

@@ -28,6 +28,18 @@
 // Forces data into DRAM instead of flash
 #define DRAM_ATTR _SECTION_ATTR_IMPL(".dram1", __COUNTER__)
 
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+// Forces data into IRAM instead of DRAM
+#define IRAM_DATA_ATTR __attribute__((section(".iram.data")))
+
+// Forces bss into IRAM instead of DRAM
+#define IRAM_BSS_ATTR __attribute__((section(".iram.bss")))
+#else
+#define IRAM_DATA_ATTR
+
+#define IRAM_BSS_ATTR
+#endif
+
 // Forces data to be 4 bytes aligned
 #define WORD_ALIGNED_ATTR __attribute__((aligned(4)))