kopia lustrzana https://github.com/espressif/esp-idf
modem_clock: implemented the modem clock hal/ll-layer (include modem syscon and lpcon) for esp32h2
wuzhenghui
rodzic
a76dee171e
commit
43a9456243
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -58,6 +58,16 @@ void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal,
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}
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}
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void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable)
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{
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if (enable) {
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modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
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modem_syscon_ll_enable_fe_cal_160m_clock(hal->syscon_dev, enable);
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modem_syscon_ll_enable_fe_160m_clock(hal->syscon_dev, enable);
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modem_syscon_ll_enable_fe_80m_clock(hal->syscon_dev, enable);
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}
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}
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void modem_clock_hal_deselect_all_lp_timer_lpclk_source(modem_clock_hal_context_t *hal)
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{
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modem_lpcon_ll_enable_lp_timer_slow_osc(hal->lpcon_dev, false);
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@ -0,0 +1,63 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-H2 LP CLKRST register operations
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#pragma once
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "soc/lp_clkrst_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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__attribute__((always_inline))
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static inline void lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(lp_clkrst_dev_t *hw, bool en)
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{
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hw->lpperi.lp_sel_osc_slow = en;
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}
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__attribute__((always_inline))
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static inline void lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(lp_clkrst_dev_t *hw, bool en)
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{
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hw->lpperi.lp_sel_osc_fast = en;
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}
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__attribute__((always_inline))
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static inline void lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(lp_clkrst_dev_t *hw, bool en)
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{
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hw->lpperi.lp_sel_xtal = en;
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}
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__attribute__((always_inline))
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static inline void lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(lp_clkrst_dev_t *hw, bool en)
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{
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hw->lpperi.lp_sel_xtal32k = en;
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}
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__attribute__((always_inline))
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static inline void lp_clkrst_ll_set_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw, uint32_t value)
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{
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hw->lpperi.lp_bletimer_div_num = value;
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}
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__attribute__((always_inline))
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static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw)
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{
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return hw->lpperi.lp_bletimer_div_num;
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}
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__attribute__((always_inline))
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static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
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{
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hw->lpperi.lp_bletimer_32k_sel = src;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,42 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for MODEM CLOCK
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "hal/modem_syscon_ll.h"
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#include "hal/modem_lpcon_ll.h"
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#include "hal/modem_clock_types.h"
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typedef struct {
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modem_syscon_dev_t *syscon_dev;
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modem_lpcon_dev_t *lpcon_dev;
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} modem_clock_hal_context_t;
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void modem_clock_hal_set_clock_domain_icg_bitmap(modem_clock_hal_context_t *hal, modem_clock_domain_t domain, uint32_t bitmap);
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void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable);
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void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider);
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void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable);
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void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src);
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void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal);
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void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src);
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void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal);
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,114 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-H2 MODEM LPCON register operations
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#pragma once
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "hal/assert.h"
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#include "modem/modem_lpcon_struct.h"
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#include "hal/modem_clock_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en)
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{
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hw->test_conf.clk_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en)
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{
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hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en)
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{
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hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en)
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{
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hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en)
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{
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hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
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{
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hw->coex_lp_clk_conf.clk_coex_lp_div_num = value;
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}
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__attribute__((always_inline))
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static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw)
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{
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return hw->coex_lp_clk_conf.clk_coex_lp_div_num;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_coex_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_i2c_master_clock(modem_lpcon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_i2c_mst_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_fe_mem_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en)
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{
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hw->clk_conf_force_on.clk_coex_fo = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_i2c_master_force_clock(modem_lpcon_dev_t *hw, bool en)
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{
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hw->clk_conf_force_on.clk_i2c_mst_fo = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_enable_fe_mem_force_clock(modem_lpcon_dev_t *hw, bool en)
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{
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hw->clk_conf_force_on.clk_fe_mem_fo = en;
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}
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__attribute__((always_inline))
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static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
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{
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hw->rst_conf.val = 0xf;
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hw->rst_conf.val = 0;
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}
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__attribute__((always_inline))
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static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
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{
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return hw->date.val;
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,276 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for ESP32-H2 MODEM SYSCON register operations
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#pragma once
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "hal/assert.h"
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#include "modem/modem_syscon_struct.h"
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#include "hal/modem_clock_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en)
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{
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hw->test_conf.clk_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en)
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{
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// ESP32H2 Not Support
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_etm_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_zb_apb_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_zb_mac_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_modem_sec_en = en;
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hw->clk_conf.clk_modem_sec_ecb_en = en;
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hw->clk_conf.clk_modem_sec_ccm_en = en;
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hw->clk_conf.clk_modem_sec_bah_en = en;
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hw->clk_conf.clk_modem_sec_apb_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_ble_timer_apb(modem_syscon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_ble_timer_apb_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_ble_timer_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en)
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{
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hw->clk_conf.clk_data_dump_en = en;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw)
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{
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hw->clk_conf_force_on.clk_etm_fo = 1;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw)
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{
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hw->clk_conf_force_on.clk_modem_sec_fo = 1;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw)
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{
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hw->clk_conf_force_on.clk_ble_timer_fo = 1;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw)
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{
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hw->clk_conf_force_on.clk_data_dump_fo = 1;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_fe = 1;
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hw->modem_rst_conf.rst_fe = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_btmac_apb = 1;
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hw->modem_rst_conf.rst_btmac_apb = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_btmac = 1;
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hw->modem_rst_conf.rst_btmac = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_btbb_apb = 1;
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hw->modem_rst_conf.rst_btbb_apb = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_btbb = 1;
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hw->modem_rst_conf.rst_btbb = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_etm = 1;
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hw->modem_rst_conf.rst_etm = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_zbmac = 1;
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hw->modem_rst_conf.rst_zbmac = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_modem_ecb(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_modem_ecb = 1;
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hw->modem_rst_conf.rst_modem_ecb = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_modem_ccm(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_modem_ccm = 1;
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hw->modem_rst_conf.rst_modem_ccm = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_modem_bah(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_modem_bah = 1;
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hw->modem_rst_conf.rst_modem_bah = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw)
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{
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hw->modem_rst_conf.rst_modem_sec = 1;
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hw->modem_rst_conf.rst_modem_sec = 0;
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}
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__attribute__((always_inline))
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static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw)
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{
|
||||
hw->modem_rst_conf.rst_ble_timer = 1;
|
||||
hw->modem_rst_conf.rst_ble_timer = 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw)
|
||||
{
|
||||
hw->modem_rst_conf.rst_data_dump = 1;
|
||||
hw->modem_rst_conf.rst_data_dump = 0;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
|
||||
{
|
||||
hw->modem_rst_conf.val = 0xffffffff;
|
||||
hw->modem_rst_conf.val = 0;
|
||||
}
|
||||
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
|
||||
{
|
||||
if(en){
|
||||
hw->clk_conf1.val = hw->clk_conf1.val | mask;
|
||||
} else {
|
||||
hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1.clk_fe_16m_en = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_fe_32m_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1.clk_fe_32m_en = en;
|
||||
}
|
||||
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1.clk_fe_sdm_en = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1.clk_fe_adc_en = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1.clk_fe_apb_en = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1.clk_bt_apb_en = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1.clk_bt_en = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_fe_force_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1_force_on.clk_fe_fo = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en)
|
||||
{
|
||||
hw->clk_conf1_force_on.clk_bt_fo = en;
|
||||
}
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw)
|
||||
{
|
||||
return hw->date.val;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,120 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for MODEM CLOCK (ESP32-C6 specific part)
|
||||
#include <stdbool.h>
|
||||
#include "esp_attr.h"
|
||||
#include "soc/soc.h"
|
||||
#include "hal/modem_clock_hal.h"
|
||||
#include "hal/lp_clkrst_ll.h"
|
||||
#include "hal/modem_clock_types.h"
|
||||
#include "hal/assert.h"
|
||||
|
||||
typedef enum {
|
||||
MODEM_CLOCK_XTAL32K_CODE = 0,
|
||||
MODEM_CLOCK_RC32K_CODE = 1,
|
||||
MODEM_CLOCK_EXT32K_CODE = 2
|
||||
} modem_clock_32k_clk_src_code_t;
|
||||
|
||||
void modem_clock_hal_enable_fe_clock(modem_clock_hal_context_t *hal, bool enable)
|
||||
{
|
||||
modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable);
|
||||
modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable);
|
||||
modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
|
||||
modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
|
||||
modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable);
|
||||
modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable);
|
||||
}
|
||||
|
||||
void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider)
|
||||
{
|
||||
lp_clkrst_ll_set_ble_rtc_timer_divisor_value(&LP_CLKRST, divider);
|
||||
}
|
||||
|
||||
void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable)
|
||||
{
|
||||
// No clock gate on ESP32-H2
|
||||
}
|
||||
|
||||
void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal)
|
||||
{
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, false);
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, false);
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, false);
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, false);
|
||||
}
|
||||
|
||||
void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
|
||||
{
|
||||
HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
|
||||
|
||||
switch (src)
|
||||
{
|
||||
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, true);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, true);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_RC32K:
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
|
||||
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
|
||||
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
|
||||
lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
|
||||
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal)
|
||||
{
|
||||
modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false);
|
||||
modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false);
|
||||
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false);
|
||||
modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false);
|
||||
}
|
||||
|
||||
void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
|
||||
{
|
||||
HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
|
||||
|
||||
switch (src)
|
||||
{
|
||||
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
|
||||
modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
|
||||
modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
|
||||
modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_RC32K:
|
||||
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
|
||||
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
|
||||
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
|
||||
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
|
||||
break;
|
||||
case MODEM_CLOCK_LPCLK_SRC_EXT32K:
|
||||
modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
|
||||
lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
Ładowanie…
Reference in New Issue