kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/i2s_dac_incorrect_clock' into 'master'
i2s: fix adc/dac clock calculation Closes IDFGH-6715 See merge request espressif/esp-idf!17233pull/7148/merge
commit
433d6ee1fd
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@ -983,9 +983,9 @@ static esp_err_t i2s_calculate_adc_dac_clock(int i2s_num, i2s_hal_clock_cfg_t *c
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ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->hal_cfg.mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN), ESP_ERR_INVALID_ARG, TAG, "current mode is not built-in ADC/DAC");
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/* Set I2S bit clock */
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clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_AD_BCK_FACTOR * 2;
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clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_AD_BCK_FACTOR;
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/* Set I2S bit clock default division */
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clk_cfg->bclk_div = I2S_LL_AD_BCK_FACTOR;
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clk_cfg->bclk_div = p_i2s[i2s_num]->hal_cfg.chan_bits;
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/* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */
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clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
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p_i2s[i2s_num]->fixed_mclk : clk_cfg->bclk * clk_cfg->bclk_div;
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