Merge branch 'bugfix/rtc_reg_fields' into 'master'

soc: allow REG_SET_FIELD to be used for bit fields

- Fixes an issue with `rtc_clk_apll_enable`: https://esp32.com/viewtopic.php?f=13&t=1673
- Fixes `rtc_clk_fast_freq_set` function always selecting XTAL/4 as fast clock source.
- Fixes regression in deep sleep current (7uA instead of 5uA).

See merge request !674

components/soc/esp32/include/soc/bb_reg.h

@@ -21,12 +21,20 @@
 
 #define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
 #define BB_FFT_FORCE_PU (BIT(3))
+#define BB_FFT_FORCE_PU_M (BIT(3))
+#define BB_FFT_FORCE_PU_V 1
 #define BB_FFT_FORCE_PU_S 3
 #define BB_FFT_FORCE_PD (BIT(2))
+#define BB_FFT_FORCE_PD_M (BIT(2))
+#define BB_FFT_FORCE_PD_V 1
 #define BB_FFT_FORCE_PD_S 2
 #define BB_DC_EST_FORCE_PU (BIT(1))
+#define BB_DC_EST_FORCE_PU_M (BIT(1))
+#define BB_DC_EST_FORCE_PU_V 1
 #define BB_DC_EST_FORCE_PU_S 1
 #define BB_DC_EST_FORCE_PD (BIT(0))
+#define BB_DC_EST_FORCE_PD_M (BIT(0))
+#define BB_DC_EST_FORCE_PD_V 1
 #define BB_DC_EST_FORCE_PD_S 0
 
 

components/soc/esp32/include/soc/emac_ex_reg.h

@@ -23,75 +23,135 @@ extern "C" {
 
 #define EMAC_EX_CLKOUT_CONF_REG (REG_EMAC_EX_BASE + 0x0000)
 #define EMAC_EX_CLK_OUT_DLY_NUM 0x00000003
+#define EMAC_EX_CLK_OUT_DLY_NUM_M (EMAC_EX_CLK_OUT_DLY_NUM_V << EMAC_EX_CLK_OUT_DLY_NUM_S)
+#define EMAC_EX_CLK_OUT_DLY_NUM_V 0x00000003
 #define EMAC_EX_CLK_OUT_DLY_NUM_S 8
 #define EMAC_EX_CLK_OUT_H_DIV_NUM 0x0000000F
+#define EMAC_EX_CLK_OUT_H_DIV_NUM_M (EMAC_EX_CLK_OUT_H_DIV_NUM_V << EMAC_EX_CLK_OUT_H_DIV_NUM_S)
+#define EMAC_EX_CLK_OUT_H_DIV_NUM_V 0x0000000F
 #define EMAC_EX_CLK_OUT_H_DIV_NUM_S 4
 #define EMAC_EX_CLK_OUT_DIV_NUM 0x0000000F
+#define EMAC_EX_CLK_OUT_DIV_NUM_M (EMAC_EX_CLK_OUT_DIV_NUM_V << EMAC_EX_CLK_OUT_DIV_NUM_S)
+#define EMAC_EX_CLK_OUT_DIV_NUM_V 0x0000000F
 #define EMAC_EX_CLK_OUT_DIV_NUM_S 0
 
 #define EMAC_EX_OSCCLK_CONF_REG (REG_EMAC_EX_BASE + 0x0004)
 #define EMAC_EX_OSC_CLK_SEL (BIT(24))
+#define EMAC_EX_OSC_CLK_SEL_M (BIT(24))
+#define EMAC_EX_OSC_CLK_SEL_V 1
 #define EMAC_EX_OSC_CLK_SEL_S 24
 #define EMAC_EX_OSC_H_DIV_NUM_100M 0x0000003F
+#define EMAC_EX_OSC_H_DIV_NUM_100M_M (EMAC_EX_OSC_H_DIV_NUM_100M_V << EMAC_EX_OSC_H_DIV_NUM_100M_S)
+#define EMAC_EX_OSC_H_DIV_NUM_100M_V 0x0000003F
 #define EMAC_EX_OSC_H_DIV_NUM_100M_S 18
 #define EMAC_EX_OSC_DIV_NUM_100M 0x0000003F
+#define EMAC_EX_OSC_DIV_NUM_100M_M (EMAC_EX_OSC_DIV_NUM_100M_V << EMAC_EX_OSC_DIV_NUM_100M_S)
+#define EMAC_EX_OSC_DIV_NUM_100M_V 0x0000003F
 #define EMAC_EX_OSC_DIV_NUM_100M_S 12
 #define EMAC_EX_OSC_H_DIV_NUM_10M 0x0000003F
+#define EMAC_EX_OSC_H_DIV_NUM_10M_M (EMAC_EX_OSC_H_DIV_NUM_10M_V << EMAC_EX_OSC_H_DIV_NUM_10M_S)
+#define EMAC_EX_OSC_H_DIV_NUM_10M_V 0x0000003F
 #define EMAC_EX_OSC_H_DIV_NUM_10M_S 6
 #define EMAC_EX_OSC_DIV_NUM_10M 0x0000003F
+#define EMAC_EX_OSC_DIV_NUM_10M_M (EMAC_EX_OSC_DIV_NUM_10M_V << EMAC_EX_OSC_DIV_NUM_10M_S)
+#define EMAC_EX_OSC_DIV_NUM_10M_V 0x0000003F
 #define EMAC_EX_OSC_DIV_NUM_10M_S 0
 
 #define EMAC_EX_CLK_CTRL_REG (REG_EMAC_EX_BASE + 0x0008)
 #define EMAC_EX_CLK_EN (BIT(5))
+#define EMAC_EX_CLK_EN_M (BIT(5))
+#define EMAC_EX_CLK_EN_V 1
 #define EMAC_EX_CLK_EN_S 5
 #define EMAC_EX_MII_CLK_RX_EN (BIT(4))
+#define EMAC_EX_MII_CLK_RX_EN_M (BIT(4))
+#define EMAC_EX_MII_CLK_RX_EN_V 1
 #define EMAC_EX_MII_CLK_RX_EN_S 4
 #define EMAC_EX_MII_CLK_TX_EN (BIT(3))
+#define EMAC_EX_MII_CLK_TX_EN_M (BIT(3))
+#define EMAC_EX_MII_CLK_TX_EN_V 1
 #define EMAC_EX_MII_CLK_TX_EN_S 3
 #define EMAC_EX_RX_125_CLK_EN (BIT(2))
+#define EMAC_EX_RX_125_CLK_EN_M (BIT(2))
+#define EMAC_EX_RX_125_CLK_EN_V 1
 #define EMAC_EX_RX_125_CLK_EN_S 2
 #define EMAC_EX_INT_OSC_EN (BIT(1))
+#define EMAC_EX_INT_OSC_EN_M (BIT(1))
+#define EMAC_EX_INT_OSC_EN_V 1
 #define EMAC_EX_INT_OSC_EN_S 1
 #define EMAC_EX_EXT_OSC_EN (BIT(0))
+#define EMAC_EX_EXT_OSC_EN_M (BIT(0))
+#define EMAC_EX_EXT_OSC_EN_V 1
 #define EMAC_EX_EXT_OSC_EN_S 0
 
 #define EMAC_EX_PHYINF_CONF_REG (REG_EMAC_EX_BASE + 0x000c)
 #define EMAC_EX_TX_ERR_OUT_EN (BIT(20))
+#define EMAC_EX_TX_ERR_OUT_EN_M (BIT(20))
+#define EMAC_EX_TX_ERR_OUT_EN_V 1
 #define EMAC_EX_TX_ERR_OUT_EN_S 20
 #define EMAC_EX_SCR_SMI_DLY_RX_SYNC (BIT(19))
+#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_M (BIT(19))
+#define EMAC_EX_SCR_SMI_DLY_RX_SYNC_V 1
 #define EMAC_EX_SCR_SMI_DLY_RX_SYNC_S 19
 #define EMAC_EX_PMT_CTRL_EN (BIT(18))
+#define EMAC_EX_PMT_CTRL_EN_M (BIT(18))
+#define EMAC_EX_PMT_CTRL_EN_V 1
 #define EMAC_EX_PMT_CTRL_EN_S 18
 #define EMAC_EX_SBD_CLK_GATING_EN (BIT(17))
+#define EMAC_EX_SBD_CLK_GATING_EN_M (BIT(17))
+#define EMAC_EX_SBD_CLK_GATING_EN_V 1
 #define EMAC_EX_SBD_CLK_GATING_EN_S 17
 #define EMAC_EX_SS_MODE (BIT(16))
+#define EMAC_EX_SS_MODE_M (BIT(16))
+#define EMAC_EX_SS_MODE_V 1
 #define EMAC_EX_SS_MODE_S 16
 #define EMAC_EX_PHY_INTF_SEL 0x00000007
+#define EMAC_EX_PHY_INTF_SEL_M (EMAC_EX_PHY_INTF_SEL_V << EMAC_EX_PHY_INTF_SEL_S)
+#define EMAC_EX_PHY_INTF_SEL_V 0x00000007
 #define EMAC_EX_PHY_INTF_SEL_S 13
 #define EMAC_EX_REVMII_PHY_ADDR 0x0000001F
+#define EMAC_EX_REVMII_PHY_ADDR_M (EMAC_EX_REVMII_PHY_ADDR_V << EMAC_EX_REVMII_PHY_ADDR_S)
+#define EMAC_EX_REVMII_PHY_ADDR_V 0x0000001F
 #define EMAC_EX_REVMII_PHY_ADDR_S 8
 #define EMAC_EX_CORE_PHY_ADDR 0x0000001F
+#define EMAC_EX_CORE_PHY_ADDR_M (EMAC_EX_CORE_PHY_ADDR_V << EMAC_EX_CORE_PHY_ADDR_S)
+#define EMAC_EX_CORE_PHY_ADDR_V 0x0000001F
 #define EMAC_EX_CORE_PHY_ADDR_S 3
 #define EMAC_EX_SBD_FLOWCTRL (BIT(2))
+#define EMAC_EX_SBD_FLOWCTRL_M (BIT(2))
+#define EMAC_EX_SBD_FLOWCTRL_V 1
 #define EMAC_EX_SBD_FLOWCTRL_S 2
 #define EMAC_EX_EXT_REVMII_RX_CLK_SEL (BIT(1))
+#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_M (BIT(1))
+#define EMAC_EX_EXT_REVMII_RX_CLK_SEL_V 1
 #define EMAC_EX_EXT_REVMII_RX_CLK_SEL_S 1
 #define EMAC_EX_INT_REVMII_RX_CLK_SEL (BIT(0))
+#define EMAC_EX_INT_REVMII_RX_CLK_SEL_M (BIT(0))
+#define EMAC_EX_INT_REVMII_RX_CLK_SEL_V 1
 #define EMAC_EX_INT_REVMII_RX_CLK_SEL_S 0
 
 #define EMAC_EX_PHY_INTF_RMII  4
 
 #define EMAC_EX_EMAC_PD_SEL_REG (REG_EMAC_EX_BASE + 0x0010)
 #define EMAC_EX_RAM_PD_EN 0x00000003
+#define EMAC_EX_RAM_PD_EN_M (EMAC_EX_RAM_PD_EN_V << EMAC_EX_RAM_PD_EN_S)
+#define EMAC_EX_RAM_PD_EN_V 0x00000003
 #define EMAC_EX_RAM_PD_EN_S 0
 
 #define EMAC_EX_DATE_REG (REG_EMAC_EX_BASE + 0x00fc)
 #define EMAC_EX_DATE 0xFFFFFFFF
+#define EMAC_EX_DATE_M (EMAC_EX_DATE_V << EMAC_EX_DATE_S)
+#define EMAC_EX_DATE_V 0xFFFFFFFF
 #define EMAC_EX_DATE_S 0
 #define EMAC_EX_DATE_VERSION 0x16042200
+#define EMAC_EX_DATE_VERSION_M (EMAC_EX_DATE_VERSION_V << EMAC_EX_DATE_VERSION_S)
+#define EMAC_EX_DATE_VERSION_V 0x16042200
 
 #define EMAC_CLK_EN_REG 0x3ff000cc
+#define EMAC_CLK_EN_REG_M (EMAC_CLK_EN_REG_V << EMAC_CLK_EN_REG_S)
+#define EMAC_CLK_EN_REG_V 0x3ff000cc
 #define EMAC_CLK_EN (BIT(14))
+#define EMAC_CLK_EN_M (BIT(14))
+#define EMAC_CLK_EN_V 1
 
 #ifdef __cplusplus
 }

components/soc/esp32/include/soc/fe_reg.h

@@ -22,12 +22,20 @@
 
 #define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
 #define FE_IQ_EST_FORCE_PU (BIT(5))
+#define FE_IQ_EST_FORCE_PU_M (BIT(5))
+#define FE_IQ_EST_FORCE_PU_V 1
 #define FE_IQ_EST_FORCE_PU_S 5
 #define FE_IQ_EST_FORCE_PD (BIT(4))
+#define FE_IQ_EST_FORCE_PD_M (BIT(4))
+#define FE_IQ_EST_FORCE_PD_V 1
 #define FE_IQ_EST_FORCE_PD_S 4
 
 #define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
 #define FE2_TX_INF_FORCE_PU (BIT(10))
+#define FE2_TX_INF_FORCE_PU_M (BIT(10))
+#define FE2_TX_INF_FORCE_PU_V 1
 #define FE2_TX_INF_FORCE_PU_S 10
 #define FE2_TX_INF_FORCE_PD (BIT(9))
+#define FE2_TX_INF_FORCE_PD_M (BIT(9))
+#define FE2_TX_INF_FORCE_PD_V 1
 #define FE2_TX_INF_FORCE_PD_S 9

components/soc/esp32/include/soc/io_mux_reg.h

@@ -1,9 +1,9 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -16,19 +16,61 @@
 
 #include "soc.h"
 
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
 #define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
 #define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
 #define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
 #define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
 #define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
 #define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
 #define SLP_DRV_S 5
+/* Pulldown enable */
 #define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
 #define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
 #define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
 #define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
 #define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
 #define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
 #define MCU_SEL_S 12
 
 #define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)

components/soc/esp32/include/soc/nrx_reg.h

@@ -22,18 +22,34 @@
 
 #define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
 #define NRX_CHAN_EST_FORCE_PU (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_V 1
 #define NRX_CHAN_EST_FORCE_PU_S 7
 #define NRX_CHAN_EST_FORCE_PD (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_V 1
 #define NRX_CHAN_EST_FORCE_PD_S 6
 #define NRX_RX_ROT_FORCE_PU (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_V 1
 #define NRX_RX_ROT_FORCE_PU_S 5
 #define NRX_RX_ROT_FORCE_PD (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_V 1
 #define NRX_RX_ROT_FORCE_PD_S 4
 #define NRX_VIT_FORCE_PU (BIT(3))
+#define NRX_VIT_FORCE_PU_M (BIT(3))
+#define NRX_VIT_FORCE_PU_V 1
 #define NRX_VIT_FORCE_PU_S 3
 #define NRX_VIT_FORCE_PD (BIT(2))
+#define NRX_VIT_FORCE_PD_M (BIT(2))
+#define NRX_VIT_FORCE_PD_V 1
 #define NRX_VIT_FORCE_PD_S 2
 #define NRX_DEMAP_FORCE_PU (BIT(1))
+#define NRX_DEMAP_FORCE_PU_M (BIT(1))
+#define NRX_DEMAP_FORCE_PU_V 1
 #define NRX_DEMAP_FORCE_PU_S 1
 #define NRX_DEMAP_FORCE_PD (BIT(0))
+#define NRX_DEMAP_FORCE_PD_M (BIT(0))
+#define NRX_DEMAP_FORCE_PD_V 1
 #define NRX_DEMAP_FORCE_PD_S 0

components/soc/esp32/include/soc/soc.h

@@ -1,9 +1,9 @@
-// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -89,8 +89,8 @@
 //get field from register, uses field _S & _V to determine mask
 #define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
 
-//set field to register, used when _f is not left shifted by _f##_S
-#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
+//set field of a register from variable, uses field _S & _V to determine mask
+#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
 
 //get field value from a variable, used when _f is not left shifted by _f##_S
 #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))