diff --git a/components/driver/adc_common.c b/components/driver/adc_common.c
index 8a987d2b16..2272a21bc5 100644
--- a/components/driver/adc_common.c
+++ b/components/driver/adc_common.c
@@ -593,6 +593,12 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
     //avoid collision with other tasks
     adc2_init();   // in critical section with whole rtc module. because the PWDET use the same registers, place it here.
     SARADC2_ENTER();
+
+#if SOC_ADC_ARBITER_SUPPORTED
+    adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
+    adc_hal_arbiter_config(&config);
+#endif
+
 #ifdef CONFIG_ADC_DISABLE_DAC
     adc2_dac_disable(channel);      //disable other peripherals
 #endif
diff --git a/components/driver/esp32c3/adc.c b/components/driver/esp32c3/adc.c
index 693810da4a..91dff0b5c5 100644
--- a/components/driver/esp32c3/adc.c
+++ b/components/driver/esp32c3/adc.c
@@ -538,6 +538,9 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *
 
     SAR_ADC2_LOCK_ACQUIRE();
 
+    adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
+    adc_hal_arbiter_config(&config);
+
     adc_atten_t atten = s_atten2_single[channel];
     uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten);
     adc_hal_set_calibration_param(ADC_NUM_2, cal_val);
diff --git a/components/hal/adc_hal.c b/components/hal/adc_hal.c
index db93aa7f86..b5e3c701dd 100644
--- a/components/hal/adc_hal.c
+++ b/components/hal/adc_hal.c
@@ -44,6 +44,14 @@ void adc_hal_init(void)
     adc_ll_digi_set_clk_div(SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT);
 }
 
+#if SOC_ADC_ARBITER_SUPPORTED
+void adc_hal_arbiter_config(adc_arbiter_t *config)
+{
+    adc_ll_set_arbiter_work_mode(config->mode);
+    adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
+}
+#endif
+
 /*---------------------------------------------------------------
                     ADC calibration setting
 ---------------------------------------------------------------*/
@@ -339,6 +347,7 @@ static void adc_hal_onetime_start(void)
     adc_ll_onetime_start(false);
     esp_rom_delay_us(delay);
     adc_ll_onetime_start(true);
+
     //No need to delay here. Becuase if the start signal is not seen, there won't be a done intr.
 }
 
diff --git a/components/hal/esp32c3/adc_hal.c b/components/hal/esp32c3/adc_hal.c
index e4b893bdb6..c2fcaab27e 100644
--- a/components/hal/esp32c3/adc_hal.c
+++ b/components/hal/esp32c3/adc_hal.c
@@ -142,24 +142,3 @@ void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable)
     s_monitor_enabled[mon_idx] = enable;
     update_monitor(mon_idx);
 }
-
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to `adc_arbiter_t`.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config)
-{
-    adc_ll_set_arbiter_work_mode(config->mode);
-    adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
-}
diff --git a/components/hal/esp32c3/include/hal/adc_hal.h b/components/hal/esp32c3/include/hal/adc_hal.h
index 9993f9e8d9..1425acf0e1 100644
--- a/components/hal/esp32c3/include/hal/adc_hal.h
+++ b/components/hal/esp32c3/include/hal/adc_hal.h
@@ -97,23 +97,6 @@ void adc_hal_digi_monitor_config(adc_digi_monitor_idx_t mon_idx, adc_digi_monito
  */
 void adc_hal_digi_monitor_enable(adc_digi_monitor_idx_t mon_idx, bool enable);
 
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to `adc_arbiter_t`.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32s2/adc_hal.c b/components/hal/esp32s2/adc_hal.c
index 6ffd5349ae..b11de2776f 100644
--- a/components/hal/esp32s2/adc_hal.c
+++ b/components/hal/esp32s2/adc_hal.c
@@ -122,24 +122,3 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
     adc_ll_digi_monitor_set_mode(adc_n, config->mode);
     adc_ll_digi_monitor_set_thres(adc_n, config->threshold);
 }
-
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to ``adc_arbiter_t``.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config)
-{
-    adc_ll_set_arbiter_work_mode(config->mode);
-    adc_ll_set_arbiter_priority(config->rtc_pri, config->dig_pri, config->pwdet_pri);
-}
diff --git a/components/hal/esp32s2/include/hal/adc_hal.h b/components/hal/esp32s2/include/hal/adc_hal.h
index ac80417ff3..a49618f07c 100644
--- a/components/hal/esp32s2/include/hal/adc_hal.h
+++ b/components/hal/esp32s2/include/hal/adc_hal.h
@@ -197,23 +197,6 @@ void adc_hal_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
  */
 #define adc_hal_rtc_reset() adc_ll_rtc_reset()
 
-/*---------------------------------------------------------------
-                    Common setting
----------------------------------------------------------------*/
-
-/**
- * Config ADC2 module arbiter.
- * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
- * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
- *
- * @note Only ADC2 support arbiter.
- * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
- * @note Default priority: Wi-Fi > RTC > Digital;
- *
- * @param config Refer to ``adc_arbiter_t``.
- */
-void adc_hal_arbiter_config(adc_arbiter_t *config);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/include/hal/adc_hal.h b/components/hal/include/hal/adc_hal.h
index 1c1a399a4d..5effc61b4b 100644
--- a/components/hal/include/hal/adc_hal.h
+++ b/components/hal/include/hal/adc_hal.h
@@ -114,6 +114,22 @@ void adc_hal_init(void);
 #define adc_hal_amp_disable() adc_ll_amp_disable()
 #endif
 
+#if SOC_ADC_ARBITER_SUPPORTED
+//No ADC2 controller arbiter on ESP32
+/**
+ * Config ADC2 module arbiter.
+ * The arbiter is to improve the use efficiency of ADC2. After the control right is robbed by the high priority,
+ * the low priority controller will read the invalid ADC2 data, and the validity of the data can be judged by the flag bit in the data.
+ *
+ * @note Only ADC2 support arbiter.
+ * @note The arbiter's working clock is APB_CLK. When the APB_CLK clock drops below 8 MHz, the arbiter must be in shield mode.
+ * @note Default priority: Wi-Fi > RTC > Digital;
+ *
+ * @param config Refer to ``adc_arbiter_t``.
+ */
+void adc_hal_arbiter_config(adc_arbiter_t *config);
+#endif  //#if SOC_ADC_ARBITER_SUPPORTED
+
 /*---------------------------------------------------------------
                     PWDET(Power detect) controller setting
 ---------------------------------------------------------------*/
diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h
index 65a923d26c..c792018c96 100644
--- a/components/soc/esp32c3/include/soc/soc_caps.h
+++ b/components/soc/esp32c3/include/soc/soc_caps.h
@@ -44,6 +44,7 @@
 //F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095
 #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH          83333
 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW           611
+#define SOC_ADC_ARBITER_SUPPORTED               1
 
 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
 #define SOC_APB_BACKUP_DMA              (1)
diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h
index 13ef55669e..0f633b8ef7 100644
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -77,6 +77,7 @@
  */
 #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
 #define SOC_ADC_SUPPORT_RTC_CTRL        1
+#define SOC_ADC_ARBITER_SUPPORTED       1
 
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
 #define SOC_BROWNOUT_RESET_SUPPORTED 1
diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h
index 1242ad4f64..9ebf9cd61d 100644
--- a/components/soc/esp32s3/include/soc/soc_caps.h
+++ b/components/soc/esp32s3/include/soc/soc_caps.h
@@ -34,6 +34,7 @@
 #define SOC_ADC_MAX_CHANNEL_NUM         (10)
 #define SOC_ADC_MAX_BITWIDTH            (12)
 #define SOC_ADC_SUPPORT_RTC_CTRL        (1)
+#define SOC_ADC_ARBITER_SUPPORTED       (1)
 
 
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/