kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/esp32c3_uart_add_wakeup_event_v4.4' into 'release/v4.4'
UART: add uart wakeup event for esp32c3 and esp32s3 (v4.4) See merge request espressif/esp-idf!22647pull/11147/head
commit
3c8bc2213c
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -58,6 +58,9 @@ typedef enum {
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UART_PARITY_ERR, /*!< UART RX parity event*/
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UART_DATA_BREAK, /*!< UART TX data and break event*/
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UART_PATTERN_DET, /*!< UART pattern detected */
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#if SOC_UART_SUPPORT_WAKEUP_INT
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UART_WAKEUP, /*!< UART wakeup event */
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#endif
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UART_EVENT_MAX, /*!< UART event max index*/
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} uart_event_type_t;
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -59,11 +59,20 @@ static const char *UART_TAG = "uart";
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#define UART_PATTERN_DET_QLEN_DEFAULT (10)
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#define UART_MIN_WAKEUP_THRESH (UART_LL_MIN_WAKEUP_THRESH)
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#if SOC_UART_SUPPORT_WAKEUP_INT
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#define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
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| (UART_INTR_RXFIFO_TOUT) \
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| (UART_INTR_RXFIFO_OVF) \
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| (UART_INTR_BRK_DET) \
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| (UART_INTR_PARITY_ERR)) \
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| (UART_INTR_WAKEUP)
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#else
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#define UART_INTR_CONFIG_FLAG ((UART_INTR_RXFIFO_FULL) \
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| (UART_INTR_RXFIFO_TOUT) \
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| (UART_INTR_RXFIFO_OVF) \
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| (UART_INTR_BRK_DET) \
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| (UART_INTR_PARITY_ERR))
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#endif
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#define UART_ENTER_CRITICAL_SAFE(mux) portENTER_CRITICAL_SAFE(mux)
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@ -1111,7 +1120,14 @@ static void UART_ISR_ATTR uart_rx_intr_handler_default(void *param)
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UART_EXIT_CRITICAL_ISR(&(uart_context[uart_num].spinlock));
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xSemaphoreGiveFromISR(p_uart_obj[uart_num]->tx_done_sem, &HPTaskAwoken);
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}
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} else {
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}
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#if SOC_UART_SUPPORT_WAKEUP_INT
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else if (uart_intr_status & UART_INTR_WAKEUP) {
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uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_INTR_WAKEUP);
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uart_event.type = UART_WAKEUP;
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}
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#endif
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else {
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uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), uart_intr_status); /*simply clear all other intr status*/
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uart_event.type = UART_EVENT_MAX;
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}
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@ -1,16 +1,8 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for UART register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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@ -59,6 +51,7 @@ typedef enum {
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UART_INTR_RS485_FRM_ERR = (0x1 << 16),
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UART_INTR_RS485_CLASH = (0x1 << 17),
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UART_INTR_CMD_CHAR_DET = (0x1 << 18),
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UART_INTR_WAKEUP = (0x1 << 19),
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} uart_intr_t;
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static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) {
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@ -59,6 +59,7 @@ typedef enum {
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UART_INTR_RS485_FRM_ERR = (0x1 << 16),
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UART_INTR_RS485_CLASH = (0x1 << 17),
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UART_INTR_CMD_CHAR_DET = (0x1 << 18),
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UART_INTR_WAKEUP = (0x1 << 19),
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} uart_intr_t;
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static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en) {
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@ -1,16 +1,8 @@
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// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for UART register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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@ -57,6 +49,7 @@ typedef enum {
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UART_INTR_RS485_FRM_ERR = (0x1<<16),
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UART_INTR_RS485_CLASH = (0x1<<17),
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UART_INTR_CMD_CHAR_DET = (0x1<<18),
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UART_INTR_WAKEUP = (0x1 << 19),
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} uart_intr_t;
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/**
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@ -1,16 +1,8 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for UART register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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@ -60,6 +52,7 @@ typedef enum {
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UART_INTR_RS485_FRM_ERR = (0x1 << 16),
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UART_INTR_RS485_CLASH = (0x1 << 17),
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UART_INTR_CMD_CHAR_DET = (0x1 << 18),
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UART_INTR_WAKEUP = (0x1 << 19),
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} uart_intr_t;
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/**
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -277,6 +277,7 @@
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#define SOC_UART_SUPPORT_RTC_CLK (1)
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#define SOC_UART_SUPPORT_XTAL_CLK (1)
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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#define SOC_UART_REQUIRE_CORE_RESET (1)
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// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
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@ -258,7 +258,7 @@
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#define SOC_UART_NUM (2)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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#define SOC_UART_SUPPORT_RTC_CLK (1)
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#define SOC_UART_SUPPORT_XTAL_CLK (1)
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -260,6 +260,7 @@
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/*-------------------------- UART CAPS ---------------------------------------*/
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// ESP32-S2 has 2 UART.
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#define SOC_UART_NUM (2)
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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#define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -258,8 +258,13 @@
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#include "twai_caps.h"
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/*-------------------------- UART CAPS ---------------------------------------*/
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#include "uart_caps.h"
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// ESP32-S3 has 3 UARTs
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#define SOC_UART_NUM (3)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
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#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
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#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
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#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
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#define SOC_UART_REQUIRE_CORE_RESET (1)
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@ -1,31 +0,0 @@
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// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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#define SOC_UART_NUM (3)
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// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
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#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
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#ifdef __cplusplus
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}
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#endif
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