From fb15f970d25c360b59ff3b2ae0be883a9c64e1de Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Wed, 18 Jul 2018 16:56:19 +0800 Subject: [PATCH 1/2] spi_master: change test to test DMA tx/rx in regions like psram --- components/driver/test/test_spi_master.c | 101 ++++++++++++++--------- 1 file changed, 60 insertions(+), 41 deletions(-) diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index 5a7b490109..2037afd372 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -22,6 +22,7 @@ #include "soc/spi_periph.h" #include "freertos/ringbuf.h" #include "soc/gpio_periph.h" +#include "sdkconfig.h" const static char TAG[] = "test_spi"; @@ -495,10 +496,21 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" TEST_ASSERT(spi_bus_free(host) == ESP_OK); } -IRAM_ATTR static uint32_t data_iram[320]; -DRAM_ATTR static uint32_t data_dram[320]={0}; +IRAM_ATTR static uint32_t data_iram[80]; +DRAM_ATTR static uint32_t data_dram[80]={0}; //force to place in code area. -static const uint32_t data_drom[320] = {0}; +static const uint8_t data_drom[320+3] = { +0xD8, 0xD1, 0x0A, 0xB8, 0xCE, 0x67, 0x1B, 0x11, 0x17, 0xA0, 0xDA, 0x89, 0x55, 0xC1, 0x40, 0x0F, 0x55, 0xEB, 0xF7, 0xEC, 0xF0, 0x3C, 0x0F, 0x4D, 0x2B, 0x9E, 0xBF, 0xCD, 0x57, 0x2C, 0x48, 0x1A, +0x8B, 0x47, 0xC5, 0x01, 0x0C, 0x05, 0x80, 0x30, 0xF4, 0xEA, 0xE5, 0x92, 0x56, 0x97, 0x98, 0x78, 0x21, 0x34, 0xA1, 0xBC, 0xAE, 0x93, 0x7E, 0x96, 0x08, 0xE6, 0x54, 0x6A, 0x6C, 0x67, 0xCF, 0x58, +0xEE, 0x15, 0xA8, 0xB6, 0x32, 0x8C, 0x85, 0xF7, 0xE9, 0x88, 0x5E, 0xB1, 0x76, 0xE4, 0xB2, 0xC7, 0x0F, 0x57, 0x51, 0x7A, 0x2F, 0xAB, 0x12, 0xC3, 0x37, 0x99, 0x4E, 0x67, 0x75, 0x28, 0xE4, 0x1D, +0xF8, 0xBA, 0x22, 0xCB, 0xA1, 0x18, 0x4C, 0xAB, 0x5F, 0xC9, 0xF3, 0xA2, 0x39, 0x92, 0x44, 0xE6, 0x7B, 0xE3, 0xD0, 0x16, 0xC5, 0xC2, 0xCB, 0xD9, 0xC0, 0x7F, 0x06, 0xBF, 0x3E, 0xCE, 0xE1, 0x26, +0xD5, 0x3C, 0xAD, 0x0E, 0xC1, 0xC7, 0x7D, 0x0D, 0x56, 0x85, 0x6F, 0x32, 0xC8, 0x63, 0x8D, 0x12, 0xAB, 0x1E, 0x81, 0x7B, 0xF4, 0xF1, 0xA9, 0xAF, 0xD9, 0x74, 0x60, 0x05, 0x3D, 0xCC, 0x0C, 0x34, +0x11, 0x44, 0xAE, 0x2A, 0x13, 0x2F, 0x04, 0xC3, 0x59, 0xF0, 0x54, 0x07, 0xBA, 0x26, 0xD9, 0xFB, 0x80, 0x95, 0xC0, 0x14, 0xFA, 0x27, 0xEF, 0xD3, 0x58, 0xB8, 0xE4, 0xA2, 0xE3, 0x5E, 0x94, 0xB3, +0xCD, 0x2C, 0x4F, 0xAC, 0x3B, 0xD1, 0xCA, 0xBE, 0x61, 0x71, 0x7B, 0x62, 0xEB, 0xF0, 0xFC, 0xEF, 0x22, 0xB7, 0x3F, 0x56, 0x65, 0x19, 0x61, 0x73, 0x1A, 0x4D, 0xE4, 0x23, 0xE5, 0x3A, 0x91, 0x5C, +0xE6, 0x1B, 0x5F, 0x0E, 0x10, 0x94, 0x7C, 0x9F, 0xCF, 0x75, 0xB3, 0xEB, 0x42, 0x4C, 0xCF, 0xFE, 0xAF, 0x68, 0x62, 0x3F, 0x9A, 0x3C, 0x81, 0x3E, 0x7A, 0x45, 0x92, 0x79, 0x91, 0x4F, 0xFF, 0xDE, +0x25, 0x18, 0x33, 0xB9, 0xA9, 0x3A, 0x3F, 0x1F, 0x4F, 0x4B, 0x5C, 0x71, 0x82, 0x75, 0xB0, 0x1F, 0xE9, 0x98, 0xA3, 0xE2, 0x65, 0xBB, 0xCA, 0x4F, 0xB7, 0x1D, 0x23, 0x43, 0x16, 0x73, 0xBD, 0x83, +0x70, 0x22, 0x7D, 0x0A, 0x6D, 0xD3, 0x77, 0x73, 0xD0, 0xF4, 0x06, 0xB2, 0x19, 0x8C, 0xFF, 0x58, 0xE4, 0xDB, 0xE9, 0xEC, 0x89, 0x6A, 0xF4, 0x0E, 0x67, 0x12, 0xEC, 0x11, 0xD2, 0x1F, 0x8D, 0xD7, +}; #if 1 //HSPI #define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO @@ -518,77 +530,84 @@ static const uint32_t data_drom[320] = {0}; TEST_CASE("SPI Master DMA test, TX and RX in different regions", "[spi]") { - uint32_t data_rxdram[320]; +#ifdef CONFIG_SPIRAM_SUPPORT + //test psram if enabled + ESP_LOGI(TAG, "testing PSRAM..."); + uint32_t* data_malloc = (uint32_t*)heap_caps_calloc(1, 324, MALLOC_CAP_SPIRAM); +#else + uint32_t* data_malloc = (uint32_t*)heap_caps_calloc(1, 324, MALLOC_CAP_DMA); +#endif + + TEST_ASSERT(data_malloc != NULL); + + srand(52); + for (int i = 0; i < 320/4; i++) { + data_iram[i] = rand(); + data_dram[i] = rand(); + data_malloc[i] = rand(); + } esp_err_t ret; spi_device_handle_t spi; - spi_bus_config_t buscfg={ - .miso_io_num=PIN_NUM_MISO, - .mosi_io_num=PIN_NUM_MOSI, - .sclk_io_num=PIN_NUM_CLK, - .quadwp_io_num=-1, - .quadhd_io_num=-1 - }; - spi_device_interface_config_t devcfg={ - .clock_speed_hz=10000000, //Clock out at 10 MHz - .mode=0, //SPI mode 0 - .spics_io_num=PIN_NUM_CS, //CS pin - .queue_size=7, //We want to be able to queue 7 transactions at a time - .pre_cb=NULL, //Specify pre-transfer callback to handle D/C line - }; + spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); + buscfg.miso_io_num = PIN_NUM_MOSI; + spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); + //Initialize the SPI bus ret=spi_bus_initialize(HSPI_HOST, &buscfg, 1); TEST_ASSERT(ret==ESP_OK); //Attach the LCD to the SPI bus ret=spi_bus_add_device(HSPI_HOST, &devcfg, &spi); TEST_ASSERT(ret==ESP_OK); + //connect MOSI to two devices breaks the output, fix it. + gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX); - static spi_transaction_t trans[6]; +#define TEST_REGION_SIZE 5 + static spi_transaction_t trans[TEST_REGION_SIZE]; int x; - printf("iram: %p, dram: %p, drom: %p\n", data_iram, data_dram, data_drom); + ESP_LOGI(TAG, "iram: %p, dram: %p", data_iram, data_dram); + ESP_LOGI(TAG, "drom: %p, malloc: %p", data_drom, data_malloc); memset(trans, 0, 6*sizeof(spi_transaction_t)); trans[0].length = 320*8, trans[0].tx_buffer = data_iram; - trans[0].rx_buffer = data_rxdram; + trans[0].rx_buffer = data_malloc+1; trans[1].length = 320*8, trans[1].tx_buffer = data_dram; - trans[1].rx_buffer = data_rxdram; + trans[1].rx_buffer = data_iram; trans[2].length = 320*8, - trans[2].tx_buffer = data_drom; - trans[2].rx_buffer = data_rxdram; + trans[2].tx_buffer = data_malloc+2; + trans[2].rx_buffer = data_dram; trans[3].length = 320*8, trans[3].tx_buffer = data_drom; trans[3].rx_buffer = data_iram; - trans[4].length = 320*8, - trans[4].rxlength = 8*4; - trans[4].tx_buffer = data_drom; - trans[4].flags = SPI_TRANS_USE_RXDATA; - - trans[5].length = 8*4; - trans[5].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA; + trans[4].length = 4*8, + trans[4].flags = SPI_TRANS_USE_RXDATA | SPI_TRANS_USE_TXDATA; + uint32_t* ptr = (uint32_t*)trans[4].rx_data; + *ptr = 0x54545454; + ptr = (uint32_t*)trans[4].tx_data; + *ptr = 0xbc124960; //Queue all transactions. - for (x=0; x<6; x++) { - ret=spi_device_queue_trans(spi,&trans[x], portMAX_DELAY); + for (x=0; x Date: Mon, 23 Jul 2018 18:47:57 +0800 Subject: [PATCH 2/2] spi_master: enable 2 tests in CI The test is previously disabled for the requirement of external connection. Now the signals are connected by internal connections. Also change the failure logic of the test. --- components/driver/test/test_spi_master.c | 74 +++++++++++++----------- 1 file changed, 40 insertions(+), 34 deletions(-) diff --git a/components/driver/test/test_spi_master.c b/components/driver/test/test_spi_master.c index 2037afd372..8887d5cefc 100644 --- a/components/driver/test/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -119,7 +119,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") static spi_device_handle_t setup_spi_bus(int clkspeed, bool dma) { spi_bus_config_t buscfg={ - .mosi_io_num=4, + .mosi_io_num=26, .miso_io_num=26, .sclk_io_num=25, .quadwp_io_num=-1, @@ -138,22 +138,24 @@ static spi_device_handle_t setup_spi_bus(int clkspeed, bool dma) { }; esp_err_t ret; spi_device_handle_t handle; - printf("THIS TEST NEEDS A JUMPER BETWEEN IO4 AND IO26\n"); ret=spi_bus_initialize(HSPI_HOST, &buscfg, dma?1:0); TEST_ASSERT(ret==ESP_OK); ret=spi_bus_add_device(HSPI_HOST, &devcfg, &handle); TEST_ASSERT(ret==ESP_OK); + //connect MOSI to two devices breaks the output, fix it. + gpio_output_sel(26, FUNC_GPIO, HSPID_OUT_IDX); printf("Bus/dev inited.\n"); return handle; } -static void spi_test(spi_device_handle_t handle, int num_bytes) { +static int spi_test(spi_device_handle_t handle, int num_bytes) { esp_err_t ret; int x; + bool success = true; srand(num_bytes); - char *sendbuf=heap_caps_malloc(num_bytes, MALLOC_CAP_DMA); - char *recvbuf=heap_caps_malloc(num_bytes, MALLOC_CAP_DMA); + char *sendbuf=heap_caps_malloc((num_bytes+3)&(~3), MALLOC_CAP_DMA); + char *recvbuf=heap_caps_malloc((num_bytes+3)&(~3), MALLOC_CAP_DMA); for (x=0; x