kopia lustrzana https://github.com/espressif/esp-idf
esp32: move crosscore int
rodzic
7d85c42e52
commit
393bd64a1e
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@ -14,7 +14,6 @@ else()
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set(srcs
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set(srcs
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"cache_sram_mmu.c"
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"cache_sram_mmu.c"
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"clk.c"
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"clk.c"
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"crosscore_int.c"
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"dport_access.c"
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"dport_access.c"
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"esp_himem.c"
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"esp_himem.c"
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"spiram.c"
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"spiram.c"
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@ -12,7 +12,6 @@ else()
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# Regular app build
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# Regular app build
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set(srcs "clk.c"
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set(srcs "clk.c"
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"crosscore_int.c"
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"dport_access.c"
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"dport_access.c"
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"esp_hmac.c"
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"esp_hmac.c"
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"esp_ds.c"
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"esp_ds.c"
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@ -1,100 +0,0 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "hal/cpu_hal.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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#define REASON_YIELD BIT(0)
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#define REASON_FREQ_SWITCH BIT(1)
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#define REASON_PRINT_BACKTRACE BIT(2)
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason[portNUM_PROCESSORS];
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// TODO ESP32-C3 IDF-2449
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static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
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{
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portYIELD_FROM_ISR();
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}
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static void IRAM_ATTR esp_crosscore_isr(void *arg)
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{
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uint32_t my_reason_val;
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//A pointer to the correct reason array item is passed to this ISR.
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volatile uint32_t *my_reason = arg;
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//Clear the interrupt first.
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
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//Grab the reason and clear it.
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portENTER_CRITICAL_ISR(&reason_spinlock);
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my_reason_val = *my_reason;
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*my_reason = 0;
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portEXIT_CRITICAL_ISR(&reason_spinlock);
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//Check what we need to do.
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if (my_reason_val & REASON_YIELD) {
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esp_crosscore_isr_handle_yield();
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}
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if (my_reason_val & REASON_FREQ_SWITCH) {
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/* Nothing to do here; the frequency switch event was already
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* handled by a hook in xtensa_vectors.S. Could be used in the future
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* to allow DFS features without the extra latency of the ISR hook.
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*/
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}
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// TODO: ESP32-C3 IDF-2986
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// if (my_reason_val & REASON_PRINT_BACKTRACE) {
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// esp_backtrace_print(100);
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// }
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}
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// Initialize the crosscore interrupt on this core.
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void esp_crosscore_int_init(void)
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{
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portENTER_CRITICAL(&reason_spinlock);
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reason[cpu_hal_get_core_id()] = 0;
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portEXIT_CRITICAL(&reason_spinlock);
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[0], NULL));
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}
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static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
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{
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assert(core_id < portNUM_PROCESSORS);
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//Mark the reason we interrupt the other CPU
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portENTER_CRITICAL(&reason_spinlock);
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reason[core_id] |= reason_mask;
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portEXIT_CRITICAL(&reason_spinlock);
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//Poke the other CPU.
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
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}
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void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_YIELD);
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}
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void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
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}
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void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
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}
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@ -13,7 +13,6 @@ else()
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set(srcs "memprot.c"
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set(srcs "memprot.c"
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"clk.c"
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"clk.c"
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"crosscore_int.c"
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"dport_access.c"
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"dport_access.c"
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"spiram.c"
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"spiram.c"
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"spiram_psram.c"
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"spiram_psram.c"
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@ -1,109 +0,0 @@
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <string.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp_debug_helpers.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/periph_defs.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#define REASON_YIELD BIT(0)
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#define REASON_FREQ_SWITCH BIT(1)
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#define REASON_PRINT_BACKTRACE BIT(2)
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason;
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/*
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ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
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the ISR will cause it to switch _away_ from it. portYIELD_FROM_ISR will probably just schedule the task again, but have to check that.
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*/
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static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
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{
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portYIELD_FROM_ISR();
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}
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static void IRAM_ATTR esp_crosscore_isr(void *arg) {
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uint32_t my_reason_val;
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//A pointer to the correct reason item is passed to this ISR.
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volatile uint32_t *my_reason=arg;
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//Clear the interrupt first.
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
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//Grab the reason and clear it.
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portENTER_CRITICAL_ISR(&reason_spinlock);
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my_reason_val=*my_reason;
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*my_reason=0;
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portEXIT_CRITICAL_ISR(&reason_spinlock);
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//Check what we need to do.
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if (my_reason_val & REASON_YIELD) {
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esp_crosscore_isr_handle_yield();
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}
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if (my_reason_val & REASON_FREQ_SWITCH) {
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/* Nothing to do here; the frequency switch event was already
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* handled by a hook in xtensa_vectors.S. Could be used in the future
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* to allow DFS features without the extra latency of the ISR hook.
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*/
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}
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if (my_reason_val & REASON_PRINT_BACKTRACE) {
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esp_backtrace_print(100);
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}
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}
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//Initialize the crosscore interrupt on this core.
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void esp_crosscore_int_init(void) {
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portENTER_CRITICAL(&reason_spinlock);
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reason = 0;
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portEXIT_CRITICAL(&reason_spinlock);
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason, NULL));
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}
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static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
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assert(core_id<portNUM_PROCESSORS);
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//Mark the reason we interrupt the current CPU
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portENTER_CRITICAL(&reason_spinlock);
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reason |= reason_mask;
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portEXIT_CRITICAL(&reason_spinlock);
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//Poke the current CPU.
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DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
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}
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void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_YIELD);
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}
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void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
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}
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void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
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}
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@ -13,7 +13,6 @@ else()
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# Regular app build
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# Regular app build
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set(srcs "clk.c"
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set(srcs "clk.c"
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"crosscore_int.c"
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"dport_access.c"
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"dport_access.c"
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"esp_crypto_lock.c"
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"esp_crypto_lock.c"
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"memprot.c"
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"memprot.c"
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@ -1,111 +0,0 @@
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// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_intr_alloc.h"
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#include "esp_debug_helpers.h"
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#include "soc/periph_defs.h"
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#include "soc/system_reg.h"
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#include "hal/cpu_hal.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/portmacro.h"
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#define REASON_YIELD BIT(0)
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#define REASON_FREQ_SWITCH BIT(1)
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#define REASON_PRINT_BACKTRACE BIT(2)
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static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
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static volatile uint32_t reason[portNUM_PROCESSORS];
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static inline void IRAM_ATTR esp_crosscore_isr_handle_yield(void)
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{
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portYIELD_FROM_ISR();
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}
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static void IRAM_ATTR esp_crosscore_isr(void *arg)
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{
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uint32_t my_reason_val;
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//A pointer to the correct reason array item is passed to this ISR.
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volatile uint32_t *my_reason = arg;
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//Clear the interrupt first.
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if (cpu_hal_get_core_id() == 0) {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
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} else {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
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}
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//Grab the reason and clear it.
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portENTER_CRITICAL_ISR(&reason_spinlock);
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my_reason_val = *my_reason;
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*my_reason = 0;
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portEXIT_CRITICAL_ISR(&reason_spinlock);
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//Check what we need to do.
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if (my_reason_val & REASON_YIELD) {
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esp_crosscore_isr_handle_yield();
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}
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if (my_reason_val & REASON_FREQ_SWITCH) {
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/* Nothing to do here; the frequency switch event was already
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* handled by a hook in xtensa_vectors.S. Could be used in the future
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* to allow DFS features without the extra latency of the ISR hook.
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*/
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}
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if (my_reason_val & REASON_PRINT_BACKTRACE) {
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esp_backtrace_print(100);
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}
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}
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// Initialize the crosscore interrupt on this core.
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void esp_crosscore_int_init(void)
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{
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portENTER_CRITICAL(&reason_spinlock);
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reason[cpu_hal_get_core_id()] = 0;
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portEXIT_CRITICAL(&reason_spinlock);
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if (cpu_hal_get_core_id() == 0) {
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[0], NULL));
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} else {
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ESP_ERROR_CHECK(esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void *)&reason[1], NULL));
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}
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}
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static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
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{
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assert(core_id < portNUM_PROCESSORS);
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//Mark the reason we interrupt the other CPU
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portENTER_CRITICAL(&reason_spinlock);
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reason[core_id] |= reason_mask;
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portEXIT_CRITICAL(&reason_spinlock);
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//Poke the other CPU.
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if (core_id == 0) {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
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} else {
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WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
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}
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}
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void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
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{
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esp_crosscore_int_send(core_id, REASON_YIELD);
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}
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||||||
|
|
||||||
void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
|
|
||||||
{
|
|
||||||
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
|
|
||||||
}
|
|
||||||
|
|
||||||
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
|
|
||||||
{
|
|
||||||
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
|
|
||||||
}
|
|
|
@ -10,7 +10,8 @@ if(BOOTLOADER_BUILD)
|
||||||
# Bootloader relies on some Kconfig options defined in esp_system.
|
# Bootloader relies on some Kconfig options defined in esp_system.
|
||||||
idf_component_register(SRCS "${srcs}")
|
idf_component_register(SRCS "${srcs}")
|
||||||
else()
|
else()
|
||||||
list(APPEND srcs "esp_err.c"
|
list(APPEND srcs "crosscore_int.c"
|
||||||
|
"esp_err.c"
|
||||||
"freertos_hooks.c"
|
"freertos_hooks.c"
|
||||||
"intr_alloc.c"
|
"intr_alloc.c"
|
||||||
"int_wdt.c"
|
"int_wdt.c"
|
||||||
|
|
|
@ -12,30 +12,31 @@
|
||||||
// See the License for the specific language governing permissions and
|
// See the License for the specific language governing permissions and
|
||||||
// limitations under the License.
|
// limitations under the License.
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
#include "esp_attr.h"
|
#include "esp_attr.h"
|
||||||
#include "esp_err.h"
|
#include "esp_err.h"
|
||||||
#include "esp_intr_alloc.h"
|
#include "esp_intr_alloc.h"
|
||||||
#include "esp_debug_helpers.h"
|
#include "esp_debug_helpers.h"
|
||||||
|
#include "soc/periph_defs.h"
|
||||||
|
|
||||||
#include "soc/cpu.h"
|
#include "hal/cpu_hal.h"
|
||||||
#include "soc/dport_reg.h"
|
|
||||||
#include "soc/gpio_periph.h"
|
|
||||||
#include "soc/rtc_periph.h"
|
|
||||||
|
|
||||||
#include "freertos/FreeRTOS.h"
|
#include "freertos/FreeRTOS.h"
|
||||||
#include "freertos/task.h"
|
#include "freertos/portmacro.h"
|
||||||
#include "freertos/semphr.h"
|
|
||||||
#include "freertos/queue.h"
|
|
||||||
|
|
||||||
|
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
|
||||||
|
#include "soc/dport_reg.h"
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
|
||||||
|
#include "soc/system_reg.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
#define REASON_YIELD BIT(0)
|
#define REASON_YIELD BIT(0)
|
||||||
#define REASON_FREQ_SWITCH BIT(1)
|
#define REASON_FREQ_SWITCH BIT(1)
|
||||||
|
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32C3
|
||||||
#define REASON_PRINT_BACKTRACE BIT(2)
|
#define REASON_PRINT_BACKTRACE BIT(2)
|
||||||
|
#endif
|
||||||
|
|
||||||
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
|
static portMUX_TYPE reason_spinlock = portMUX_INITIALIZER_UNLOCKED;
|
||||||
static volatile uint32_t reason[ portNUM_PROCESSORS ];
|
static volatile uint32_t reason[portNUM_PROCESSORS];
|
||||||
|
|
||||||
/*
|
/*
|
||||||
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
|
ToDo: There is a small chance the CPU already has yielded when this ISR is serviced. In that case, it's running the intended task but
|
||||||
|
@ -52,11 +53,24 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
|
||||||
volatile uint32_t *my_reason=arg;
|
volatile uint32_t *my_reason=arg;
|
||||||
|
|
||||||
//Clear the interrupt first.
|
//Clear the interrupt first.
|
||||||
if (xPortGetCoreID()==0) {
|
#if CONFIG_IDF_TARGET_ESP32
|
||||||
|
if (cpu_hal_get_core_id()==0) {
|
||||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
|
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
|
||||||
} else {
|
} else {
|
||||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
|
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
|
||||||
}
|
}
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||||
|
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||||
|
if (cpu_hal_get_core_id()==0) {
|
||||||
|
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
|
||||||
|
} else {
|
||||||
|
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0);
|
||||||
|
}
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||||
|
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0);
|
||||||
|
#endif
|
||||||
|
|
||||||
//Grab the reason and clear it.
|
//Grab the reason and clear it.
|
||||||
portENTER_CRITICAL_ISR(&reason_spinlock);
|
portENTER_CRITICAL_ISR(&reason_spinlock);
|
||||||
my_reason_val=*my_reason;
|
my_reason_val=*my_reason;
|
||||||
|
@ -73,24 +87,30 @@ static void IRAM_ATTR esp_crosscore_isr(void *arg) {
|
||||||
* to allow DFS features without the extra latency of the ISR hook.
|
* to allow DFS features without the extra latency of the ISR hook.
|
||||||
*/
|
*/
|
||||||
}
|
}
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32C3 // IDF-2986
|
||||||
if (my_reason_val & REASON_PRINT_BACKTRACE) {
|
if (my_reason_val & REASON_PRINT_BACKTRACE) {
|
||||||
esp_backtrace_print(100);
|
esp_backtrace_print(100);
|
||||||
}
|
}
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
//Initialize the crosscore interrupt on this core. Call this once
|
//Initialize the crosscore interrupt on this core. Call this once
|
||||||
//on each active core.
|
//on each active core.
|
||||||
void esp_crosscore_int_init(void) {
|
void esp_crosscore_int_init(void) {
|
||||||
portENTER_CRITICAL(&reason_spinlock);
|
portENTER_CRITICAL(&reason_spinlock);
|
||||||
reason[xPortGetCoreID()]=0;
|
reason[cpu_hal_get_core_id()]=0;
|
||||||
portEXIT_CRITICAL(&reason_spinlock);
|
portEXIT_CRITICAL(&reason_spinlock);
|
||||||
esp_err_t err __attribute__((unused));
|
esp_err_t err __attribute__((unused)) = ESP_OK;
|
||||||
if (xPortGetCoreID()==0) {
|
#if portNUM_PROCESSORS > 1
|
||||||
|
if (cpu_hal_get_core_id()==0) {
|
||||||
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
|
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
|
||||||
} else {
|
} else {
|
||||||
err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
|
err = esp_intr_alloc(ETS_FROM_CPU_INTR1_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[1], NULL);
|
||||||
}
|
}
|
||||||
assert(err == ESP_OK);
|
#else
|
||||||
|
err = esp_intr_alloc(ETS_FROM_CPU_INTR0_SOURCE, ESP_INTR_FLAG_IRAM, esp_crosscore_isr, (void*)&reason[0], NULL);
|
||||||
|
#endif
|
||||||
|
ESP_ERROR_CHECK(err);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
|
static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask) {
|
||||||
|
@ -100,11 +120,23 @@ static void IRAM_ATTR esp_crosscore_int_send(int core_id, uint32_t reason_mask)
|
||||||
reason[core_id] |= reason_mask;
|
reason[core_id] |= reason_mask;
|
||||||
portEXIT_CRITICAL_ISR(&reason_spinlock);
|
portEXIT_CRITICAL_ISR(&reason_spinlock);
|
||||||
//Poke the other CPU.
|
//Poke the other CPU.
|
||||||
|
#if CONFIG_IDF_TARGET_ESP32
|
||||||
if (core_id==0) {
|
if (core_id==0) {
|
||||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
|
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
|
||||||
} else {
|
} else {
|
||||||
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
|
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
|
||||||
}
|
}
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
||||||
|
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||||
|
if (core_id==0) {
|
||||||
|
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
|
||||||
|
} else {
|
||||||
|
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1);
|
||||||
|
}
|
||||||
|
#elif CONFIG_IDF_TARGET_ESP32C3
|
||||||
|
WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
|
void IRAM_ATTR esp_crosscore_int_send_yield(int core_id)
|
||||||
|
@ -117,7 +149,9 @@ void IRAM_ATTR esp_crosscore_int_send_freq_switch(int core_id)
|
||||||
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
|
esp_crosscore_int_send(core_id, REASON_FREQ_SWITCH);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32C3
|
||||||
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
|
void IRAM_ATTR esp_crosscore_int_send_print_backtrace(int core_id)
|
||||||
{
|
{
|
||||||
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
|
esp_crosscore_int_send(core_id, REASON_PRINT_BACKTRACE);
|
||||||
}
|
}
|
||||||
|
#endif
|
|
@ -14,6 +14,8 @@
|
||||||
#ifndef __ESP_CROSSCORE_INT_H
|
#ifndef __ESP_CROSSCORE_INT_H
|
||||||
#define __ESP_CROSSCORE_INT_H
|
#define __ESP_CROSSCORE_INT_H
|
||||||
|
|
||||||
|
#include "sdkconfig.h"
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
extern "C" {
|
extern "C" {
|
||||||
#endif
|
#endif
|
||||||
|
@ -54,6 +56,8 @@ void esp_crosscore_int_send_yield(int core_id);
|
||||||
*/
|
*/
|
||||||
void esp_crosscore_int_send_freq_switch(int core_id);
|
void esp_crosscore_int_send_freq_switch(int core_id);
|
||||||
|
|
||||||
|
|
||||||
|
#if !CONFIG_IDF_TARGET_ESP32C3
|
||||||
/**
|
/**
|
||||||
* Send an interrupt to a CPU indicating it should print its current backtrace
|
* Send an interrupt to a CPU indicating it should print its current backtrace
|
||||||
*
|
*
|
||||||
|
@ -63,6 +67,7 @@ void esp_crosscore_int_send_freq_switch(int core_id);
|
||||||
* @param core_id Core that should print its backtrace
|
* @param core_id Core that should print its backtrace
|
||||||
*/
|
*/
|
||||||
void esp_crosscore_int_send_print_backtrace(int core_id);
|
void esp_crosscore_int_send_print_backtrace(int core_id);
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
|
|
Ładowanie…
Reference in New Issue