From 3610b14aef055f51def67bddaf98a5609d99c9b5 Mon Sep 17 00:00:00 2001 From: gaoxu Date: Tue, 23 Aug 2022 10:46:56 +0800 Subject: [PATCH] SPI : fix wrong dummy cycle on quad mode and put get-command function in spi_ll.h 1.The dummy_bits is set to 4 in ESP32C3/C2, therefore, the data transmission started too early.This commit fix this issue by changing dummy_bits to 8. 2.Put the spi command the spi defintion in spi_types.h 3.Put the function which get spi command or dummy bits in spi_ll.h --- .gitlab/ci/target-test.yml | 25 ++++ components/esp_serial_slave_link/essl_spi.c | 67 ++++++----- .../include/essl_spi/esp32c2_defs.h | 30 ----- .../include/essl_spi/esp32c3_defs.h | 38 ------ .../include/essl_spi/esp32h2_defs.h | 30 ----- .../include/essl_spi/esp32s2_defs.h | 38 ------ .../include/essl_spi/esp32s3_defs.h | 38 ------ components/hal/esp32/include/hal/spi_ll.h | 23 ++++ components/hal/esp32c2/include/hal/spi_ll.h | 102 ++++++++++++++++ components/hal/esp32c3/include/hal/spi_ll.h | 102 ++++++++++++++++ components/hal/esp32h2/include/hal/spi_ll.h | 102 ++++++++++++++++ components/hal/esp32s2/include/hal/spi_ll.h | 113 ++++++++++++++++++ components/hal/esp32s3/include/hal/spi_ll.h | 102 ++++++++++++++++ components/hal/include/hal/spi_types.h | 16 +++ 14 files changed, 620 insertions(+), 206 deletions(-) delete mode 100644 components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h delete mode 100644 components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h delete mode 100644 components/esp_serial_slave_link/include/essl_spi/esp32h2_defs.h delete mode 100644 components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h delete mode 100644 components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h diff --git a/.gitlab/ci/target-test.yml b/.gitlab/ci/target-test.yml index c4c3591d48..f5daa0e01b 100644 --- a/.gitlab/ci/target-test.yml +++ b/.gitlab/ci/target-test.yml @@ -935,6 +935,31 @@ UT_S2_SPI_DUAL: - ESP32S2_IDF - Example_SPI_Multi_device +UT_S2_SPI_QUAD: + extends: .unit_test_esp32s2_template + tags: + - ESP32S2_IDF + - Example_SPI_Quad_Multi_device + +UT_S3_SPI_QUAD: + extends: .unit_test_esp32s3_template + tags: + - ESP32S3_IDF + - Example_SPI_Quad_Multi_device + +UT_C2_SPI_QUAD: + extends: .unit_test_esp32c2_template + tags: + - ESP32C2_IDF + - Example_SPI_Quad_Multi_device + - xtal_40mhz + +UT_C3_SPI_QUAD: + extends: .unit_test_esp32c3_template + tags: + - ESP32C3_IDF + - Example_SPI_Quad_Multi_device + UT_S2_SDSPI: extends: .unit_test_esp32s2_template tags: diff --git a/components/esp_serial_slave_link/essl_spi.c b/components/esp_serial_slave_link/essl_spi.c index 4a6ece1a1a..00f933e34d 100644 --- a/components/esp_serial_slave_link/essl_spi.c +++ b/components/esp_serial_slave_link/essl_spi.c @@ -13,8 +13,8 @@ #include "esp_private/periph_ctrl.h" #include "essl_internal.h" #include "essl_spi.h" -#include "essl_spi/esp32s2_defs.h" - +#include "hal/spi_types.h" +#include "hal/spi_ll.h" /** * Initialise device function list of SPI by this macro. @@ -51,51 +51,54 @@ typedef struct { } master_in; } essl_spi_context_t; - -static uint16_t get_hd_command(uint16_t cmd_i, uint32_t flags) +static uint16_t get_hd_command(spi_command_t cmd_t, uint32_t flags) { - //have no prefixes - if (cmd_i == CMD_HD_EN_QPI_REG) return cmd_i; - //doesn't support 4-line commands - if(flags & SPI_TRANS_MODE_QIO && flags & SPI_TRANS_MODE_DIOQIO_ADDR && - (cmd_i == CMD_HD_WR_END_REG || cmd_i == CMD_HD_INT0_REG || - cmd_i == CMD_HD_INT1_REG || cmd_i == CMD_HD_INT2_REG)) { - //the transaction will be sent in corresponding 1/2/4 bit mode, without address and data. - //the CMD will have no 0xA- prefix - return cmd_i; - } + spi_line_mode_t line_mode = { + .cmd_lines = 1, + }; if (flags & SPI_TRANS_MODE_DIO) { + line_mode.data_lines = 2; if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) { - return cmd_i | CMD_HD_DIO_MODE; + line_mode.addr_lines = 2; } else { - return cmd_i | CMD_HD_DOUT_MODE; + line_mode.addr_lines = 1; } } else if (flags & SPI_TRANS_MODE_QIO) { + line_mode.data_lines = 4; if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) { - return cmd_i | CMD_HD_QIO_MODE; + line_mode.addr_lines = 4; } else { - return cmd_i | CMD_HD_QOUT_MODE; + line_mode.addr_lines = 1; } + } else { + line_mode.data_lines = 1; + line_mode.addr_lines = 1; } - return cmd_i | CMD_HD_ONEBIT_MODE; + + return spi_ll_get_slave_hd_command(cmd_t, line_mode); } static int get_hd_dummy_bits(uint32_t flags) { - //dummy is always 4 cycles when dual or quad mode is enabled. Otherwise 8 cycles in normal mode. - if (flags & (SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_QIO)) { - return 4; + spi_line_mode_t line_mode = {}; + + if (flags & SPI_TRANS_MODE_DIO) { + line_mode.data_lines = 2; + } else if (flags & SPI_TRANS_MODE_QIO) { + line_mode.data_lines = 4; } else { - return 8; + line_mode.data_lines = 1; } + + return spi_ll_get_slave_hd_dummy_bits(line_mode); } esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags) { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_RDBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags), .addr = addr % 72, .rxlength = len * 8, .rx_buffer = out_data, @@ -111,7 +114,7 @@ esp_err_t essl_spi_rdbuf_polling(spi_device_handle_t spi, uint8_t *out_data, int { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_RDBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags), .addr = addr % 72, .rxlength = len * 8, .rx_buffer = out_data, @@ -127,7 +130,7 @@ esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr, { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_WRBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags), .addr = addr % 72, .length = len * 8, .tx_buffer = data, @@ -142,7 +145,7 @@ esp_err_t essl_spi_wrbuf_polling(spi_device_handle_t spi, const uint8_t *data, i { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_WRBUF_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags), .addr = addr % 72, .length = len * 8, .tx_buffer = data, @@ -157,7 +160,7 @@ esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_RDDMA_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_RDDMA, flags), .rxlength = seg_len * 8, .rx_buffer = out_data, .flags = flags | SPI_TRANS_VARIABLE_DUMMY, @@ -170,7 +173,7 @@ esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags) { spi_transaction_t end_t = { - .cmd = get_hd_command(CMD_HD_INT0_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_INT0, flags), .flags = flags, }; return spi_device_transmit(spi, &end_t); @@ -201,7 +204,7 @@ esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int s { spi_transaction_ext_t t = { .base = { - .cmd = get_hd_command(CMD_HD_WRDMA_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WRDMA, flags), .length = seg_len * 8, .tx_buffer = data, .flags = flags | SPI_TRANS_VARIABLE_DUMMY, @@ -214,7 +217,7 @@ esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int s esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags) { spi_transaction_t end_t = { - .cmd = get_hd_command(CMD_HD_WR_END_REG, flags), + .cmd = get_hd_command(SPI_CMD_HD_WR_END, flags), .flags = flags, }; return spi_device_transmit(spi, &end_t); @@ -243,7 +246,7 @@ esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len, esp_err_t essl_spi_int(spi_device_handle_t spi, int int_n, uint32_t flags) { spi_transaction_t end_t = { - .cmd = get_hd_command(CMD_HD_INT0_REG + int_n, flags), + .cmd = get_hd_command(SPI_CMD_HD_INT0 + int_n, flags), .flags = flags, }; return spi_device_transmit(spi, &end_t); diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h deleted file mode 100644 index 51abd189b2..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32c2_defs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 64 diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h deleted file mode 100644 index 3dfd4a14b7..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32c3_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 64 diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32h2_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32h2_defs.h deleted file mode 100644 index 51abd189b2..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32h2_defs.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 64 diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h deleted file mode 100644 index 49ba82ddf0..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32s2_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 72 diff --git a/components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h b/components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h deleted file mode 100644 index 3dfd4a14b7..0000000000 --- a/components/esp_serial_slave_link/include/essl_spi/esp32s3_defs.h +++ /dev/null @@ -1,38 +0,0 @@ -// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - - -#pragma once - -// NOTE: From the view of master -#define CMD_HD_WRBUF_REG 0x01 -#define CMD_HD_RDBUF_REG 0x02 -#define CMD_HD_WRDMA_REG 0x03 -#define CMD_HD_RDDMA_REG 0x04 - -#define CMD_HD_ONEBIT_MODE 0x00 -#define CMD_HD_DOUT_MODE 0x10 -#define CMD_HD_QOUT_MODE 0x20 -#define CMD_HD_DIO_MODE 0x50 -#define CMD_HD_QIO_MODE 0xA0 - -#define CMD_HD_SEG_END_REG 0x05 -#define CMD_HD_EN_QPI_REG 0x06 -#define CMD_HD_WR_END_REG 0x07 -#define CMD_HD_INT0_REG 0x08 -#define CMD_HD_INT1_REG 0x09 -#define CMD_HD_INT2_REG 0x0A -#define CMD_HD_EX_QPI_REG 0xDD - -#define SPI_SLAVE_HD_BUFFER_SIZE 64 diff --git a/components/hal/esp32/include/hal/spi_ll.h b/components/hal/esp32/include/hal/spi_ll.h index 63efb384eb..cf09b6e94f 100644 --- a/components/hal/esp32/include/hal/spi_ll.h +++ b/components/hal/esp32/include/hal/spi_ll.h @@ -1081,6 +1081,29 @@ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uin //does not configure it in ESP32 } +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + //This is not supported in esp32 + return 0; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + //This is not supported in esp32 + return 0; +} + #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/components/hal/esp32c2/include/hal/spi_ll.h b/components/hal/esp32c2/include/hal/spi_ll.h index 13f5b6ed8d..ca67e3960a 100644 --- a/components/hal/esp32c2/include/hal/spi_ll.h +++ b/components/hal/esp32c2/include/hal/spi_ll.h @@ -74,6 +74,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32c2 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1073,6 +1088,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) return hw->slave1.last_addr; } +/** + * Get the base spi command in esp32c2 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK diff --git a/components/hal/esp32c3/include/hal/spi_ll.h b/components/hal/esp32c3/include/hal/spi_ll.h index 01070e918f..78b58de6c4 100644 --- a/components/hal/esp32c3/include/hal/spi_ll.h +++ b/components/hal/esp32c3/include/hal/spi_ll.h @@ -74,6 +74,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32c3 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1076,6 +1091,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32c3 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/spi_ll.h b/components/hal/esp32h2/include/hal/spi_ll.h index 8c7cc0bec2..d63b3a9e5c 100644 --- a/components/hal/esp32h2/include/hal/spi_ll.h +++ b/components/hal/esp32h2/include/hal/spi_ll.h @@ -74,6 +74,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32h2 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1074,6 +1089,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32h2 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 4; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/spi_ll.h b/components/hal/esp32s2/include/hal/spi_ll.h index 9b0fa420ec..65084c8d23 100644 --- a/components/hal/esp32s2/include/hal/spi_ll.h +++ b/components/hal/esp32s2/include/hal/spi_ll.h @@ -84,6 +84,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32s2 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1278,6 +1293,104 @@ static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32s2 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + uint8_t dummy_bits = 0; + + if (line_mode.data_lines == 2) { + dummy_bits = 4; + } else if (line_mode.data_lines == 4) { + dummy_bits = 4; + } else { + dummy_bits = 8; + } + + HAL_ASSERT(dummy_bits); + return dummy_bits; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/spi_ll.h b/components/hal/esp32s3/include/hal/spi_ll.h index 6058afe1e5..e210a76f8e 100644 --- a/components/hal/esp32s3/include/hal/spi_ll.h +++ b/components/hal/esp32s3/include/hal/spi_ll.h @@ -76,6 +76,21 @@ typedef enum { } spi_ll_trans_len_cond_t; FLAG_ATTR(spi_ll_trans_len_cond_t) +// SPI base command in esp32s3 +typedef enum { + /* Slave HD Only */ + SPI_LL_BASE_CMD_HD_WRBUF = 0x01, + SPI_LL_BASE_CMD_HD_RDBUF = 0x02, + SPI_LL_BASE_CMD_HD_WRDMA = 0x03, + SPI_LL_BASE_CMD_HD_RDDMA = 0x04, + SPI_LL_BASE_CMD_HD_SEG_END = 0x05, + SPI_LL_BASE_CMD_HD_EN_QPI = 0x06, + SPI_LL_BASE_CMD_HD_WR_END = 0x07, + SPI_LL_BASE_CMD_HD_INT0 = 0x08, + SPI_LL_BASE_CMD_HD_INT1 = 0x09, + SPI_LL_BASE_CMD_HD_INT2 = 0x0A, +} spi_ll_base_command_t; + /*------------------------------------------------------------------------------ * Control *----------------------------------------------------------------------------*/ @@ -1091,6 +1106,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw) #undef SPI_LL_RST_MASK #undef SPI_LL_UNUSED_INT_MASK +/** + * Get the base spi command in esp32s3 + * + * @param cmd_t Command value + */ +static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t) +{ + uint8_t cmd_base = 0x00; + switch (cmd_t) + { + case SPI_CMD_HD_WRBUF: + cmd_base = SPI_LL_BASE_CMD_HD_WRBUF; + break; + case SPI_CMD_HD_RDBUF: + cmd_base = SPI_LL_BASE_CMD_HD_RDBUF; + break; + case SPI_CMD_HD_WRDMA: + cmd_base = SPI_LL_BASE_CMD_HD_WRDMA; + break; + case SPI_CMD_HD_RDDMA: + cmd_base = SPI_LL_BASE_CMD_HD_RDDMA; + break; + case SPI_CMD_HD_SEG_END: + cmd_base = SPI_LL_BASE_CMD_HD_SEG_END; + break; + case SPI_CMD_HD_EN_QPI: + cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI; + break; + case SPI_CMD_HD_WR_END: + cmd_base = SPI_LL_BASE_CMD_HD_WR_END; + break; + case SPI_CMD_HD_INT0: + cmd_base = SPI_LL_BASE_CMD_HD_INT0; + break; + case SPI_CMD_HD_INT1: + cmd_base = SPI_LL_BASE_CMD_HD_INT1; + break; + case SPI_CMD_HD_INT2: + cmd_base = SPI_LL_BASE_CMD_HD_INT2; + break; + default: + HAL_ASSERT(cmd_base); + } + return cmd_base; +} + +/** + * Get the spi communication command + * + * @param cmd_t Base command value + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode) +{ + uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t); + uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit + + if (line_mode.data_lines == 2) { + if (line_mode.addr_lines == 2) { + cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit + } else { + cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit + } + } else if (line_mode.data_lines == 4) { + if (line_mode.addr_lines == 4) { + cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit + } else { + cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit + } + } + if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) { + cmd_mod = 0x00; + } + + return cmd_base | cmd_mod; +} + +/** + * Get the dummy bits + * + * @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN. + */ +static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode) +{ + return 8; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/spi_types.h b/components/hal/include/hal/spi_types.h index 37e9e53787..3420468872 100644 --- a/components/hal/include/hal/spi_types.h +++ b/components/hal/include/hal/spi_types.h @@ -53,6 +53,22 @@ typedef struct { uint8_t data_lines; ///< The line width of data phase, e.g. 4-line-data-phase. } spi_line_mode_t; +/** + * @brief SPI command. + */ +typedef enum { + /* Slave HD Only */ + SPI_CMD_HD_WRBUF = BIT(0), + SPI_CMD_HD_RDBUF = BIT(1), + SPI_CMD_HD_WRDMA = BIT(2), + SPI_CMD_HD_RDDMA = BIT(3), + SPI_CMD_HD_SEG_END = BIT(4), + SPI_CMD_HD_EN_QPI = BIT(5), + SPI_CMD_HD_WR_END = BIT(6), + SPI_CMD_HD_INT0 = BIT(7), + SPI_CMD_HD_INT1 = BIT(8), + SPI_CMD_HD_INT2 = BIT(9), +} spi_command_t; /** @cond */ //Doxy command to hide preprocessor definitions from docs */