kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/esp32p4_remove_fence' into 'master'
fix(riscv): Remove the memory barrier when changing interrupt threshold Closes IDF-7898 See merge request espressif/esp-idf!29119pull/13294/head
commit
345bf79b4e
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@ -60,15 +60,6 @@ FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_wait_for_intr(voi
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asm volatile ("wfi\n");
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}
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/* ------------------------------------------------- Memory Barrier ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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//TODO: IDF-7898
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FORCE_INLINE_ATTR void rv_utils_memory_barrier(void)
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{
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asm volatile("fence iorw, iorw" : : : "memory");
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}
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/* -------------------------------------------------- CPU Registers ----------------------------------------------------
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*
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* ------------------------------------------------------------------------------------------------------------------ */
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@ -191,15 +182,11 @@ FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel(
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REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((intlevel << (8 - NLBITS))) | 0x1f);
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/**
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* TODO: IDF-7898
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* Here is an issue that,
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* 1. Set the CLIC_INT_THRESH_REG to mask off interrupts whose level is lower than `intlevel`.
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* 2. Set MSTATUS_MIE (global interrupt), then program may jump to interrupt vector.
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* 3. The register value change in Step 1 may happen during Step 2.
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*
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* To prevent this, here a fence is used
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* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
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* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
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* operations is forced, making the new threshold active. It is then safe to re-enable MIE bit in mstatus.
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*/
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rv_utils_memory_barrier();
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REG_READ(CLIC_INT_THRESH_REG);
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RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
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return old_thresh;
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