From 3369f15fa3c46a09b5dcf1a2e05e260c921b1e87 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 20 Nov 2017 15:27:16 +0800 Subject: [PATCH] soc/rtc: don't power down BIAS_I2C along with APLL if other PLL is used If enable == false, and SOC_CLK_SEL == PLL, the code would would erroneously set RTC_CNTL_BIAS_I2C_FORCE_PD. This change fixes the logic. --- components/soc/esp32/rtc_clk.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/components/soc/esp32/rtc_clk.c b/components/soc/esp32/rtc_clk.c index aafae93263..7c8d9609a4 100644 --- a/components/soc/esp32/rtc_clk.c +++ b/components/soc/esp32/rtc_clk.c @@ -168,11 +168,12 @@ void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm { REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1); REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0); - REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD, enable ? 0 : 1); if (!enable && REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL) != RTC_CNTL_SOC_CLK_SEL_PLL) { - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); + REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); + } else { + REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD); } if (enable) {