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gdma: update DMA soc data for esp32-s3

pull/7307/head
morris 2021-06-15 19:14:15 +08:00
rodzic 217d3eb690
commit 3176ba11d8
6 zmienionych plików z 25 dodań i 44 usunięć
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3
components/driver/include/esp_private/gdma.h
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@ -38,7 +38,8 @@ typedef enum {
GDMA_TRIG_PERIPH_ADC, /*!< GDMA trigger peripheral: ADC */
GDMA_TRIG_PERIPH_DAC, /*!< GDMA trigger peripheral: DAC */
GDMA_TRIG_PERIPH_LCD, /*!< GDMA trigger peripheral: LCD */
GDMA_TRIG_PERIPH_CAM /*!< GDMA trigger peripheral: CAM */
GDMA_TRIG_PERIPH_CAM, /*!< GDMA trigger peripheral: CAM */
GDMA_TRIG_PERIPH_RMT, /*!< GDMA trigger peripheral: RMT */
} gdma_trigger_peripheral_t;
/**

38
components/hal/esp32s3/include/hal/gdma_ll.h
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@ -48,9 +48,12 @@ extern "C" {
#define GDMA_LL_EVENT_RX_SUC_EOF (1<<1)
#define GDMA_LL_EVENT_RX_DONE (1<<0)
/* Memory block size value supported by TX channel */
#define GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B (0)
#define GDMA_LL_OUT_EXT_MEM_BK_SIZE_32B (1)
#define GDMA_LL_L2FIFO_BASE_SIZE (16) // Basic size of GDMA Level 2 FIFO
/* Memory block size value supported by channel */
#define GDMA_LL_EXT_MEM_BK_SIZE_16B (0)
#define GDMA_LL_EXT_MEM_BK_SIZE_32B (1)
#define GDMA_LL_EXT_MEM_BK_SIZE_64B (2)
///////////////////////////////////// Common /////////////////////////////////////////
/**
@ -146,7 +149,7 @@ static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
/**
* @brief Set DMA RX channel memory block size
* @param size_index Supported value: GDMA_IN_EXT_MEM_BK_SIZE_16B, GDMA_IN_EXT_MEM_BK_SIZE_32B
* @param size_index Supported value: GDMA_LL_EXT_MEM_BK_SIZE_16B/32B/64B
*/
static inline void gdma_ll_rx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
@ -300,19 +303,6 @@ static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
dev->channel[channel].in.peri_sel.sel = periph_id;
}
/**
* @brief Extend the L2 FIFO size for RX channel
* @note By default, the L2 FIFO size is SOC_GDMA_L2_FIFO_BASE_SIZE Bytes. Suggest to extend it to twice the block size when accessing PSRAM.
* @note `size_in_bytes` should aligned to 8 and larger than SOC_GDMA_L2_FIFO_BASE_SIZE
*/
static inline void gdma_ll_rx_extend_l2_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->sram_size[channel].in.in_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}
///////////////////////////////////// TX /////////////////////////////////////////
/**
* @brief Get DMA TX channel interrupt status word
@ -401,7 +391,7 @@ static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
/**
* @brief Set DMA TX channel memory block size
* @param size_index Supported value: GDMA_OUT_EXT_MEM_BK_SIZE_16B, GDMA_OUT_EXT_MEM_BK_SIZE_32B
* @param size_index Supported value: GDMA_LL_EXT_MEM_BK_SIZE_16B/32B/64B
*/
static inline void gdma_ll_tx_set_block_size_psram(gdma_dev_t *dev, uint32_t channel, uint32_t size_index)
{
@ -531,18 +521,6 @@ static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channe
dev->channel[channel].out.peri_sel.sel = periph_id;
}
/**
* @brief Extend the L2 FIFO size for TX channel
* @note By default, the L2 FIFO size is SOC_GDMA_L2_FIFO_BASE_SIZE Bytes. Suggest to extend it to twice the block size when accessing PSRAM.
* @note `size_in_bytes` should aligned to 8 and larger than SOC_GDMA_L2_FIFO_BASE_SIZE
*/
static inline void gdma_ll_tx_extend_fifo_size_to(gdma_dev_t *dev, uint32_t channel, uint32_t size_in_bytes)
{
if (size_in_bytes > SOC_GDMA_L2_FIFO_BASE_SIZE) {
dev->sram_size[channel].out.out_size = (size_in_bytes - SOC_GDMA_L2_FIFO_BASE_SIZE) / 8;
}
}
#ifdef __cplusplus
}
#endif

8
components/hal/include/hal/dma_types.h
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@ -14,12 +14,12 @@
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief Type of DMA descriptor
*
@ -43,3 +43,7 @@ _Static_assert(sizeof(dma_descriptor_t) == 12, "dma_descriptor_t should occupy 1
#define DMA_DESCRIPTOR_BUFFER_OWNER_CPU (0) /*!< DMA buffer is allowed to be accessed by CPU */
#define DMA_DESCRIPTOR_BUFFER_OWNER_DMA (1) /*!< DMA buffer is allowed to be accessed by DMA engine */
#define DMA_DESCRIPTOR_BUFFER_MAX_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */
#ifdef __cplusplus
}
#endif

15
components/mbedtls/port/crypto_shared_gdma/esp_crypto_shared_gdma.c
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@ -54,7 +54,7 @@ static inline esp_err_t crypto_shared_gdma_new_channel(gdma_channel_alloc_config
}
#if SOC_GDMA_SUPPORT_EXTMEM
#if SOC_GDMA_SUPPORT_PSRAM
/* Initialize external memory specific DMA configs */
static void esp_crypto_shared_dma_init_extmem(void)
{
@ -64,13 +64,10 @@ static void esp_crypto_shared_dma_init_extmem(void)
gdma_get_channel_id(tx_channel, &tx_ch_id);
gdma_get_channel_id(rx_channel, &rx_ch_id);
/* An L2 FIFO bigger than 40 bytes is need when accessing external ram */
gdma_ll_tx_extend_fifo_size_to(&GDMA, tx_ch_id, 40);
gdma_ll_rx_extend_l2_fifo_size_to(&GDMA, rx_ch_id, 40);
gdma_ll_tx_set_block_size_psram(&GDMA, tx_ch_id, GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B);
gdma_ll_rx_set_block_size_psram(&GDMA, rx_ch_id, GDMA_LL_OUT_EXT_MEM_BK_SIZE_16B);
gdma_ll_tx_set_block_size_psram(&GDMA, tx_ch_id, GDMA_LL_EXT_MEM_BK_SIZE_16B);
gdma_ll_rx_set_block_size_psram(&GDMA, rx_ch_id, GDMA_LL_EXT_MEM_BK_SIZE_16B);
}
#endif //SOC_GDMA_SUPPORT_EXTMEM
#endif //SOC_GDMA_SUPPORT_PSRAM
/* Initialize GDMA module and channels */
static esp_err_t crypto_shared_gdma_init(void)
@ -96,9 +93,9 @@ static esp_err_t crypto_shared_gdma_init(void)
goto err;
}
#if SOC_GDMA_SUPPORT_EXTMEM
#if SOC_GDMA_SUPPORT_PSRAM
esp_crypto_shared_dma_init_extmem();
#endif //SOC_GDMA_SUPPORT_EXTMEM
#endif //SOC_GDMA_SUPPORT_PSRAM
gdma_connect(rx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));
gdma_connect(tx_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_AES, 0));

1
components/soc/esp32s3/include/soc/gdma_channel.h
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@ -27,3 +27,4 @@
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
#define SOC_GDMA_TRIG_PERIPH_DAC0 (8)
#define SOC_GDMA_TRIG_PERIPH_RMT0 (9)

4
components/soc/esp32s3/include/soc/soc_caps.h
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@ -44,8 +44,8 @@
/*-------------------------- GDMA CAPS ---------------------------------------*/
#define SOC_GDMA_GROUPS (1) // Number of GDMA groups
#define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group
#define SOC_GDMA_L2_FIFO_BASE_SIZE (16) // Basic size of GDMA Level 2 FIFO
#define SOC_GDMA_SUPPORT_EXTMEM (1) // GDMA can access external PSRAM
#define SOC_GDMA_SUPPORT_PSRAM (1) // GDMA can access external PSRAM
#define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction
/*-------------------------- GPIO CAPS ---------------------------------------*/
#include "gpio_caps.h"