From 2efd009dfb1352d5f9a0189bf4219e11eb0a454f Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 23 Mar 2022 17:43:24 +0800 Subject: [PATCH] ulp: temporarily disable ULP support for S3 Due to a hardware issue ULP support on S3 is temporarily disabled until a fixed is released. Running ULP + sleep together can potentially cause permanent damage to the chip. --- components/ulp/ulp_fsm/ulp.c | 6 ++++++ components/ulp/ulp_riscv/ulp_riscv.c | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/components/ulp/ulp_fsm/ulp.c b/components/ulp/ulp_fsm/ulp.c index f6c21b3dd1..5d138af12b 100644 --- a/components/ulp/ulp_fsm/ulp.c +++ b/components/ulp/ulp_fsm/ulp.c @@ -42,6 +42,12 @@ static const char* TAG = "ulp"; esp_err_t ulp_run(uint32_t entry_point) { +#if CONFIG_IDF_TARGET_ESP32S3 + ESP_LOGE(TAG, "ULP temporarily unsupported on ESP32-S3, running sleep + ULP risks causing permanent damage to chip"); + abort(); +// Fix in-progress: DIG-160 +#endif //CONFIG_IDF_TARGET_ESP32S3 + #if CONFIG_IDF_TARGET_ESP32 // disable ULP timer CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); diff --git a/components/ulp/ulp_riscv/ulp_riscv.c b/components/ulp/ulp_riscv/ulp_riscv.c index 7a769f1477..64e6999fe0 100644 --- a/components/ulp/ulp_riscv/ulp_riscv.c +++ b/components/ulp/ulp_riscv/ulp_riscv.c @@ -20,6 +20,8 @@ #include "ulp_common.h" #include "esp_rom_sys.h" +__attribute__((unused)) static const char* TAG = "ulp-riscv"; + static esp_err_t ulp_riscv_config_wakeup_source(ulp_riscv_wakeup_source_t wakeup_source) { esp_err_t ret = ESP_OK; @@ -46,6 +48,12 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) { esp_err_t ret = ESP_OK; +#if CONFIG_IDF_TARGET_ESP32S3 + ESP_LOGE(TAG, "ULP temporarily unsupported on ESP32-S3, running sleep + ULP risks causing permanent damage to chip"); + abort(); +// Fix in-progress: DIG-160 +#endif //CONFIG_IDF_TARGET_ESP32S3 + #if CONFIG_IDF_TARGET_ESP32S2 /* Reset COCPU when power on. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);