kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/fix_esp32s3_psram_access_failed_in_dfs_v5.1' into 'release/v5.1'
esp_pm: fix esp32s3 psram access failed when dfs is enabled (backport v5.1) See merge request espressif/esp-idf!24202pull/12369/head
commit
27a5a6fcae
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@ -563,8 +563,8 @@ void mspi_timing_enter_high_speed_mode(bool control_spi1)
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void mspi_timing_change_speed_mode_cache_safe(bool switch_down)
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{
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Cache_Freeze_ICache_Enable(1);
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Cache_Freeze_DCache_Enable(1);
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Cache_Freeze_ICache_Enable(CACHE_FREEZE_ACK_BUSY);
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Cache_Freeze_DCache_Enable(CACHE_FREEZE_ACK_BUSY);
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if (switch_down) {
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//enter MSPI low speed mode, extra delays should be removed
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mspi_timing_enter_low_speed_mode(false);
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@ -512,7 +512,7 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
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pd_flags &= ~RTC_SLEEP_PD_INT_8M;
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}
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// Turn down mspi clock speed
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// Will switch to XTAL turn down MSPI speed
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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mspi_timing_change_speed_mode_cache_safe(true);
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#endif
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@ -704,14 +704,15 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags, esp_sleep_mode_t mo
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}
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// Set mspi clock to ROM default one.
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if (cpu_freq_config.source == SOC_CPU_CLK_SRC_PLL) {
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#if SOC_MEMSPI_CLOCK_IS_INDEPENDENT
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spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT);
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spi_flash_set_clock_src(MSPI_CLK_SRC_DEFAULT);
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#endif
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// Speed up mspi clock freq
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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mspi_timing_change_speed_mode_cache_safe(false);
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// Turn up MSPI speed if switch to PLL
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mspi_timing_change_speed_mode_cache_safe(false);
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#endif
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}
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if (!deep_sleep) {
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s_config.ccount_ticks_record = esp_cpu_get_cycle_count();
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@ -10,11 +10,14 @@
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "esp_system.h"
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#include "esp_check.h"
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#include "esp_attr.h"
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#include "esp_flash.h"
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#include "esp_partition.h"
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#include "esp_pm.h"
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#include "esp_private/esp_clk.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/opi_flash.h"
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@ -32,9 +35,17 @@
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#define LENGTH_PER_TIME 1024
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#endif
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TEST_CASE("MSPI: Test_SPI0_PSRAM", "[mspi]")
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#define MHZ (1000000)
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#ifndef MIN
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#define MIN(x, y) (((x) < (y)) ? (x) : (y))
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#endif
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static SemaphoreHandle_t DoneSemphr;
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static SemaphoreHandle_t StopSemphr;
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static void psram_read_write_task(void* arg)
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{
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printf("----------SPI0 PSRAM Test----------\n");
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printf("----------SPI0 PSRAM Access Test----------\n");
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uint8_t *psram_wr_buf = (uint8_t *)heap_caps_malloc(LENGTH_PER_TIME, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
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if (!psram_wr_buf) {
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@ -42,28 +53,143 @@ TEST_CASE("MSPI: Test_SPI0_PSRAM", "[mspi]")
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abort();
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}
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uint32_t *psram_rd_buf = (uint32_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
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uint8_t *psram_rd_buf = (uint8_t *)heap_caps_malloc(SPI0_PSRAM_TEST_LEN, MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM);
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if (!psram_rd_buf) {
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printf("no memory\n");
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abort();
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}
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srand(399);
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for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) {
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for (int j = 0; j < sizeof(psram_wr_buf); j++) {
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psram_wr_buf[j] = rand();
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}
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memcpy(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME);
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for (uint32_t loop = 0; loop < (uint32_t)(arg); loop++) {
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for (int i = 0; i < SPI0_PSRAM_TEST_LEN / LENGTH_PER_TIME; i++) {
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for (int j = 0; j < sizeof(psram_wr_buf); j++) {
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psram_wr_buf[j] = rand();
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}
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memcpy(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME);
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if (memcmp(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME) != 0) {
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free(psram_rd_buf);
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free(psram_wr_buf);
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TEST_FAIL_MESSAGE("SPI0 PSRAM Test Fail");
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if (memcmp(psram_rd_buf + i * LENGTH_PER_TIME, psram_wr_buf, LENGTH_PER_TIME) != 0) {
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free(psram_rd_buf);
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free(psram_wr_buf);
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TEST_FAIL_MESSAGE("SPI0 PSRAM Test Fail");
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}
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}
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xSemaphoreGive(DoneSemphr);
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vTaskDelay(10);
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}
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free(psram_rd_buf);
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free(psram_wr_buf);
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printf(DRAM_STR("----------SPI0 PSRAM Test Success----------\n\n"));
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vTaskDelete(NULL);
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}
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static void pm_light_sleep_enable(void)
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{
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int cur_freq_mhz = esp_clk_cpu_freq() / MHZ;
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int xtal_freq = esp_clk_xtal_freq() / MHZ;
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esp_pm_config_t pm_config = {
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.max_freq_mhz = cur_freq_mhz,
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.min_freq_mhz = xtal_freq,
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.light_sleep_enable = true
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};
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TEST_ESP_OK( esp_pm_configure(&pm_config) );
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}
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static void pm_light_sleep_disable(void)
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{
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int cur_freq_mhz = esp_clk_cpu_freq() / MHZ;
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esp_pm_config_t pm_config = {
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.max_freq_mhz = cur_freq_mhz,
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.min_freq_mhz = cur_freq_mhz,
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};
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TEST_ESP_OK( esp_pm_configure(&pm_config) );
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}
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static void pm_switch_freq(int max_cpu_freq_mhz)
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{
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int xtal_freq_mhz = esp_clk_xtal_freq() / MHZ;
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esp_pm_config_t pm_config = {
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.max_freq_mhz = max_cpu_freq_mhz,
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.min_freq_mhz = MIN(max_cpu_freq_mhz, xtal_freq_mhz),
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};
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TEST_ESP_OK( esp_pm_configure(&pm_config) );
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printf("Waiting for frequency to be set to %d MHz...\n", max_cpu_freq_mhz);
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while (esp_clk_cpu_freq() / MHZ != max_cpu_freq_mhz)
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{
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vTaskDelay(pdMS_TO_TICKS(200));
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printf("Frequency is %d MHz\n", esp_clk_cpu_freq() / MHZ);
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}
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}
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static void goto_idle_and_check_stop(uint32_t period)
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{
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if (xSemaphoreTake(StopSemphr, pdMS_TO_TICKS(period)) == pdTRUE) {
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pm_switch_freq(CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ);
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vSemaphoreDelete(StopSemphr);
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vTaskDelete(NULL);
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}
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}
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static void pm_switch_task(void *arg)
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{
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pm_light_sleep_disable();
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uint32_t period = 100;
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StopSemphr = xSemaphoreCreateBinary();
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while (1) {
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pm_light_sleep_enable();
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goto_idle_and_check_stop(period);
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pm_light_sleep_disable();
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goto_idle_and_check_stop(period);
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pm_switch_freq(10);
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goto_idle_and_check_stop(period);
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pm_switch_freq(80);
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goto_idle_and_check_stop(period);
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pm_switch_freq(40);
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goto_idle_and_check_stop(period);
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}
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}
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TEST_CASE("MSPI: Test_SPI0_PSRAM", "[mspi]")
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{
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DoneSemphr = xSemaphoreCreateCounting(1, 0);
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xTaskCreate(psram_read_write_task, "", 2048, (void *)(1), 3, NULL);
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if (xSemaphoreTake(DoneSemphr, pdMS_TO_TICKS(100)) == pdTRUE) {
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printf(DRAM_STR("----------SPI0 PSRAM Test Success----------\n\n"));
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} else {
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TEST_FAIL_MESSAGE(DRAM_STR("SPI0 PSRAM Test Timeout"));
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}
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vSemaphoreDelete(DoneSemphr);
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/* Wait for test_task to finish up */
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vTaskDelay(100);
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}
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TEST_CASE("MSPI: Test_SPI0_PSRAM with DFS", "[mspi]")
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{
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printf("----------Access SPI0 PSRAM with DFS Test----------\n");
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uint32_t test_loop = 50;
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DoneSemphr = xSemaphoreCreateCounting(test_loop, 0);
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xTaskCreatePinnedToCore(pm_switch_task, "", 4096, NULL, 3, NULL, 0);
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xTaskCreatePinnedToCore(psram_read_write_task, "", 2048, (void *)(test_loop), 3, NULL, 1);
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int cnt = 0;
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while (cnt < test_loop) {
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if (xSemaphoreTake(DoneSemphr, pdMS_TO_TICKS(1000)) == pdTRUE) {
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cnt++;
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} else {
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vSemaphoreDelete(DoneSemphr);
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TEST_FAIL_MESSAGE(DRAM_STR("SPI0 PSRAM Test Timeout"));
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}
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}
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xSemaphoreGive(StopSemphr);
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vSemaphoreDelete(DoneSemphr);
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/* Wait for test_task to finish up */
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vTaskDelay(pdMS_TO_TICKS(500));
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printf(DRAM_STR("----------Access SPI0 PSRAM with DFS Test Success----------\n\n"));
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}
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#endif
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@ -4,3 +4,10 @@ CONFIG_ESP_TASK_WDT_EN=n
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CONFIG_PARTITION_TABLE_CUSTOM=y
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CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv"
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CONFIG_PARTITION_TABLE_FILENAME="partitions.csv"
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# For test access psram with DFS enabled
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CONFIG_SPIRAM_FETCH_INSTRUCTIONS=y
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CONFIG_SPIRAM_RODATA=y
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CONFIG_PM_ENABLE=y
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CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
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CONFIG_FREERTOS_IDLE_TIME_BEFORE_SLEEP=5
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@ -31,6 +31,10 @@
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#include "xtensa/core-macros.h"
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#endif
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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#include "esp_private/mspi_timing_tuning.h"
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#endif
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#include "esp_private/pm_impl.h"
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#include "esp_private/pm_trace.h"
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#include "esp_private/esp_timer_private.h"
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@ -475,7 +479,17 @@ static void IRAM_ATTR do_switch(pm_mode_t new_mode)
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if (switch_down) {
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on_freq_update(old_ticks_per_us, new_ticks_per_us);
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}
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rtc_clk_cpu_freq_set_config_fast(&new_config);
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if (new_config.source == SOC_CPU_CLK_SRC_PLL) {
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rtc_clk_cpu_freq_set_config_fast(&new_config);
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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mspi_timing_change_speed_mode_cache_safe(false);
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#endif
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} else {
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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mspi_timing_change_speed_mode_cache_safe(true);
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#endif
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rtc_clk_cpu_freq_set_config_fast(&new_config);
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}
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if (!switch_down) {
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on_freq_update(old_ticks_per_us, new_ticks_per_us);
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}
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@ -15,13 +15,20 @@
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* Feel free to change when debugging.
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*/
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static const int DRAM_ATTR s_trace_io[] = {
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
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BIT(4), BIT(5), // ESP_PM_TRACE_IDLE
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BIT(16), BIT(17), // ESP_PM_TRACE_TICK
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BIT(18), BIT(18), // ESP_PM_TRACE_FREQ_SWITCH
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BIT(19), BIT(19), // ESP_PM_TRACE_CCOMPARE_UPDATE
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BIT(25), BIT(26), // ESP_PM_TRACE_ISR_HOOK
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BIT(27), BIT(27), // ESP_PM_TRACE_SLEEP
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#elif CONFIG_IDF_TARGET_ESP32S3
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BIT(4), BIT(5), // ESP_PM_TRACE_IDLE
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BIT(6), BIT(7), // ESP_PM_TRACE_TICK
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BIT(14), BIT(14), // ESP_PM_TRACE_FREQ_SWITCH
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BIT(15), BIT(15), // ESP_PM_TRACE_CCOMPARE_UPDATE
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BIT(16), BIT(17), // ESP_PM_TRACE_ISR_HOOK
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BIT(18), BIT(18), // ESP_PM_TRACE_SLEEP
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#else
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BIT(2), BIT(3), // ESP_PM_TRACE_IDLE
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BIT(4), BIT(5), // ESP_PM_TRACE_TICK
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