feat(spiram): Add .noinit and .bss segement support on esp32c61

components/esp_common/test_apps/.build-test-rules.yml

@@ -4,6 +4,3 @@ components/esp_common/test_apps/esp_common:
   disable:
     - if: CONFIG_NAME == "psram" and SOC_SPIRAM_SUPPORTED != 1
     - if: CONFIG_NAME == "psram_noinit" and SOC_SPIRAM_SUPPORTED != 1
-    - if: CONFIG_NAME == "psram_noinit" and IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: esp32c61 is not supported yet # TODO: IDF-9293

components/esp_psram/test_apps/.build-test-rules.yml

@@ -3,10 +3,6 @@
 components/esp_psram/test_apps/psram:
   disable:
     - if: SOC_SPIRAM_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET in ["esp32c61"]
-      temporary: true
-      reason: No runner
   depends_components:
     - esp_psram
     - esp_mm

components/esp_system/ld/esp32c5/sections.ld.in

@@ -391,7 +391,7 @@ SECTIONS
   {
     . = ORIGIN(extern_ram_seg);
     . = . + (_rodata_reserved_end - _flash_rodata_dummy_start);
-    . = ALIGN (0x10000);
+    . = ALIGN (_esp_mmu_page_size);
   } > extern_ram_seg
 
 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY

components/esp_system/ld/esp32c61/memory.ld.in

@@ -78,6 +78,9 @@ MEMORY
      The aim of this is to keep data that will not be moved around and have a fixed address.
   */
   lp_reserved_seg(RW) :        org = 0x50000000 + 0x4000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
+
+    /* PSRAM seg */
+  extern_ram_seg(RWX) :        org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20
 }
 
 /* Heap ends at top of sram_seg */

components/esp_system/ld/esp32c61/sections.ld.in

@@ -379,6 +379,46 @@ SECTIONS
   } > default_rodata_seg
   ASSERT_SECTIONS_GAP(.flash.rodata, .eh_frame_hdr)
 
+
+  /* External RAM */
+  /**
+   * This section is required to skip flash sections, because `extern_ram_seg`
+   * and `drom_seg` / `irom_seg` are on the same bus when app build use flash sections
+   */
+  .ext_ram.dummy (NOLOAD):
+  {
+    . = ORIGIN(extern_ram_seg);
+    . = . + (_rodata_reserved_end - _flash_rodata_dummy_start);
+    . = ALIGN (_esp_mmu_page_size);
+  } > extern_ram_seg
+
+#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
+  /* This section holds .ext_ram.bss data, and will be put in PSRAM */
+  .ext_ram.bss (NOLOAD) :
+  {
+    _ext_ram_bss_start = ABSOLUTE(.);
+
+    mapping[extern_ram]
+
+    ALIGNED_SYMBOL(4, _ext_ram_bss_end)
+  } > extern_ram_seg
+#endif  //CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
+
+#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
+  /**
+   * This section holds data that won't be initialized when startup.
+   * This section locates in External RAM region.
+   */
+  .ext_ram_noinit (NOLOAD) :
+  {
+    _ext_ram_noinit_start = ABSOLUTE(.);
+
+    *(.ext_ram_noinit*)
+
+    ALIGNED_SYMBOL(4, _ext_ram_noinit_end)
+  } > extern_ram_seg
+#endif //CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
+
   .eh_frame_hdr :
   {
 #if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME

components/esp_system/ld/esp32p4/sections.ld.in

@@ -483,7 +483,7 @@ SECTIONS
   .ext_ram.dummy (NOLOAD):
   {
     . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start);
-    . = ALIGN (0x10000);
+    . = ALIGN (_esp_mmu_page_size);
   } > ext_ram_seg
 #endif  //CONFIG_SPIRAM_XIP_FROM_PSRAM
 

components/esp_system/ld/esp32s3/sections.ld.in

@@ -436,7 +436,7 @@ SECTIONS
   {
     . = ORIGIN(extern_ram_seg);
     . = . + (_rodata_reserved_end - _flash_rodata_dummy_start);
-    . = ALIGN (0x10000);
+    . = ALIGN (_esp_mmu_page_size);
   } > extern_ram_seg
 
 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY

components/soc/esp32c61/include/soc/clk_tree_defs.h

@@ -355,6 +355,7 @@ typedef enum {
     MSPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,           /*!< Select XTAL as the source clock */
     MSPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,     /*!< Select RC_FAST as the source clock */
     MSPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL,           /*!< Select SPLL as the source clock */
+    MSPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL,        /*!< Select PLL_F64M as the default clock choice */
     MSPI_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< Select XTAL as ROM default clock source */
 } soc_periph_mspi_clk_src_t;
 

docs/docs_not_updated/esp32c5.txt

@@ -34,7 +34,6 @@ api-guides/esp-ble-mesh/ble-mesh-feature-list.rst
 api-guides/esp-ble-mesh/ble-mesh-terminology.rst
 api-guides/esp-ble-mesh/ble-mesh-architecture.rst
 api-guides/esp-ble-mesh/ble-mesh-faq.rst
-api-guides/external-ram.rst
 api-guides/wifi-security.rst
 api-guides/openthread.rst
 third-party-tools/platformio.rst

docs/docs_not_updated/esp32c61.txt

@@ -44,7 +44,6 @@ api-guides/esp-ble-mesh/ble-mesh-feature-list.rst
 api-guides/esp-ble-mesh/ble-mesh-terminology.rst
 api-guides/esp-ble-mesh/ble-mesh-architecture.rst
 api-guides/esp-ble-mesh/ble-mesh-faq.rst
-api-guides/external-ram.rst
 api-guides/wifi-security.rst
 api-guides/index.rst
 api-guides/openthread.rst