kopia lustrzana https://github.com/espressif/esp-idf
fix(esp32s3): patch Cache_WriteBack_Addr api
Need to ensure that the cacheline being written back will not be accessed during the write back process.pull/12186/head
gaoxiaojie
rodzic
c739cdf50d
commit
25603522e8
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@ -30,6 +30,10 @@ if(target STREQUAL "esp32s2" OR target STREQUAL "esp32s3")
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list(APPEND sources "patches/esp_rom_cache.c")
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endif()
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if(target STREQUAL "esp32s3")
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list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S")
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endif()
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idf_component_register(SRCS ${sources}
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INCLUDE_DIRS ${include_dirs}
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PRIV_REQUIRES ${private_required_comp})
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@ -1,8 +1,10 @@
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COMPONENT_ADD_INCLUDEDIRS := include esp32 include/esp32
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COMPONENT_SRCDIRS := patches .
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COMPONENT_OBJEXCLUDE := patches/esp_rom_cache_writeback_esp32s3.o
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ifdef IS_BOOTLOADER_BUILD
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COMPONENT_OBJEXCLUDE := patches/esp_rom_longjmp.o
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COMPONENT_OBJEXCLUDE += patches/esp_rom_longjmp.o
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endif
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#Linker scripts used to link the final application.
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@ -25,3 +25,4 @@
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#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register
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#define ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG (1) // ROM api Cache_Count_Flash_Pages will return unexpected value
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#define ESP_ROM_HAS_CACHE_SUSPEND_WAITI_BUG (1) // ROM api Cache_Suspend_I/DCache and Cache_Freeze_I/DCache_Enable does not waiti
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#define ESP_ROM_HAS_CACHE_WRITEBACK_BUG (1) // ROM api Cache_WriteBack_Addr access cacheline being writen back may cause cache hit with wrong value.
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@ -381,7 +381,7 @@ PROVIDE( Cache_WriteBack_Items = 0x40001698 );
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PROVIDE( Cache_Op_Addr = 0x400016a4 );
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PROVIDE( Cache_Invalidate_Addr = 0x400016b0 );
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PROVIDE( Cache_Clean_Addr = 0x400016bc );
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PROVIDE( Cache_WriteBack_Addr = 0x400016c8 );
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PROVIDE( rom_Cache_WriteBack_Addr = 0x400016c8 );
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PROVIDE( Cache_Invalidate_ICache_All = 0x400016d4 );
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PROVIDE( Cache_Invalidate_DCache_All = 0x400016e0 );
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PROVIDE( Cache_Clean_All = 0x400016ec );
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@ -10,10 +10,14 @@
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#include "esp_attr.h"
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#include "esp_rom_caps.h"
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#include "soc/extmem_reg.h"
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#include "xtensa/xtruntime.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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#include "esp32s3/rom/cache.h"
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#endif
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#define ALIGN_UP(addr, align) (((addr) + (align)-1) & ~((align)-1))
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#define ALIGN_DOWN(addr, align) ((addr) & ~((align) - 1))
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// this api is renamed for patch
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extern uint32_t rom_Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
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IRAM_ATTR uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped)
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@ -83,4 +87,71 @@ IRAM_ATTR void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode)
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}
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extern void Cache_Freeze_DCache_Enable(cache_freeze_mode_t mode);
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#endif
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#if ESP_ROM_HAS_CACHE_WRITEBACK_BUG
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/* Defined in esp_rom_cache_writeback_esp32s3.S */
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extern void cache_writeback_items_freeze(uint32_t addr, uint32_t items);
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// renamed for patch
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extern int rom_Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
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IRAM_ATTR int Cache_WriteBack_Addr(uint32_t addr, uint32_t size)
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{
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/* Do special processing for unaligned memory at the start and end of the cache writeback memory.
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* 1. Disable the interrupt to prevent the current CPU accessing the same cacheline.
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* 2. Enable dcache freeze to prevent the another CPU accessing the same cacheline.
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*/
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uint32_t irq_status;
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uint32_t start_len, end_len;
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uint32_t start, end;
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uint32_t dcache_line_size;
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uint32_t autoload;
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int ret = 0;
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start = addr;
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end = addr + size;
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dcache_line_size = Cache_Get_DCache_Line_Size();
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if (size == 0) {
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return 0;
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}
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/*the start address is unaligned*/
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if (start & (dcache_line_size -1)) {
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addr = ALIGN_UP(start, dcache_line_size);
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start_len = addr - start;
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size = (size < start_len) ? 0 : (size - start_len);
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/*writeback start unaligned mem, one cacheline*/
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irq_status = XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);//mask all interrupts
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cache_writeback_items_freeze(start, 1);
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XTOS_RESTORE_INTLEVEL(irq_status);
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if (size == 0) {
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return 0;
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}
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}
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/*the end address is unaligned*/
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if (end & (dcache_line_size -1)) {
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end = ALIGN_DOWN(end, dcache_line_size);
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end_len = addr + size - end;
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size = (size - end_len);
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/*writeback end unaligned mem, one cacheline*/
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irq_status = XTOS_SET_INTLEVEL(XCHAL_NMILEVEL);//mask all interrupts
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cache_writeback_items_freeze(end, 1);
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XTOS_RESTORE_INTLEVEL(irq_status);
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if (size == 0) {
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return 0;
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}
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}
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/*suspend autoload, avoid load cachelines being written back*/
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autoload = Cache_Suspend_DCache_Autoload();
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ret = rom_Cache_WriteBack_Addr(addr, size);
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Cache_Resume_DCache_Autoload(autoload);
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return ret;
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}
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extern int Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
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#endif //ESP_ROM_HAS_CACHE_WRITEBACK_BUG
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#endif
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@ -0,0 +1,135 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "esp_bit_defs.h"
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#include "soc/extmem_reg.h"
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#if CONFIG_IDF_TARGET_ESP32S3
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/**
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* @brief Write back the cache items of DCache, enable cache freeze during writeback.
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* Operation will be done CACHE_LINE_SIZE aligned.
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* If the region is not in DCache addr room, nothing will be done.
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* Please do not call this function in your SDK application.
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* @param uint32_t addr: start address to write back
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* @param uint32_t items: cache lines to invalidate, items * cache_line_size should
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* not exceed the bus address size(4MB)
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*
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* void cache_writeback_items_freeze(uint32_t addr, uint32_t items)
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*/
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/*******************************************************************************
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This function is a cache write-back function that works around the following
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hardware errata on the ESP32-S3:
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- Core X manually triggers (via the EXTMEM_DCACHE_SYNC_CTRL_REG register) the
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write-back of one or more cache lines.
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- While the write-back is in progress, there are two scenarios that may cause
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cache hit error.
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- Core X enters the interrupt handler and access the same cache line
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being written back.
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- Core Y access the same cache line being written back.
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To workaround this errata, the following steps must be taken when manually
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triggering a cache write-back:
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- Core X must disable interrupts so that it cannot be preempted
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- Core X must freeze the cache (via the EXTMEM_DCACHE_FREEZE_REG register) to
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prevent Core Y from accessing the same cache lines that are about to be written
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back.
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- Core X now triggers the cache write-back. During the write-back...
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- If Core Y attempts the access any address in the cache region, Core Y will
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busy wait until the cache is unfrozen.
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- Core X must ensure that it does not access any address in the cache region,
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otherwise Core X will busy wait thus causing a deadlock.
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- After the write-back is complete, Core X unfreezes the cache, and reenables
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interrupts.
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Notes:
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- Please do not modify this function, it must strictly follow the current execution
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sequence, otherwise it may cause unexpected errors.
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- This function is written in assmebly to ensure that the function itself never
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accesses any cache address while the cache is frozen. Unexpected cache access
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could occur if...
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- the function triggers an window overflow onto a stack placed in PSRAM.
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Thus, we only use two window panes (a0 to a8) in this function and trigger
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all window overflows before freezing the cache.
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- the function accesses literals/read-only variables placed in Flash.
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*******************************************************************************/
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.section .iram1,"ax"
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.align 4
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/*
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Create dedicated literal pool for this function. Mostly used to store out
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of range movi transformations.
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*/
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.literal_position
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.global cache_writeback_items_freeze
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.type cache_writeback_items_freeze, @function
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cache_writeback_items_freeze:
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entry sp, 32
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/* REG_WRITE(EXTMEM_DCACHE_SYNC_ADDR_REG, addr); */
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movi a4, EXTMEM_DCACHE_SYNC_ADDR_REG
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s32i a2, a4, 0
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/* REG_WRITE(EXTMEM_DCACHE_SYNC_SIZE_REG, items); */
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movi a4, EXTMEM_DCACHE_SYNC_SIZE_REG
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s32i a3, a4, 0
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memw /* About to freeze the cache. Ensure all previous memory R/W are completed */
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movi a2, EXTMEM_DCACHE_FREEZE_REG
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movi a3, EXTMEM_DCACHE_SYNC_CTRL_REG
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/*
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REG_CLR_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_MODE);
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REG_SET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_ENA);
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*/
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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movi a5, ~(EXTMEM_DCACHE_FREEZE_MODE_M)
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and a4, a4, a5
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movi a5, EXTMEM_DCACHE_FREEZE_ENA_M
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or a4, a4, a5
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s32i a4, a2, 0 /* *(EXTMEM_DCACHE_FREEZE_REG) = a4 */
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/* while (!REG_GET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_DONE)); */
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movi a5, EXTMEM_DCACHE_FREEZE_DONE_M
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_wait_freeze_done:
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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memw
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bnone a4, a5, _wait_freeze_done
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/* REG_SET_BIT(EXTMEM_DCACHE_SYNC_CTRL_REG, EXTMEM_DCACHE_WRITEBACK_ENA); */
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l32i a4, a3, 0 /* a4 = *(EXTMEM_DCACHE_SYNC_CTRL_REG) */
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movi a5, EXTMEM_DCACHE_WRITEBACK_ENA_M
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or a4, a4, a5
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s32i a4, a3, 0 /* *(EXTMEM_DCACHE_SYNC_CTRL_REG) = a4 */
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/* while(!REG_GET_BIT(EXTMEM_DCACHE_SYNC_CTRL_REG, EXTMEM_DCACHE_SYNC_DONE)); */
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movi a5, EXTMEM_DCACHE_SYNC_DONE_M
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_wait_writeback_done:
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l32i a4, a3, 0 /* a4 = *(EXTMEM_DCACHE_SYNC_CTRL_REG) */
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memw
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bnone a4, a5, _wait_writeback_done
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/* REG_CLR_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_ENA); */
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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movi a5, ~(EXTMEM_DCACHE_FREEZE_ENA_M)
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and a4, a4, a5
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s32i a4, a2, 0 /* *(EXTMEM_DCACHE_FREEZE_REG) = a4 */
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/* while (REG_GET_BIT(EXTMEM_DCACHE_FREEZE_REG, EXTMEM_DCACHE_FREEZE_DONE)); */
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movi a5, EXTMEM_DCACHE_FREEZE_DONE_M
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_wait_unfreeze_done:
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l32i a4, a2, 0 /* a4 = *(EXTMEM_DCACHE_FREEZE_REG) */
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memw
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bany a4, a5, _wait_unfreeze_done
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retw
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.size cache_writeback_items_freeze, . - cache_writeback_items_freeze
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#endif /* CONFIG_IDF_TARGET_ESP32S3 */
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