From f4f45345ee554acc2c97c57c3a380d4011ccfe4f Mon Sep 17 00:00:00 2001 From: Jakob Hasse Date: Tue, 30 May 2023 12:15:48 +0800 Subject: [PATCH] esp_hw_support: decrease RNG read frequency on C6 and H2 * The RNG reading frequency of 200 KHz has been too high for C6 and H2 since on these chips the RNG output is combined with the RTC slow clock which is only 150KHz. Reduced the max reading frequency via esp_random() from 200KHz to 62.5KHz, which show best results in tests. Also updated the bootloader_fill_random() max frequency to the same value to be in line, even though it was just 83KHz. --- .../bootloader_support/src/bootloader_random.c | 3 ++- components/esp_hw_support/hw_random.c | 12 ++++++------ 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/components/bootloader_support/src/bootloader_random.c b/components/bootloader_support/src/bootloader_random.c index c3abdcc92a..4bc121450e 100644 --- a/components/bootloader_support/src/bootloader_random.c +++ b/components/bootloader_support/src/bootloader_random.c @@ -25,7 +25,8 @@ #if !defined CONFIG_IDF_TARGET_ESP32S3 #if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2) - #define RNG_CPU_WAIT_CYCLE_NUM (80 * 12) // higher frequency because we are reading bytes instead of words + #define RNG_CPU_WAIT_CYCLE_NUM (80 * 16) // Keep the byte sampling frequency in the ~62KHz range which has been + // tested. #else #define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */ #endif diff --git a/components/esp_hw_support/hw_random.c b/components/esp_hw_support/hw_random.c index a05cc49094..fa83bfc0d9 100644 --- a/components/esp_hw_support/hw_random.c +++ b/components/esp_hw_support/hw_random.c @@ -19,16 +19,16 @@ #endif #if defined CONFIG_IDF_TARGET_ESP32S3 -#define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, maximum sampling frequency is around 45 KHz*/ +#define APB_CYCLE_WAIT_NUM (1778) /* If APB clock is 80 MHz, the maximum sampling frequency is around 45 KHz*/ /* 45 KHz reading frequency is the maximum we have tested so far on S3 */ #elif defined CONFIG_IDF_TARGET_ESP32C6 -#define APB_CYCLE_WAIT_NUM (160 * 5) /* We want to have a maximum sampling frequency below 50KHz for - * 32-bit samples. But on ESP32C6, we only read one byte at a time, - * hence, the wait time is 4 times lower. The current value translates - * to a sampling frequency of 50 KHz for reading 32 bit samples, +#define APB_CYCLE_WAIT_NUM (160 * 16) /* On ESP32C6, we only read one byte at a time, then XOR the value with + * an asynchronous timer (see code below). + * The current value translates to a sampling frequency of around 62.5 KHz + * for reading 8 bit samples, which is the rate at which the RNG was tested, * plus additional overhead for the calculation, making it slower. */ #elif defined CONFIG_IDF_TARGET_ESP32H2 -#define APB_CYCLE_WAIT_NUM (160 * 3) /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is +#define APB_CYCLE_WAIT_NUM (96 * 16) /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is * 96MHz instead of 160 MHz */ #else #define APB_CYCLE_WAIT_NUM (16)