kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'feature/unicore_bootloader_can_run_multicore_app_v4.4' into 'release/v4.4'
esp_system: Fix case when multicore app can not be run if bootloader is unicore (v4.4) See merge request espressif/esp-idf!23029pull/12186/head
commit
2183fbc046
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@ -374,6 +374,12 @@ test_app_test_005:
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- ESP32C3
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- Example_GENERIC
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test_app_test_006:
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extends: .test_app_esp32s3_template
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tags:
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- ESP32S3
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- Example_GENERIC
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test_app_test_esp32_generic:
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extends: .test_app_esp32_template
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parallel: 5
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@ -94,4 +94,12 @@ void bootloader_print_banner(void)
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{
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ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER);
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ESP_LOGI(TAG, "compile time " __TIME__);
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#if CONFIG_FREERTOS_UNICORE
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#if (SOC_CPU_CORES_NUM > 1)
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ESP_EARLY_LOGW(TAG, "Unicore bootloader");
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#endif
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#else
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ESP_EARLY_LOGI(TAG, "Multicore bootloader");
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#endif
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}
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@ -70,6 +70,10 @@
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#include "hal/wdt_hal.h"
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#include "soc/rtc.h"
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#include "soc/efuse_reg.h"
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#if (SOC_CPU_CORES_NUM > 1)
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#include "hal/cache_ll.h"
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#endif
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#include "hal/efuse_ll.h"
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#include "soc/periph_defs.h"
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#include "soc/cpu.h"
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#include "soc/rtc.h"
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@ -244,6 +248,39 @@ static void start_other_core(void)
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esp_rom_delay_us(100);
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}
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}
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// This function is needed to make the multicore app runnable on a unicore bootloader (built with FREERTOS UNICORE).
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// It does some cache settings for other CPUs.
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void IRAM_ATTR do_multicore_settings(void)
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{
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// We intentionally do not check the cache settings before changing them,
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// because it helps to get the application to run on older bootloaders.
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#ifdef CONFIG_IDF_TARGET_ESP32
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if (!efuse_ll_get_disable_app_cpu()) {
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Cache_Read_Disable(1);
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Cache_Flush(1);
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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// We do not enable cache for CPU1 now because it will be done later in start_other_core().
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}
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#endif
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cache_bus_mask_t cache_bus_mask_core0 = cache_ll_l1_get_enabled_bus(0);
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#ifndef CONFIG_IDF_TARGET_ESP32
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// 1. disable the cache before changing its settings.
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Cache_Disable_ICache();
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Cache_Disable_DCache();
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#endif
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for (unsigned core = 1; core < SOC_CPU_CORES_NUM; core++) {
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// 2. change cache settings. All cores must have the same settings.
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cache_ll_l1_enable_bus(core, cache_bus_mask_core0);
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}
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#ifndef CONFIG_IDF_TARGET_ESP32
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// 3. enable the cache after changing its settings.
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Cache_Enable_ICache(0);
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Cache_Enable_DCache(0);
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#endif
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}
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#endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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/*
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@ -312,6 +349,14 @@ void IRAM_ATTR call_start_cpu0(void)
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memset(&_rtc_bss_start, 0, (&_rtc_bss_end - &_rtc_bss_start) * sizeof(_rtc_bss_start));
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}
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#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
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ESP_EARLY_LOGI(TAG, "Unicore app");
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#else
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ESP_EARLY_LOGI(TAG, "Multicore app");
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// It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
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do_multicore_settings();
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#endif
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#if CONFIG_IDF_TARGET_ESP32S2
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/* Configure the mode of instruction cache : cache size, cache associated ways, cache line size. */
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extern void esp_config_instruction_cache_mode(void);
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@ -0,0 +1,127 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/dport_reg.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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/**
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* Returns enabled buses for a given core
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return State of enabled buses
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*/
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__attribute__((always_inline))
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static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
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{
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cache_bus_mask_t mask = 0;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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if (cache_id == 0) {
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uint32_t bus_mask= DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG);
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
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mask |= (!(bus_mask & DPORT_PRO_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
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} else {
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uint32_t bus_mask= DPORT_REG_READ(DPORT_APP_CACHE_CTRL1_REG);
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM0)) ? CACHE_BUS_IBUS0 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IRAM1)) ? CACHE_BUS_IBUS1 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_IROM0)) ? CACHE_BUS_IBUS2 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DROM0)) ? CACHE_BUS_DBUS0 : 0;
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mask |= (!(bus_mask & DPORT_APP_CACHE_MASK_DRAM1)) ? CACHE_BUS_DBUS1 : 0;
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}
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return mask;
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}
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_PRO_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_PRO_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_SET_BIT(DPORT_PRO_CACHE_CTRL1_REG, bus_mask);
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} else {
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bus_mask |= (mask & CACHE_BUS_IBUS0) ? DPORT_APP_CACHE_MASK_IRAM0 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS1) ? DPORT_APP_CACHE_MASK_IRAM1 : 0;
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bus_mask |= (mask & CACHE_BUS_IBUS2) ? DPORT_APP_CACHE_MASK_IROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS0) ? DPORT_APP_CACHE_MASK_DROM0 : 0;
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bus_mask |= (mask & CACHE_BUS_DBUS1) ? DPORT_APP_CACHE_MASK_DRAM1 : 0;
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, bus_mask);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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@ -0,0 +1,115 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include "soc/extmem_reg.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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if (cache_id == 0) {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
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} else {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
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}
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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if (cache_id == 1) {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
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} else {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
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}
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REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
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}
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/**
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* Returns enabled buses for a given core
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return State of enabled buses
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*/
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__attribute__((always_inline))
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static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
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{
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cache_bus_mask_t mask = 0;
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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uint32_t ibus_mask = REG_READ(EXTMEM_ICACHE_CTRL1_REG);
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if (cache_id == 0) {
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mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_IBUS0 : 0;
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} else {
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mask |= (!(ibus_mask & EXTMEM_ICACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_IBUS0 : 0;
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}
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uint32_t dbus_mask = REG_READ(EXTMEM_DCACHE_CTRL1_REG);
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if (cache_id == 1) {
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mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE0_BUS)) ? CACHE_BUS_DBUS0 : 0;
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} else {
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mask |= (!(dbus_mask & EXTMEM_DCACHE_SHUT_CORE1_BUS)) ? CACHE_BUS_DBUS0 : 0;
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}
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return mask;
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}
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|
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/**
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* Disable the Cache Buses
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*
|
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* @param cache_id cache ID (when l1 cache is per core)
|
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* @param mask To know which buses should be disabled
|
||||
*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0 || cache_id == 1);
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//On esp32s3, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
|
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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if (cache_id == 0) {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE0_BUS : 0;
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} else {
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_CORE1_BUS : 0;
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}
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REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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if (cache_id == 1) {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE0_BUS : 0;
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} else {
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_DCACHE_SHUT_CORE1_BUS : 0;
|
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}
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REG_SET_BIT(EXTMEM_DCACHE_CTRL1_REG, dbus_mask);
|
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}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Ibuses and Dbuses.
|
||||
*
|
||||
* @note
|
||||
* These enumurations are abstract concepts. Virtual address reside in one of these buses.
|
||||
* Therefore, use `cache_ll_l1_get_bus(cache_id, vaddr_start, len)` to convert your vaddr into buses first
|
||||
*/
|
||||
typedef enum {
|
||||
CACHE_BUS_IBUS0 = BIT(0),
|
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CACHE_BUS_IBUS1 = BIT(1),
|
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CACHE_BUS_IBUS2 = BIT(2),
|
||||
CACHE_BUS_DBUS0 = BIT(3),
|
||||
CACHE_BUS_DBUS1 = BIT(4),
|
||||
CACHE_BUS_DBUS2 = BIT(5),
|
||||
} cache_bus_mask_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
|
@ -391,13 +391,14 @@ class IDFDUT(DUT.SerialDUT):
|
|||
for (_, f) in encrypt_offs_files:
|
||||
f.close()
|
||||
|
||||
def bootloader_flash(self):
|
||||
def bootloader_flash(self, binary_path=None):
|
||||
"""
|
||||
download bootloader.
|
||||
|
||||
:return: None
|
||||
"""
|
||||
bootloader_path = os.path.join(self.app.binary_path, 'bootloader', 'bootloader.bin')
|
||||
binary_path = self.app.binary_path if binary_path is None else binary_path
|
||||
bootloader_path = os.path.join(binary_path, 'bootloader', 'bootloader.bin')
|
||||
offs = int(self.app.get_sdkconfig()['CONFIG_BOOTLOADER_OFFSET_IN_FLASH'], 0)
|
||||
flash_files = [(offs, bootloader_path)]
|
||||
self.write_flash(flash_files)
|
||||
|
|
|
@ -0,0 +1,6 @@
|
|||
# The following lines of boilerplate have to be in your project's
|
||||
# CMakeLists in this exact order for cmake to work correctly
|
||||
cmake_minimum_required(VERSION 3.5)
|
||||
|
||||
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
|
||||
project(test_unicore_bootloader)
|
|
@ -0,0 +1,2 @@
|
|||
| Supported Targets | ESP32 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- |
|
|
@ -0,0 +1,4 @@
|
|||
This project tests if the app can start up in a certain configuration.
|
||||
Multicore app can start up even if the bootloader is unicore.
|
||||
|
||||
The test is only for Multicore chips.
|
|
@ -0,0 +1,42 @@
|
|||
#!/usr/bin/env python
|
||||
|
||||
from typing import Any
|
||||
|
||||
import ttfw_idf
|
||||
|
||||
|
||||
@ttfw_idf.idf_custom_test(env_tag='Example_GENERIC', group='test-apps', target=['esp32', 'esp32s3'])
|
||||
def test_multicore_app_and_unicore_bootloader(env, _): # type: (Any, Any) -> None
|
||||
dut = env.get_dut('unicore_bootloader', 'tools/test_apps/system/unicore_bootloader', app_config_name='multicore_cfg')
|
||||
dut.start_app()
|
||||
dut.expect('Multicore bootloader')
|
||||
dut.expect('Multicore app')
|
||||
dut.expect('App is running')
|
||||
env.close_dut(dut.name)
|
||||
|
||||
dut = env.get_dut('unicore_bootloader', 'tools/test_apps/system/unicore_bootloader', app_config_name='unicore_cfg')
|
||||
dut.bootloader_flash()
|
||||
dut.expect('Unicore bootloader')
|
||||
dut.expect('Multicore app')
|
||||
dut.expect('App is running')
|
||||
|
||||
|
||||
@ttfw_idf.idf_custom_test(env_tag='Example_GENERIC', group='test-apps', target=['esp32', 'esp32s3'])
|
||||
def test_unicore_app_and_multicore_bootloader(env, _): # type: (Any, Any) -> None
|
||||
dut = env.get_dut('unicore_bootloader', 'tools/test_apps/system/unicore_bootloader', app_config_name='unicore_cfg')
|
||||
dut.start_app()
|
||||
dut.expect('Unicore bootloader')
|
||||
dut.expect('Unicore app')
|
||||
dut.expect('App is running')
|
||||
env.close_dut(dut.name)
|
||||
|
||||
dut = env.get_dut('unicore_bootloader', 'tools/test_apps/system/unicore_bootloader', app_config_name='multicore_cfg')
|
||||
dut.bootloader_flash()
|
||||
dut.expect('Multicore bootloader')
|
||||
dut.expect('Unicore app')
|
||||
dut.expect('App is running')
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
test_multicore_app_and_unicore_bootloader()
|
||||
test_unicore_app_and_multicore_bootloader()
|
|
@ -0,0 +1 @@
|
|||
idf_component_register(SRCS "main.c")
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
void app_main(void)
|
||||
{
|
||||
printf("App is running\n");
|
||||
}
|
|
@ -0,0 +1 @@
|
|||
CONFIG_FREERTOS_UNICORE=y
|
Ładowanie…
Reference in New Issue