diff --git a/components/ulp/lp_core/include/lp_core_i2c.h b/components/ulp/lp_core/include/lp_core_i2c.h index 8350adcaef..90c34d4d8d 100644 --- a/components/ulp/lp_core/include/lp_core_i2c.h +++ b/components/ulp/lp_core/include/lp_core_i2c.h @@ -26,7 +26,6 @@ typedef struct { bool scl_pullup_en; /*!< SCL line enable internal pullup. Can be configured if external pullup is not used. */ } lp_core_i2c_pin_cfg_t; - /** * @brief LP Core I2C timing config parameters */ @@ -34,7 +33,6 @@ typedef struct { uint32_t clk_speed_hz; /*!< LP I2C clock speed for master mode */ } lp_core_i2c_timing_cfg_t; - /** * @brief LP Core I2C config parameters */ diff --git a/components/ulp/lp_core/include/ulp_lp_core.h b/components/ulp/lp_core/include/ulp_lp_core.h index 106f6b97c4..8931f80890 100644 --- a/components/ulp/lp_core/include/ulp_lp_core.h +++ b/components/ulp/lp_core/include/ulp_lp_core.h @@ -15,7 +15,6 @@ extern "C" { #endif - #define ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU BIT(0) // Started by HP core (1 single wakeup) #define ULP_LP_CORE_WAKEUP_SOURCE_LP_UART BIT(1) // Enable wake-up by a certain number of LP UART RX pulses #define ULP_LP_CORE_WAKEUP_SOURCE_LP_IO BIT(2) // Enable wake-up by LP IO interrupt diff --git a/components/ulp/lp_core/lp_core.c b/components/ulp/lp_core/lp_core.c index 08bffc7be7..54d7c3a483 100644 --- a/components/ulp/lp_core/lp_core.c +++ b/components/ulp/lp_core/lp_core.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,7 +40,7 @@ static uint32_t wakeup_src_sw_to_hw_flag_lookup[WAKEUP_SOURCE_MAX_NUMBER] = { static uint32_t lp_core_get_wakeup_source_hw_flags(uint32_t flags) { uint32_t hw_flags = 0; - for(int i = 0; i < WAKEUP_SOURCE_MAX_NUMBER; i++) { + for (int i = 0; i < WAKEUP_SOURCE_MAX_NUMBER; i++) { if (flags & (1 << i)) { hw_flags |= wakeup_src_sw_to_hw_flag_lookup[i]; } @@ -99,12 +99,11 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg) ulp_lp_core_lp_timer_set_wakeup_time(cfg->lp_timer_sleep_duration_us); } - if (cfg->wakeup_source & (ULP_LP_CORE_WAKEUP_SOURCE_LP_UART | ULP_LP_CORE_WAKEUP_SOURCE_LP_IO | ULP_LP_CORE_WAKEUP_SOURCE_ETM )) { + if (cfg->wakeup_source & (ULP_LP_CORE_WAKEUP_SOURCE_LP_UART | ULP_LP_CORE_WAKEUP_SOURCE_LP_IO | ULP_LP_CORE_WAKEUP_SOURCE_ETM)) { ESP_LOGE(TAG, "Wake-up source not yet supported"); return ESP_ERR_INVALID_ARG; } - return ESP_OK; } @@ -129,7 +128,6 @@ esp_err_t ulp_lp_core_load_binary(const uint8_t* program_binary, size_t program_ return ESP_OK; } - void ulp_lp_core_stop(void) { /* Disable wake-up source and put lp core to sleep */ diff --git a/components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h b/components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h index 85ac81cf00..42745dc186 100644 --- a/components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h +++ b/components/ulp/lp_core/lp_core/include/ulp_lp_core_gpio.h @@ -117,7 +117,7 @@ static inline void ulp_lp_core_gpio_set_output_mode(lp_io_num_t lp_io_num, rtcio static inline void ulp_lp_core_gpio_pullup_enable(lp_io_num_t lp_io_num) { /* Enable internal weak pull-up */ - rtcio_ll_pullup_enable(lp_io_num); + rtcio_ll_pullup_enable(lp_io_num); } /** diff --git a/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h b/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h index c539bde255..a98f5ebb1a 100644 --- a/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h +++ b/components/ulp/lp_core/lp_core/include/ulp_lp_core_i2c.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -33,8 +33,8 @@ extern "C" { * @note the LP I2C port number is ignored at the moment. */ esp_err_t lp_core_i2c_master_read_from_device(i2c_port_t lp_i2c_num, uint16_t device_addr, - uint8_t *data_rd, size_t size, - int32_t ticks_to_wait); + uint8_t *data_rd, size_t size, + int32_t ticks_to_wait); /** * @brief Write to I2C device @@ -54,8 +54,8 @@ esp_err_t lp_core_i2c_master_read_from_device(i2c_port_t lp_i2c_num, uint16_t de * @note the LP I2C port number is ignored at the moment. */ esp_err_t lp_core_i2c_master_write_to_device(i2c_port_t lp_i2c_num, uint16_t device_addr, - const uint8_t *data_wr, size_t size, - int32_t ticks_to_wait); + const uint8_t *data_wr, size_t size, + int32_t ticks_to_wait); /** * @brief Write to and then read from an I2C device in a single transaction @@ -77,9 +77,9 @@ esp_err_t lp_core_i2c_master_write_to_device(i2c_port_t lp_i2c_num, uint16_t dev * @note the LP I2C port number is ignored at the moment. */ esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t device_addr, - const uint8_t *data_wr, size_t write_size, - uint8_t *data_rd, size_t read_size, - int32_t ticks_to_wait); + const uint8_t *data_wr, size_t write_size, + uint8_t *data_rd, size_t read_size, + int32_t ticks_to_wait); /** * @brief Enable or disable ACK checking by the LP_I2C controller during write operations diff --git a/components/ulp/lp_core/lp_core/lp_core_i2c.c b/components/ulp/lp_core/lp_core/lp_core_i2c.c index f0ed013472..fa1b348fd7 100644 --- a/components/ulp/lp_core/lp_core/lp_core_i2c.c +++ b/components/ulp/lp_core/lp_core/lp_core_i2c.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -37,7 +37,7 @@ static bool s_ack_check_en = true; * |----------|----------|---------|---------|----------|------------|---------| */ static void lp_core_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t ack_val, - uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num) + uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num) { if (cmd_idx >= sizeof(dev->command)) { /* We only have limited HW command registers. @@ -51,12 +51,12 @@ static void lp_core_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t ac .done = 0, // CMD Done .op_code = op_code, // Opcode .ack_val = ack_val, // ACK bit sent by I2C controller during READ. - // Ignored during RSTART, STOP, END and WRITE cmds. + // Ignored during RSTART, STOP, END and WRITE cmds. .ack_exp = ack_expected, // ACK bit expected by I2C controller during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. + // Ignored during RSTART, STOP, END and READ cmds. .ack_en = ack_check_en, // I2C controller verifies that the ACK bit sent by the - // slave device matches the ACK expected bit during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. + // slave device matches the ACK expected bit during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. .byte_num = byte_num, // Byte Num }; @@ -142,8 +142,8 @@ void lp_core_i2c_master_set_ack_check_en(i2c_port_t lp_i2c_num, bool ack_check_e } esp_err_t lp_core_i2c_master_read_from_device(i2c_port_t lp_i2c_num, uint16_t device_addr, - uint8_t *data_rd, size_t size, - int32_t ticks_to_wait) + uint8_t *data_rd, size_t size, + int32_t ticks_to_wait) { (void)lp_i2c_num; @@ -233,8 +233,8 @@ esp_err_t lp_core_i2c_master_read_from_device(i2c_port_t lp_i2c_num, uint16_t de } esp_err_t lp_core_i2c_master_write_to_device(i2c_port_t lp_i2c_num, uint16_t device_addr, - const uint8_t *data_wr, size_t size, - int32_t ticks_to_wait) + const uint8_t *data_wr, size_t size, + int32_t ticks_to_wait) { (void)lp_i2c_num; @@ -324,9 +324,9 @@ esp_err_t lp_core_i2c_master_write_to_device(i2c_port_t lp_i2c_num, uint16_t dev } esp_err_t lp_core_i2c_master_write_read_device(i2c_port_t lp_i2c_num, uint16_t device_addr, - const uint8_t *data_wr, size_t write_size, - uint8_t *data_rd, size_t read_size, - int32_t ticks_to_wait) + const uint8_t *data_wr, size_t write_size, + uint8_t *data_rd, size_t read_size, + int32_t ticks_to_wait) { (void)lp_i2c_num; diff --git a/components/ulp/lp_core/lp_core/lp_core_print.c b/components/ulp/lp_core/lp_core/lp_core_print.c index ca6cd9d19e..d010f68328 100644 --- a/components/ulp/lp_core/lp_core/lp_core_print.c +++ b/components/ulp/lp_core/lp_core/lp_core_print.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -103,115 +103,117 @@ static int lp_core_ets_vprintf(void (*putc)(char c), const char *fmt, va_list ap } } switch (c) { - case 'p': - islong = 1; - case 'd': - case 'D': - case 'x': - case 'X': - case 'u': - case 'U': + case 'p': + islong = 1; + case 'd': + case 'D': + case 'x': + case 'X': + case 'u': + case 'U': #ifdef BINARY_SUPPORT - case 'b': - case 'B': + case 'b': + case 'B': #endif - if (islonglong) { - val = va_arg(ap, long long); - } else if (islong) { - val = (long long)va_arg(ap, long); - } else { - val = (long long)va_arg(ap, int); - } + if (islonglong) { + val = va_arg(ap, long long); + } else if (islong) { + val = (long long)va_arg(ap, long); + } else { + val = (long long)va_arg(ap, int); + } - if ((c == 'd') || (c == 'D')) { - if (val < 0) { - sign = '-'; - val = -val; - } - } else { - if (islonglong) { - ; - } else if (islong) { - val &= ((long long)1 << (sizeof(long) * 8)) - 1; - } else { - val &= ((long long)1 << (sizeof(int) * 8)) - 1; - } + if ((c == 'd') || (c == 'D')) { + if (val < 0) { + sign = '-'; + val = -val; } - break; - default: - break; + } else { + if (islonglong) { + ; + } else if (islong) { + val &= ((long long)1 << (sizeof(long) * 8)) - 1; + } else { + val &= ((long long)1 << (sizeof(int) * 8)) - 1; + } + } + break; + default: + break; } switch (c) { - case 'p': - (*putc)('0'); - (*putc)('x'); - zero_fill = true; - left_prec = sizeof(unsigned long) * 2; + case 'p': + (*putc)('0'); + (*putc)('x'); + zero_fill = true; + left_prec = sizeof(unsigned long) * 2; + case 'd': + case 'D': + case 'u': + case 'U': + case 'x': + case 'X': + switch (c) { case 'd': case 'D': case 'u': case 'U': + length = lp_core_cvt(val, buf, 10, "0123456789"); + break; + case 'p': case 'x': + length = lp_core_cvt(val, buf, 16, "0123456789abcdef"); + break; case 'X': - switch (c) { - case 'd': - case 'D': - case 'u': - case 'U': - length = lp_core_cvt(val, buf, 10, "0123456789"); - break; - case 'p': - case 'x': - length = lp_core_cvt(val, buf, 16, "0123456789abcdef"); - break; - case 'X': - length = lp_core_cvt(val, buf, 16, "0123456789ABCDEF"); - break; - } - cp = buf; + length = lp_core_cvt(val, buf, 16, "0123456789ABCDEF"); break; - case 's': - case 'S': - cp = va_arg(ap, char *); - if (cp == NULL) { - cp = ""; - } - length = 0; - while (cp[length] != '\0') - length++; - break; - case 'c': - case 'C': - c = va_arg(ap, int /*char*/); - (*putc)(c); - res++; - continue; + } + cp = buf; + break; + case 's': + case 'S': + cp = va_arg(ap, char *); + if (cp == NULL) { + cp = ""; + } + length = 0; + while (cp[length] != '\0') { + length++; + } + break; + case 'c': + case 'C': + c = va_arg(ap, int /*char*/); + (*putc)(c); + res++; + continue; #ifdef BINARY_SUPPORT - case 'b': - case 'B': - length = left_prec; - if (left_prec == 0) { - if (islonglong) - length = sizeof(long long) * 8; - else if (islong) - length = sizeof(long) * 8; - else - length = sizeof(int) * 8; + case 'b': + case 'B': + length = left_prec; + if (left_prec == 0) { + if (islonglong) { + length = sizeof(long long) * 8; + } else if (islong) { + length = sizeof(long) * 8; + } else { + length = sizeof(int) * 8; } - for (int i = 0; i < length - 1; i++) { - buf[i] = ((val & ((long long)1 << i)) ? '1' : '.'); - } - cp = buf; - break; + } + for (int i = 0; i < length - 1; i++) { + buf[i] = ((val & ((long long)1 << i)) ? '1' : '.'); + } + cp = buf; + break; #endif - case '%': - (*putc)('%'); - break; - default: - (*putc)('%'); - (*putc)(c); - res += 2; + case '%': + (*putc)('%'); + break; + default: + (*putc)('%'); + (*putc)(c); + res += 2; } pad = left_prec - length; if (sign != '\0') { diff --git a/components/ulp/lp_core/lp_core/lp_core_startup.c b/components/ulp/lp_core/lp_core/lp_core_startup.c index a5cf8855b9..b7cc5e6b51 100644 --- a/components/ulp/lp_core/lp_core/lp_core_startup.c +++ b/components/ulp/lp_core/lp_core/lp_core_startup.c @@ -7,10 +7,8 @@ #include "ulp_lp_core_lp_timer_shared.h" #include "ulp_lp_core_memory_shared.h" - extern void main(); - /* Initialize lp core related system functions before calling user's main*/ void lp_core_startup() { diff --git a/components/ulp/lp_core/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core/lp_core_uart.c index fa00f7aa4e..ef20026587 100644 --- a/components/ulp/lp_core/lp_core/lp_core_uart.c +++ b/components/ulp/lp_core/lp_core/lp_core_uart.c @@ -182,7 +182,7 @@ int lp_core_uart_read_bytes(uart_port_t lp_uart_num, void *buf, size_t size, int /* We have some data to read from the Rx FIFO. Check Rx interrupt status */ intr_status = uart_hal_get_intsts_mask(&hal); if ((intr_status & UART_INTR_RXFIFO_FULL) || - (intr_status & UART_INTR_RXFIFO_TOUT)) { + (intr_status & UART_INTR_RXFIFO_TOUT)) { /* This is expected. Clear interrupt status and break */ uart_hal_clr_intsts_mask(&hal, intr_mask); break; diff --git a/components/ulp/lp_core/lp_core/lp_core_utils.c b/components/ulp/lp_core/lp_core/lp_core_utils.c index 5ed302ba31..e08ffdcf87 100644 --- a/components/ulp/lp_core/lp_core/lp_core_utils.c +++ b/components/ulp/lp_core/lp_core/lp_core_utils.c @@ -1,10 +1,9 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ - #include #include "riscv/csr.h" #include "soc/soc.h" @@ -29,31 +28,31 @@ static uint32_t lp_wakeup_cause = 0; void ulp_lp_core_update_wakeup_cause(void) { if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_HP_CPU) \ - && (pmu_ll_lp_get_interrupt_raw(&PMU) & PMU_HP_SW_TRIGGER_INT_RAW)) { + && (pmu_ll_lp_get_interrupt_raw(&PMU) & PMU_HP_SW_TRIGGER_INT_RAW)) { lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_HP_CPU; pmu_ll_lp_clear_intsts_mask(&PMU, PMU_HP_SW_TRIGGER_INT_CLR); } if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_UART) \ - && (uart_ll_get_intraw_mask(&LP_UART) & LP_UART_WAKEUP_INT_RAW)) { + && (uart_ll_get_intraw_mask(&LP_UART) & LP_UART_WAKEUP_INT_RAW)) { lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_UART; uart_ll_clr_intsts_mask(&LP_UART, LP_UART_WAKEUP_INT_CLR); } if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_IO) \ - && rtcio_ll_get_interrupt_status()) { + && rtcio_ll_get_interrupt_status()) { lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_IO; rtcio_ll_clear_interrupt_status(); } if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_ETM) \ - && etm_ll_is_lpcore_wakeup_triggered()) { + && etm_ll_is_lpcore_wakeup_triggered()) { lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_ETM; etm_ll_clear_lpcore_wakeup_status(); } if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER) \ - && (lp_timer_ll_get_lp_intr_raw(&LP_TIMER) & LP_TIMER_MAIN_TIMER_LP_INT_RAW)) { + && (lp_timer_ll_get_lp_intr_raw(&LP_TIMER) & LP_TIMER_MAIN_TIMER_LP_INT_RAW)) { lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER; lp_timer_ll_clear_lp_intsts_mask(&LP_TIMER, LP_TIMER_MAIN_TIMER_LP_INT_CLR); } @@ -77,7 +76,6 @@ void ulp_lp_core_wakeup_main_processor(void) REG_SET_FIELD(PMU_HP_LP_CPU_COMM_REG, PMU_LP_TRIGGER_HP, 1); } - /** * @brief Makes the co-processor busy wait for a certain number of microseconds * @@ -112,7 +110,7 @@ void ulp_lp_core_halt(void) { REG_SET_FIELD(PMU_LP_CPU_PWR1_REG, PMU_LP_CPU_SLEEP_REQ, 1); - while(1); + while (1); } void ulp_lp_core_stop_lp_core(void) diff --git a/components/ulp/lp_core/lp_core_uart.c b/components/ulp/lp_core/lp_core_uart.c index eba6bbc2d5..7ab414ec16 100644 --- a/components/ulp/lp_core/lp_core_uart.c +++ b/components/ulp/lp_core/lp_core_uart.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -29,8 +29,8 @@ static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg) /* Argument sanity check */ if ((cfg->uart_proto_cfg.rx_flow_ctrl_thresh > SOC_LP_UART_FIFO_LEN) || - (cfg->uart_proto_cfg.flow_ctrl > UART_HW_FLOWCTRL_MAX) || - (cfg->uart_proto_cfg.data_bits > UART_DATA_BITS_MAX)) { + (cfg->uart_proto_cfg.flow_ctrl > UART_HW_FLOWCTRL_MAX) || + (cfg->uart_proto_cfg.data_bits > UART_DATA_BITS_MAX)) { // Invalid config return ESP_ERR_INVALID_ARG; } @@ -93,9 +93,9 @@ static esp_err_t lp_core_uart_set_pin(const lp_core_uart_cfg_t *cfg) /* Argument sanity check */ if ((cfg->uart_pin_cfg.tx_io_num != GPIO_NUM_5) || - (cfg->uart_pin_cfg.rx_io_num != GPIO_NUM_4) || - (cfg->uart_pin_cfg.rts_io_num != GPIO_NUM_2) || - (cfg->uart_pin_cfg.cts_io_num != GPIO_NUM_3)) { + (cfg->uart_pin_cfg.rx_io_num != GPIO_NUM_4) || + (cfg->uart_pin_cfg.rts_io_num != GPIO_NUM_2) || + (cfg->uart_pin_cfg.cts_io_num != GPIO_NUM_3)) { // Invalid IO config return ESP_ERR_INVALID_ARG; } diff --git a/components/ulp/lp_core/shared/include/ulp_lp_core_lp_timer_shared.h b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_timer_shared.h index 522965ff83..284e8d3904 100644 --- a/components/ulp/lp_core/shared/include/ulp_lp_core_lp_timer_shared.h +++ b/components/ulp/lp_core/shared/include/ulp_lp_core_lp_timer_shared.h @@ -24,7 +24,6 @@ extern "C" { */ void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us); - /** * @brief Disables the lp timer alarm and clears any pending alarm interrupts * diff --git a/components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c b/components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c index a555aa96da..21b4212225 100644 --- a/components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c +++ b/components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c @@ -26,7 +26,6 @@ static uint64_t lp_timer_hal_get_cycle_count(void) uint32_t lo = lp_timer_ll_get_counter_value_low(lp_timer_context.dev, 0); uint32_t hi = lp_timer_ll_get_counter_value_high(lp_timer_context.dev, 0); - lp_timer_counter_value_t result = { .lo = lo, .hi = hi @@ -35,7 +34,6 @@ static uint64_t lp_timer_hal_get_cycle_count(void) return result.val; } - void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us) { uint64_t cycle_cnt = lp_timer_hal_get_cycle_count(); @@ -44,7 +42,6 @@ void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us) lp_timer_hal_set_alarm_target(alarm_target); } - void ulp_lp_core_lp_timer_disable(void) { lp_timer_ll_set_target_enable(lp_timer_context.dev, TIMER_ID, false); diff --git a/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c b/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c index d58fe62508..e36c4b56dd 100644 --- a/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c +++ b/components/ulp/lp_core/shared/ulp_lp_core_memory_shared.c @@ -9,7 +9,6 @@ #include "soc/soc.h" #include "esp_assert.h" - /* The last CONFIG_ULP_SHARED_MEM bytes of the reserved memory are reserved for a shared cfg struct The main cpu app and the ulp binary can share variables automatically through the linkerscript generated from esp32ulp_mapgen.py, but this is not available when compiling the ULP library. @@ -24,5 +23,5 @@ ESP_STATIC_ASSERT(CONFIG_ULP_SHARED_MEM == sizeof(ulp_lp_core_memory_shared_cfg_ ulp_lp_core_memory_shared_cfg_t* ulp_lp_core_memory_shared_cfg_get(void) { - return s_shared_mem; + return s_shared_mem; } diff --git a/components/ulp/test_apps/lp_core/main/lp_core/test_main.c b/components/ulp/test_apps/lp_core/main/lp_core/test_main.c index 2a21cad981..beff51564c 100644 --- a/components/ulp/test_apps/lp_core/main/lp_core/test_main.c +++ b/components/ulp/test_apps/lp_core/main/lp_core/test_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,8 +10,6 @@ #include "test_shared.h" #include "ulp_lp_core_utils.h" - - volatile lp_core_test_commands_t main_cpu_command = LP_CORE_NO_COMMAND; volatile lp_core_test_command_reply_t main_cpu_reply = LP_CORE_COMMAND_INVALID; volatile lp_core_test_commands_t command_resp = LP_CORE_NO_COMMAND; @@ -24,69 +22,69 @@ void handle_commands(lp_core_test_commands_t cmd) { switch (cmd) { - case LP_CORE_READ_WRITE_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = LP_CORE_READ_WRITE_TEST; + case LP_CORE_READ_WRITE_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = LP_CORE_READ_WRITE_TEST; - /* Process test data */ - test_data_out = test_data_in ^ XOR_MASK; + /* Process test data */ + test_data_out = test_data_in ^ XOR_MASK; - /* Set the command reply status */ - main_cpu_reply = LP_CORE_COMMAND_OK; - main_cpu_command = LP_CORE_NO_COMMAND; + /* Set the command reply status */ + main_cpu_reply = LP_CORE_COMMAND_OK; + main_cpu_command = LP_CORE_NO_COMMAND; - break; + break; - case LP_CORE_DELAY_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = LP_CORE_DELAY_TEST; + case LP_CORE_DELAY_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = LP_CORE_DELAY_TEST; - ulp_lp_core_delay_us(test_data_in); - main_cpu_reply = LP_CORE_COMMAND_OK; - main_cpu_command = LP_CORE_NO_COMMAND; - break; + ulp_lp_core_delay_us(test_data_in); + main_cpu_reply = LP_CORE_COMMAND_OK; + main_cpu_command = LP_CORE_NO_COMMAND; + break; - case LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST; + case LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST; - /* Set the command reply status */ - main_cpu_reply = LP_CORE_COMMAND_OK; - main_cpu_command = LP_CORE_NO_COMMAND; + /* Set the command reply status */ + main_cpu_reply = LP_CORE_COMMAND_OK; + main_cpu_command = LP_CORE_NO_COMMAND; - ulp_lp_core_delay_us(1000*1000); - ulp_lp_core_wakeup_main_processor(); + ulp_lp_core_delay_us(1000 * 1000); + ulp_lp_core_wakeup_main_processor(); - break; + break; - case LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST; + case LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST; - /* Set the command reply status */ - main_cpu_reply = LP_CORE_COMMAND_OK; - main_cpu_command = LP_CORE_NO_COMMAND; + /* Set the command reply status */ + main_cpu_reply = LP_CORE_COMMAND_OK; + main_cpu_command = LP_CORE_NO_COMMAND; - ulp_lp_core_delay_us(10000*1000); - ulp_lp_core_wakeup_main_processor(); + ulp_lp_core_delay_us(10000 * 1000); + ulp_lp_core_wakeup_main_processor(); - break; + break; - case LP_CORE_NO_COMMAND: - main_cpu_reply = LP_CORE_COMMAND_NOK; - break; + case LP_CORE_NO_COMMAND: + main_cpu_reply = LP_CORE_COMMAND_NOK; + break; - default: - main_cpu_reply = LP_CORE_COMMAND_NOK; - break; + default: + main_cpu_reply = LP_CORE_COMMAND_NOK; + break; } } -int main (void) +int main(void) { while (1) { handle_commands(main_cpu_command); - } + } return 0; } diff --git a/components/ulp/test_apps/lp_core/main/lp_core/test_main_counter.c b/components/ulp/test_apps/lp_core/main/lp_core/test_main_counter.c index 405d9730e6..7bab470565 100644 --- a/components/ulp/test_apps/lp_core/main/lp_core/test_main_counter.c +++ b/components/ulp/test_apps/lp_core/main/lp_core/test_main_counter.c @@ -10,7 +10,7 @@ volatile uint32_t counter; volatile uint32_t counter_wakeup_limit; -int main (void) +int main(void) { counter++; diff --git a/components/ulp/test_apps/lp_core/main/lp_core/test_main_gpio.c b/components/ulp/test_apps/lp_core/main/lp_core/test_main_gpio.c index 1e20a27ce3..4d5b09f7b6 100644 --- a/components/ulp/test_apps/lp_core/main/lp_core/test_main_gpio.c +++ b/components/ulp/test_apps/lp_core/main/lp_core/test_main_gpio.c @@ -12,8 +12,7 @@ volatile uint32_t gpio_test_finished; volatile uint32_t gpio_test_succeeded; - -int main (void) +int main(void) { ulp_lp_core_gpio_init(LP_IO_NUM_0); diff --git a/components/ulp/test_apps/lp_core/main/lp_core/test_main_i2c.c b/components/ulp/test_apps/lp_core/main/lp_core/test_main_i2c.c index d110ce29cd..06657c0de6 100644 --- a/components/ulp/test_apps/lp_core/main/lp_core/test_main_i2c.c +++ b/components/ulp/test_apps/lp_core/main/lp_core/test_main_i2c.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,19 +17,19 @@ volatile lp_core_test_command_reply_t write_test_cmd = LP_CORE_COMMAND_INVALID; uint8_t data_rd[DATA_LENGTH] = {}; uint8_t data_wr[DATA_LENGTH] = {}; -int main (void) +int main(void) { lp_core_i2c_master_read_from_device(LP_I2C_NUM_0, I2C_SLAVE_ADDRESS, data_rd, RW_TEST_LENGTH, LP_I2C_TRANS_WAIT_FOREVER); read_test_reply = LP_CORE_COMMAND_OK; /* Wait for write command from main CPU */ - while(write_test_cmd != LP_CORE_COMMAND_OK) { + while (write_test_cmd != LP_CORE_COMMAND_OK) { } lp_core_i2c_master_write_to_device(LP_I2C_NUM_0, I2C_SLAVE_ADDRESS, data_wr, RW_TEST_LENGTH, LP_I2C_TRANS_WAIT_FOREVER); write_test_cmd = LP_CORE_COMMAND_NOK; - while(1) { + while (1) { } } diff --git a/components/ulp/test_apps/lp_core/main/lp_core/test_main_set_timer_wakeup.c b/components/ulp/test_apps/lp_core/main/lp_core/test_main_set_timer_wakeup.c index e46124d136..c584221e98 100644 --- a/components/ulp/test_apps/lp_core/main/lp_core/test_main_set_timer_wakeup.c +++ b/components/ulp/test_apps/lp_core/main/lp_core/test_main_set_timer_wakeup.c @@ -11,13 +11,13 @@ volatile uint32_t set_timer_wakeup_counter; volatile uint32_t WAKEUP_PERIOD_BASE_US = 100000; -int main (void) +int main(void) { set_timer_wakeup_counter++; /* Alternate between WAKEUP_PERIOD_BASE_US and 2*WAKEUP_PERIOD_BASE_US to let the main CPU see that the wake-up time can be reconfigured */ - ulp_lp_core_lp_timer_set_wakeup_time( ((set_timer_wakeup_counter % 2) + 1)*WAKEUP_PERIOD_BASE_US); + ulp_lp_core_lp_timer_set_wakeup_time(((set_timer_wakeup_counter % 2) + 1)*WAKEUP_PERIOD_BASE_US); return 0; } diff --git a/components/ulp/test_apps/lp_core/main/lp_core/test_shared.h b/components/ulp/test_apps/lp_core/main/lp_core/test_shared.h index 5541045ccf..7497ff4e6c 100644 --- a/components/ulp/test_apps/lp_core/main/lp_core/test_shared.h +++ b/components/ulp/test_apps/lp_core/main/lp_core/test_shared.h @@ -12,7 +12,7 @@ #define DATA_LENGTH 200 #define RW_TEST_LENGTH 129 /*!= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); @@ -261,36 +261,36 @@ TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]") /* ULP co-processor program to read from and write to peripheral registers */ const ulp_insn_t program[] = { - I_MOVI(R1, 64), // r1 = 64 - I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15), // r0 = REG_READ(RTC_CNTL_STORE1_REG[15:0]) - I_ST(R0, R1, 0), // mem[r1 + 0] = r0 - I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11), // r0 = REG_READ(RTC_CNTL_STORE1_REG[11:4]) - I_ST(R0, R1, 1), // mem[r1 + 1] = r0 - I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31), // r0 = REG_READ(RTC_CNTL_STORE1_REG[31:16]) - I_ST(R0, R1, 2), // mem[r1 + 2] = r0 - I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27), // r0 = REG_READ(RTC_CNTL_STORE1_REG[27:20]) - I_ST(R0, R1, 3), // mem[r1 + 3] = r0 - I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89), // REG_WRITE(RTC_CNTL_STORE0_REG[7:0], 0x89) - I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab), // REG_WRITE(RTC_CNTL_STORE0_REG[15:8], 0xab) - I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd), // REG_WRITE(RTC_CNTL_STORE0_REG[23:16], 0xcd) - I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef), // REG_WRITE(RTC_CNTL_STORE0_REG[31:24], 0xef) - I_LD(R0, R1, 4), // r0 = mem[r1 + 4] - I_ADDI(R0, R0, 1), // r0 = r0 + 1 - I_ST(R0, R1, 4), // mem[r1 + 4] = r0 - I_END(), // stop ULP timer - I_HALT() // halt + I_MOVI(R1, 64), // r1 = 64 + I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15), // r0 = REG_READ(RTC_CNTL_STORE1_REG[15:0]) + I_ST(R0, R1, 0), // mem[r1 + 0] = r0 + I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11), // r0 = REG_READ(RTC_CNTL_STORE1_REG[11:4]) + I_ST(R0, R1, 1), // mem[r1 + 1] = r0 + I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31), // r0 = REG_READ(RTC_CNTL_STORE1_REG[31:16]) + I_ST(R0, R1, 2), // mem[r1 + 2] = r0 + I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27), // r0 = REG_READ(RTC_CNTL_STORE1_REG[27:20]) + I_ST(R0, R1, 3), // mem[r1 + 3] = r0 + I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89), // REG_WRITE(RTC_CNTL_STORE0_REG[7:0], 0x89) + I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab), // REG_WRITE(RTC_CNTL_STORE0_REG[15:8], 0xab) + I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd), // REG_WRITE(RTC_CNTL_STORE0_REG[23:16], 0xcd) + I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef), // REG_WRITE(RTC_CNTL_STORE0_REG[31:24], 0xef) + I_LD(R0, R1, 4), // r0 = mem[r1 + 4] + I_ADDI(R0, R0, 1), // r0 = r0 + 1 + I_ST(R0, R1, 4), // mem[r1 + 4] = r0 + I_END(), // stop ULP timer + I_HALT() // halt }; /* Set data in the peripheral register to be read by the ULP co-processor */ REG_WRITE(RTC_CNTL_STORE1_REG, 0x89abcdef); /* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */ - size_t size = sizeof(program)/sizeof(ulp_insn_t); + size_t size = sizeof(program) / sizeof(ulp_insn_t); TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size)); TEST_ESP_OK(ulp_run(0)); /* Wait for the ULP co-processor to finish up */ - vTaskDelay(100/portTICK_PERIOD_MS); + vTaskDelay(100 / portTICK_PERIOD_MS); /* Verify the test results */ TEST_ASSERT_EQUAL_HEX32(0xefcdab89, REG_READ(RTC_CNTL_STORE0_REG)); @@ -328,13 +328,13 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]") }; const size_t test_items_count = - sizeof(test_items)/sizeof(test_items[0]); + sizeof(test_items) / sizeof(test_items[0]); for (size_t i = 0; i < test_items_count; ++i) { - const uint32_t mask = (uint32_t) (((1ULL << test_items[i].width) - 1) << test_items[i].low); + const uint32_t mask = (uint32_t)(((1ULL << test_items[i].width) - 1) << test_items[i].low); const uint32_t not_mask = ~mask; printf("#%2d: low: %2d width: %2d mask: %08" PRIx32 " expected: %08" PRIx32 " ", i, - test_items[i].low, test_items[i].width, - mask, not_mask); + test_items[i].low, test_items[i].width, + mask, not_mask); /* Set all bits in RTC_CNTL_STORE0_REG and reset all bits in RTC_CNTL_STORE1_REG */ uint32_t rtc_store0 = REG_READ(RTC_CNTL_STORE0_REG); @@ -345,24 +345,24 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]") /* ULP co-processor program to write to peripheral registers */ const ulp_insn_t program[] = { I_WR_REG(RTC_CNTL_STORE0_REG, - test_items[i].low, - test_items[i].low + test_items[i].width - 1, - 0), + test_items[i].low, + test_items[i].low + test_items[i].width - 1, + 0), I_WR_REG(RTC_CNTL_STORE1_REG, - test_items[i].low, - test_items[i].low + test_items[i].width - 1, - 0xff & ((1 << test_items[i].width) - 1)), + test_items[i].low, + test_items[i].low + test_items[i].width - 1, + 0xff & ((1 << test_items[i].width) - 1)), I_END(), I_HALT() }; /* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */ - size_t size = sizeof(program)/sizeof(ulp_insn_t); + size_t size = sizeof(program) / sizeof(ulp_insn_t); TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size)); TEST_ESP_OK(ulp_run(0)); /* Wait for the ULP co-processor to finish up */ - vTaskDelay(10/portTICK_PERIOD_MS); + vTaskDelay(10 / portTICK_PERIOD_MS); /* Verify the test results */ uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG); @@ -378,9 +378,6 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]") } } - - - TEST_CASE("ULP FSM timer setting", "[ulp]") { assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); @@ -403,7 +400,7 @@ TEST_CASE("ULP FSM timer setting", "[ulp]") }; /* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */ - size_t size = sizeof(program)/sizeof(ulp_insn_t); + size_t size = sizeof(program) / sizeof(ulp_insn_t); TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size)); assert(offset >= size && "data offset needs to be greater or equal to program size"); TEST_ESP_OK(ulp_run(0)); @@ -418,7 +415,8 @@ TEST_CASE("ULP FSM timer setting", "[ulp]") 100000, // 100 ms 200000, // 200 ms 500000, // 500 ms - 1000000 }; // 1 sec + 1000000 + }; // 1 sec const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]); for (size_t i = 0; i < tests_count; ++i) { @@ -474,7 +472,7 @@ TEST_CASE("ULP FSM interrupt signal can be handled via ISRs on the main core", " TEST_ASSERT_EQUAL(ESP_OK, ulp_isr_register(ulp_isr, (void *)ulp_isr_sem)); /* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */ - size_t size = sizeof(program)/sizeof(ulp_insn_t); + size_t size = sizeof(program) / sizeof(ulp_insn_t); TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size)); TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0)); @@ -482,7 +480,7 @@ TEST_CASE("ULP FSM interrupt signal can be handled via ISRs on the main core", " TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(ulp_isr_sem, portMAX_DELAY)); /* Deregister the ISR */ - TEST_ASSERT_EQUAL(ESP_OK, ulp_isr_deregister(ulp_isr, (void *)ulp_isr_sem )); + TEST_ASSERT_EQUAL(ESP_OK, ulp_isr_deregister(ulp_isr, (void *)ulp_isr_sem)); /* Delete test semaphore */ vSemaphoreDelete(ulp_isr_sem); diff --git a/components/ulp/test_apps/ulp_fsm/main/test_ulp_manual.c b/components/ulp/test_apps/ulp_fsm/main/test_ulp_manual.c index 83462c902f..168dad4f90 100644 --- a/components/ulp/test_apps/ulp_fsm/main/test_ulp_manual.c +++ b/components/ulp/test_apps/ulp_fsm/main/test_ulp_manual.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,29 +43,29 @@ void ulp_fsm_controls_rtc_io(void) I_MOVI(R0, 0), // r0 is LED state I_MOVI(R2, 16), // loop r2 from 16 down to 0 M_LABEL(4), // define label 4 - I_SUBI(R2, R2, 1), // r2 = r2 - 1 - M_BXZ(6), // branch to label 6 if r2 = 0 - I_ADDI(R0, R0, 1), // r0 = (r0 + 1) % 2 - I_ANDI(R0, R0, 0x1), - M_BL(0, 1), // if r0 < 1 goto 0 - M_LABEL(1), // define label 1 - I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1 - M_BX(2), // goto 2 - M_LABEL(0), // define label 0 - I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0 - M_LABEL(2), // define label 2 - I_MOVI(R1, 100), // loop R1 from 100 down to 0 - M_LABEL(3), // define label 3 - I_SUBI(R1, R1, 1), // r1 = r1 - 1 - M_BXZ(5), // branch to label 5 if r1 = 0 - I_DELAY(32000), // delay for a while - M_BX(3), // goto 3 - M_LABEL(5), // define label 5 - M_BX(4), // loop back to label 4 + I_SUBI(R2, R2, 1), // r2 = r2 - 1 + M_BXZ(6), // branch to label 6 if r2 = 0 + I_ADDI(R0, R0, 1), // r0 = (r0 + 1) % 2 + I_ANDI(R0, R0, 0x1), + M_BL(0, 1), // if r0 < 1 goto 0 + M_LABEL(1), // define label 1 + I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1 + M_BX(2), // goto 2 + M_LABEL(0), // define label 0 + I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0 + M_LABEL(2), // define label 2 + I_MOVI(R1, 100), // loop R1 from 100 down to 0 + M_LABEL(3), // define label 3 + I_SUBI(R1, R1, 1), // r1 = r1 - 1 + M_BXZ(5), // branch to label 5 if r1 = 0 + I_DELAY(32000), // delay for a while + M_BX(3), // goto 3 + M_LABEL(5), // define label 5 + M_BX(4), // loop back to label 4 M_LABEL(6), // define label 6 - I_WAKE(), // wake up the SoC - I_END(), // stop ULP program timer - I_HALT() + I_WAKE(), // wake up the SoC + I_END(), // stop ULP program timer + I_HALT() }; /* Configure LED GPIOs */ @@ -74,14 +74,14 @@ void ulp_fsm_controls_rtc_io(void) GPIO_NUM_0, GPIO_NUM_4 }; - for (size_t i = 0; i < sizeof(led_gpios)/sizeof(led_gpios[0]); ++i) { + for (size_t i = 0; i < sizeof(led_gpios) / sizeof(led_gpios[0]); ++i) { rtc_gpio_init(led_gpios[i]); rtc_gpio_set_direction(led_gpios[i], RTC_GPIO_MODE_OUTPUT_ONLY); rtc_gpio_set_level(led_gpios[i], 0); } /* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */ - size_t size = sizeof(program)/sizeof(ulp_insn_t); + size_t size = sizeof(program) / sizeof(ulp_insn_t); TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size)); TEST_ESP_OK(ulp_run(0)); @@ -155,18 +155,18 @@ void ulp_fsm_temp_sens(void) I_SUBI(R3, R3, 1), // end = length - 1 I_SUBR(R3, R3, R2), // r3 = length - counter M_BXF(1), // if overflow goto 1: - I_TSENS(R0, 16383), // r0 <- tsens - I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] <- r0 - I_ADDI(R2, R2, 1), // counter += 1 - I_ST(R2, R1, 1), // save counter - I_HALT(), // enter sleep + I_TSENS(R0, 16383), // r0 <- tsens + I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] <- r0 + I_ADDI(R2, R2, 1), // counter += 1 + I_ST(R2, R1, 1), // save counter + I_HALT(), // enter sleep M_LABEL(1), // done with measurements - I_END(), // stop ULP timer - I_WAKE(), // initiate wakeup - I_HALT() + I_END(), // stop ULP timer + I_WAKE(), // initiate wakeup + I_HALT() }; - size_t size = sizeof(program)/sizeof(ulp_insn_t); + size_t size = sizeof(program) / sizeof(ulp_insn_t); TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size)); assert(offset >= size); @@ -183,8 +183,6 @@ void ulp_fsm_temp_sens(void) } #endif //#if !DISABLED_FOR_TARGETS(ESP32) - - void ulp_fsm_adc(void) { assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig"); @@ -258,17 +256,17 @@ void ulp_fsm_adc(void) I_SUBI(R3, R3, 1), // end = length - 1 I_SUBR(R3, R3, R2), // r3 = length - counter M_BXF(1), // if overflow goto 1: - I_ADC(R0, adc, channel), // r0 <- ADC - I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] = r0 - I_ADDI(R2, R2, 1), // counter += 1 - I_ST(R2, R1, 1), // save counter - I_HALT(), // enter sleep + I_ADC(R0, adc, channel), // r0 <- ADC + I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] = r0 + I_ADDI(R2, R2, 1), // counter += 1 + I_ST(R2, R1, 1), // save counter + I_HALT(), // enter sleep M_LABEL(1), // done with measurements - I_END(), // stop ULP program timer - I_HALT() + I_END(), // stop ULP program timer + I_HALT() }; - size_t size = sizeof(program)/sizeof(ulp_insn_t); + size_t size = sizeof(program) / sizeof(ulp_insn_t); TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size)); assert(offset >= size); diff --git a/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c b/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c index e4f7ec12d3..33db873eb2 100644 --- a/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c +++ b/components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -261,8 +261,6 @@ TEST_CASE("ULP-RISC-V can stop itself and be resumed from the main CPU", "[ulp]" TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter)); } - - TEST_CASE("ULP-RISC-V mutex", "[ulp]") { /* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */ @@ -281,17 +279,16 @@ TEST_CASE("ULP-RISC-V mutex", "[ulp]") ulp_riscv_lock_release(lock); } - while(ulp_main_cpu_reply != RISCV_COMMAND_OK) { + while (ulp_main_cpu_reply != RISCV_COMMAND_OK) { // Wait for ULP to finish } /* If the variable is protected there should be no race conditions results should be the sum of increments made by ULP and by main CPU */ - TEST_ASSERT_EQUAL(2*MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer); + TEST_ASSERT_EQUAL(2 * MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer); } - static void do_ulp_wakeup_deepsleep(riscv_test_commands_t ulp_cmd, bool rtc_periph_pd) { if (!rtc_periph_pd) { @@ -325,9 +322,8 @@ static void do_ulp_wakeup_after_long_delay_deepsleep(void) /* Certain erroneous wake-up triggers happen only after sleeping for a few seconds */ TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a long delay", "[ulp]", - do_ulp_wakeup_after_long_delay_deepsleep, - check_reset_reason_ulp_wakeup); - + do_ulp_wakeup_after_long_delay_deepsleep, + check_reset_reason_ulp_wakeup); static void do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on(void) { @@ -335,8 +331,8 @@ static void do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on(void) } TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a long delay, RTC periph powerup", "[ulp]", - do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on, - check_reset_reason_ulp_wakeup); + do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on, + check_reset_reason_ulp_wakeup); static void do_ulp_wakeup_after_short_delay_deepsleep(void) { @@ -344,9 +340,8 @@ static void do_ulp_wakeup_after_short_delay_deepsleep(void) } TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a short delay", "[ulp]", - do_ulp_wakeup_after_short_delay_deepsleep, - check_reset_reason_ulp_wakeup); - + do_ulp_wakeup_after_short_delay_deepsleep, + check_reset_reason_ulp_wakeup); static void do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on(void) { @@ -354,8 +349,8 @@ static void do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on(void) } TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a short delay, RTC periph powerup", "[ulp]", - do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on, - check_reset_reason_ulp_wakeup); + do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on, + check_reset_reason_ulp_wakeup); typedef struct { SemaphoreHandle_t ulp_isr_sw_sem; @@ -393,7 +388,7 @@ TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core /* Register ULP RISC-V signal ISR */ TEST_ASSERT_EQUAL(ESP_OK, ulp_riscv_isr_register(ulp_riscv_isr, (void *)&test_sem_cfg, - (ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT))); + (ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT))); /* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */ printf("Loading good ULP firmware\n"); @@ -425,7 +420,7 @@ TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core /* Deregister the ISR */ TEST_ASSERT_EQUAL(ESP_OK, ulp_riscv_isr_deregister(ulp_riscv_isr, (void *)&test_sem_cfg, - (ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT))); + (ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT))); /* Delete test semaphores */ vSemaphoreDelete(test_sem_cfg.ulp_isr_sw_sem); @@ -445,7 +440,6 @@ TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core TEST_CASE("ULP ADC can init-deinit-init", "[ulp]") { - ulp_adc_cfg_t riscv_adc_cfg = { .adc_n = ADC_UNIT, .channel = CHANNEL, diff --git a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c index 1ecf9157d5..efed04a9b5 100644 --- a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c +++ b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,7 +12,6 @@ #include "ulp_riscv_lock_ulp_core.h" #include "ulp_test_shared.h" - volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND; volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID; volatile riscv_test_commands_t command_resp = RISCV_NO_COMMAND; @@ -28,96 +27,96 @@ void handle_commands(riscv_test_commands_t cmd) riscv_counter++; switch (cmd) { - case RISCV_READ_WRITE_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = RISCV_READ_WRITE_TEST; + case RISCV_READ_WRITE_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = RISCV_READ_WRITE_TEST; - /* Process test data */ - riscv_test_data_out = riscv_test_data_in ^ XOR_MASK; + /* Process test data */ + riscv_test_data_out = riscv_test_data_in ^ XOR_MASK; - /* Set the command reply status */ - main_cpu_reply = RISCV_COMMAND_OK; + /* Set the command reply status */ + main_cpu_reply = RISCV_COMMAND_OK; - /* Wakeup the main CPU */ - ulp_riscv_wakeup_main_processor(); - break; + /* Wakeup the main CPU */ + ulp_riscv_wakeup_main_processor(); + break; - case RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST; + case RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST; - /* Set the command reply status */ - main_cpu_reply = RISCV_COMMAND_OK; + /* Set the command reply status */ + main_cpu_reply = RISCV_COMMAND_OK; - ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS); + ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS); - /* Wakeup the main CPU */ - ulp_riscv_wakeup_main_processor(); - break; + /* Wakeup the main CPU */ + ulp_riscv_wakeup_main_processor(); + break; - case RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST; + case RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST; - /* Set the command reply status */ - main_cpu_reply = RISCV_COMMAND_OK; + /* Set the command reply status */ + main_cpu_reply = RISCV_COMMAND_OK; - ulp_riscv_delay_cycles(10000 * ULP_RISCV_CYCLES_PER_MS); + ulp_riscv_delay_cycles(10000 * ULP_RISCV_CYCLES_PER_MS); - /* Wakeup the main CPU */ - ulp_riscv_wakeup_main_processor(); - break; + /* Wakeup the main CPU */ + ulp_riscv_wakeup_main_processor(); + break; - case RISCV_LIGHT_SLEEP_WAKEUP_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = RISCV_LIGHT_SLEEP_WAKEUP_TEST; + case RISCV_LIGHT_SLEEP_WAKEUP_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = RISCV_LIGHT_SLEEP_WAKEUP_TEST; - /* Set the command reply status */ - main_cpu_reply = RISCV_COMMAND_OK; + /* Set the command reply status */ + main_cpu_reply = RISCV_COMMAND_OK; - /* Wakeup the main CPU */ - ulp_riscv_wakeup_main_processor(); - break; + /* Wakeup the main CPU */ + ulp_riscv_wakeup_main_processor(); + break; - case RISCV_STOP_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = RISCV_STOP_TEST; + case RISCV_STOP_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = RISCV_STOP_TEST; - /* Set the command reply status */ - main_cpu_reply = RISCV_COMMAND_OK; + /* Set the command reply status */ + main_cpu_reply = RISCV_COMMAND_OK; - /* Will never return from here */ - ulp_riscv_timer_stop(); - ulp_riscv_halt(); + /* Will never return from here */ + ulp_riscv_timer_stop(); + ulp_riscv_halt(); - break; + break; - case RISCV_MUTEX_TEST: - /* Echo the command ID back to the main CPU */ - command_resp = RISCV_MUTEX_TEST; + case RISCV_MUTEX_TEST: + /* Echo the command ID back to the main CPU */ + command_resp = RISCV_MUTEX_TEST; - for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) { - ulp_riscv_lock_acquire(&lock); - riscv_incrementer++; - ulp_riscv_lock_release(&lock); - } - /* Set the command reply status */ - main_cpu_reply = RISCV_COMMAND_OK; - main_cpu_command = RISCV_NO_COMMAND; + for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) { + ulp_riscv_lock_acquire(&lock); + riscv_incrementer++; + ulp_riscv_lock_release(&lock); + } + /* Set the command reply status */ + main_cpu_reply = RISCV_COMMAND_OK; + main_cpu_command = RISCV_NO_COMMAND; - break; + break; - case RISCV_NO_COMMAND: - main_cpu_reply = RISCV_COMMAND_OK; - break; + case RISCV_NO_COMMAND: + main_cpu_reply = RISCV_COMMAND_OK; + break; - default: - main_cpu_reply = RISCV_COMMAND_NOK; - break; + default: + main_cpu_reply = RISCV_COMMAND_NOK; + break; } } -int main (void) +int main(void) { while (1) { diff --git a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_cocpu_crash.c b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_cocpu_crash.c index 054de4cd33..4b9e243bae 100644 --- a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_cocpu_crash.c +++ b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_cocpu_crash.c @@ -8,7 +8,7 @@ #include #include "ulp_riscv_utils.h" -int main (void) +int main(void) { // Wait for the main core in the test case to enter lightsleep ulp_riscv_delay_cycles(100 * ULP_RISCV_CYCLES_PER_MS); diff --git a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_second_cocpu_firmware.c b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_second_cocpu_firmware.c index 80c97ff206..aae8d58aa3 100644 --- a/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_second_cocpu_firmware.c +++ b/components/ulp/test_apps/ulp_riscv/main/ulp/test_main_second_cocpu_firmware.c @@ -8,7 +8,7 @@ volatile uint32_t riscv_counter2 = 0; -int main (void) +int main(void) { riscv_counter2++; diff --git a/components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h b/components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h index 77791eac9a..babcdeb10f 100644 --- a/components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h +++ b/components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h @@ -8,7 +8,7 @@ #define MUTEX_TEST_ITERATIONS 100000 #define XOR_MASK 0xDEADBEEF -typedef enum{ +typedef enum { RISCV_READ_WRITE_TEST = 1, RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST, RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST, diff --git a/components/ulp/ulp_common/ulp_common.c b/components/ulp/ulp_common/ulp_common.c index 52b64254e7..b290645e70 100644 --- a/components/ulp/ulp_common/ulp_common.c +++ b/components/ulp/ulp_common/ulp_common.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -28,8 +28,8 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us) #if CONFIG_IDF_TARGET_ESP32 uint64_t period_cycles = (period_us_64 << RTC_CLK_CAL_FRACT) / esp_clk_slowclk_cal_get(); uint64_t min_sleep_period_cycles = ULP_FSM_PREPARE_SLEEP_CYCLES - + ULP_FSM_WAKEUP_SLEEP_CYCLES - + REG_GET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT); + + ULP_FSM_WAKEUP_SLEEP_CYCLES + + REG_GET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT); if (period_cycles < min_sleep_period_cycles) { period_cycles = min_sleep_period_cycles; ESP_LOGW("ulp", "Sleep period clipped to minimum of %"PRIu32" cycles", (uint32_t) min_sleep_period_cycles); @@ -37,7 +37,7 @@ esp_err_t ulp_set_wakeup_period(size_t period_index, uint32_t period_us) period_cycles -= min_sleep_period_cycles; } REG_SET_FIELD(SENS_ULP_CP_SLEEP_CYC0_REG + period_index * sizeof(uint32_t), - SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles); + SENS_SLEEP_CYCLES_S0, (uint32_t) period_cycles); #elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3) soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get(); rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX; diff --git a/components/ulp/ulp_fsm/include/esp32/ulp.h b/components/ulp/ulp_fsm/include/esp32/ulp.h index c5d9b8b9f4..5eb33fd683 100644 --- a/components/ulp/ulp_fsm/include/esp32/ulp.h +++ b/components/ulp/ulp_fsm/include/esp32/ulp.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2016-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,7 +22,6 @@ extern "C" { * @{ */ - #define R0 0 /*!< general purpose register 0 */ #define R1 1 /*!< general purpose register 1 */ #define R2 2 /*!< general purpose register 2 */ @@ -102,7 +101,6 @@ extern "C" { #define SUB_OPCODE_MACRO_LABELPC 2 /*!< Label pointer macro */ /**@}*/ - /** * @brief Instruction format structure * @@ -306,7 +304,8 @@ union ulp_insn { * @param reg peripheral register in RTC_CNTL_, RTC_IO_, SENS_, RTC_I2C peripherals. * @return periph_sel value for the peripheral to which this register belongs. */ -static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { +static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) +{ uint32_t ret = 3; if (reg < DR_REG_RTCCNTL_BASE) { assert(0 && "invalid register base"); @@ -314,9 +313,9 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { ret = RD_REG_PERIPH_RTC_CNTL; } else if (reg < DR_REG_SENS_BASE) { ret = RD_REG_PERIPH_RTC_IO; - } else if (reg < DR_REG_RTC_I2C_BASE){ + } else if (reg < DR_REG_RTC_I2C_BASE) { ret = RD_REG_PERIPH_SENS; - } else if (reg < DR_REG_IO_MUX_BASE){ + } else if (reg < DR_REG_IO_MUX_BASE) { ret = RD_REG_PERIPH_RTC_I2C; } else { assert(0 && "invalid register base"); @@ -465,7 +464,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { .sub_opcode = SUB_OPCODE_ST, \ .opcode = OPCODE_ST } } - /** * Load value from RTC memory into reg_dest register. * @@ -480,7 +478,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { .unused2 = 0, \ .opcode = OPCODE_LD } } - /** * Branch relative if R0 less than immediate value. * @@ -596,7 +593,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { .sub_opcode = SUB_OPCODE_BX, \ .opcode = OPCODE_BRANCH } } - /** * Addition: dest = src1 + src2 */ @@ -669,7 +665,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { .sub_opcode = SUB_OPCODE_ALU_REG, \ .opcode = OPCODE_ALU } } - /** * Logical shift right: dest = src >> shift */ @@ -694,7 +689,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { .sub_opcode = SUB_OPCODE_ALU_IMM, \ .opcode = OPCODE_ALU } } - /** * Subtract register and an immediate value: dest = src - imm */ @@ -755,7 +749,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) { .sub_opcode = SUB_OPCODE_ALU_IMM, \ .opcode = OPCODE_ALU } } - /** * Logical shift right register value by an immediate: dest = val >> imm */ diff --git a/components/ulp/ulp_fsm/include/esp32s2/ulp.h b/components/ulp/ulp_fsm/include/esp32s2/ulp.h index dff1697355..67cdc19e40 100644 --- a/components/ulp/ulp_fsm/include/esp32s2/ulp.h +++ b/components/ulp/ulp_fsm/include/esp32s2/ulp.h @@ -22,7 +22,6 @@ extern "C" { * @{ */ - #define R0 0 /*!< general purpose register 0 */ #define R1 1 /*!< general purpose register 1 */ #define R2 2 /*!< general purpose register 2 */ @@ -906,7 +905,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) .sub_opcode = SUB_OPCODE_ALU_REG, \ .opcode = OPCODE_ALU } } - /** * Logical shift right: dest = src >> shift */ @@ -933,7 +931,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) .sub_opcode = SUB_OPCODE_ALU_IMM, \ .opcode = OPCODE_ALU } } - /** * Subtract register and an immediate value: dest = src - imm */ @@ -999,7 +996,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) .sub_opcode = SUB_OPCODE_ALU_IMM, \ .opcode = OPCODE_ALU } } - /** * Logical shift right register value by an immediate: dest = val >> imm */ diff --git a/components/ulp/ulp_fsm/include/esp32s3/ulp.h b/components/ulp/ulp_fsm/include/esp32s3/ulp.h index dff1697355..67cdc19e40 100644 --- a/components/ulp/ulp_fsm/include/esp32s3/ulp.h +++ b/components/ulp/ulp_fsm/include/esp32s3/ulp.h @@ -22,7 +22,6 @@ extern "C" { * @{ */ - #define R0 0 /*!< general purpose register 0 */ #define R1 1 /*!< general purpose register 1 */ #define R2 2 /*!< general purpose register 2 */ @@ -906,7 +905,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) .sub_opcode = SUB_OPCODE_ALU_REG, \ .opcode = OPCODE_ALU } } - /** * Logical shift right: dest = src >> shift */ @@ -933,7 +931,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) .sub_opcode = SUB_OPCODE_ALU_IMM, \ .opcode = OPCODE_ALU } } - /** * Subtract register and an immediate value: dest = src - imm */ @@ -999,7 +996,6 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) .sub_opcode = SUB_OPCODE_ALU_IMM, \ .opcode = OPCODE_ALU } } - /** * Logical shift right register value by an immediate: dest = val >> imm */ diff --git a/components/ulp/ulp_fsm/ulp.c b/components/ulp/ulp_fsm/ulp.c index ebb405fd68..e03751b0eb 100644 --- a/components/ulp/ulp_fsm/ulp.c +++ b/components/ulp/ulp_fsm/ulp.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -93,7 +93,7 @@ esp_err_t ulp_run(uint32_t entry_point) REG_SET_FIELD(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_PC_INIT, entry_point); SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SEL); // Select ULP_TIMER trigger target for ULP. // start ULP clock gate. - SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG ,RTC_CNTL_ULP_CP_CLK_FO); + SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_CLK_FO); // ULP FSM sends the DONE signal. CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE_FORCE); #if CONFIG_IDF_TARGET_ESP32S3 @@ -133,11 +133,11 @@ esp_err_t ulp_load_binary(uint32_t load_addr, const uint8_t* program_binary, siz } size_t total_size = (size_t) header.text_offset + (size_t) header.text_size + - (size_t) header.data_size; + (size_t) header.data_size; ESP_LOGD(TAG, "program_size_bytes: %d total_size: %d offset: %d .text: %d, .data: %d, .bss: %d", - program_size_bytes, total_size, header.text_offset, - header.text_size, header.data_size, header.bss_size); + program_size_bytes, total_size, header.text_offset, + header.text_size, header.data_size, header.bss_size); if (total_size != program_size_bytes) { return ESP_ERR_INVALID_SIZE; diff --git a/components/ulp/ulp_fsm/ulp_macro.c b/components/ulp/ulp_fsm/ulp_macro.c index fd4c335c4d..f7d436f7ab 100644 --- a/components/ulp/ulp_fsm/ulp_macro.c +++ b/components/ulp/ulp_fsm/ulp_macro.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -84,7 +84,6 @@ static int reloc_sort_func(const void* p_lhs, const void* p_rhs) return 0; } - /* Processing branch and label macros involves four steps: * * 1. Iterate over program and count all instructions @@ -124,52 +123,52 @@ static int reloc_sort_func(const void* p_lhs, const void* p_rhs) */ static esp_err_t do_single_reloc(ulp_insn_t* program, uint32_t load_addr, - reloc_info_t label_info, reloc_info_t the_reloc) + reloc_info_t label_info, reloc_info_t the_reloc) { size_t insn_offset = the_reloc.addr - load_addr; ulp_insn_t* insn = &program[insn_offset]; switch (the_reloc.type) { - case RELOC_TYPE_BRANCH: { - // B, BS and BX have the same layout of opcode/sub_opcode fields, - // and share the same opcode. B and BS also have the same layout of - // offset and sign fields. - assert(insn->b.opcode == OPCODE_BRANCH - && "branch macro was applied to a non-branch instruction"); - switch (insn->b.sub_opcode) { - case SUB_OPCODE_B: - case SUB_OPCODE_BS:{ - int32_t offset = ((int32_t) label_info.addr) - ((int32_t) the_reloc.addr); - uint32_t abs_offset = abs(offset); - uint32_t sign = (offset >= 0) ? 0 : 1; - if (abs_offset > 127) { - ESP_LOGW(TAG, "target out of range: branch from %x to %x", - the_reloc.addr, label_info.addr); - return ESP_ERR_ULP_BRANCH_OUT_OF_RANGE; - } - insn->b.offset = abs_offset; //== insn->bs.offset = abs_offset; - insn->b.sign = sign; //== insn->bs.sign = sign; - break; - } - case SUB_OPCODE_BX:{ - assert(insn->bx.reg == 0 && - "relocation applied to a jump with offset in register"); - insn->bx.addr = label_info.addr; - break; - } - default: - assert(false && "unexpected branch sub-opcode"); + case RELOC_TYPE_BRANCH: { + // B, BS and BX have the same layout of opcode/sub_opcode fields, + // and share the same opcode. B and BS also have the same layout of + // offset and sign fields. + assert(insn->b.opcode == OPCODE_BRANCH + && "branch macro was applied to a non-branch instruction"); + switch (insn->b.sub_opcode) { + case SUB_OPCODE_B: + case SUB_OPCODE_BS: { + int32_t offset = ((int32_t) label_info.addr) - ((int32_t) the_reloc.addr); + uint32_t abs_offset = abs(offset); + uint32_t sign = (offset >= 0) ? 0 : 1; + if (abs_offset > 127) { + ESP_LOGW(TAG, "target out of range: branch from %x to %x", + the_reloc.addr, label_info.addr); + return ESP_ERR_ULP_BRANCH_OUT_OF_RANGE; } + insn->b.offset = abs_offset; //== insn->bs.offset = abs_offset; + insn->b.sign = sign; //== insn->bs.sign = sign; break; } - case RELOC_TYPE_LABELPC: { - assert((insn->alu_imm.opcode == OPCODE_ALU && insn->alu_imm.sub_opcode == SUB_OPCODE_ALU_IMM && insn->alu_imm.sel == ALU_SEL_MOV) - && "pc macro was applied to an incompatible instruction"); - insn->alu_imm.imm = label_info.addr; + case SUB_OPCODE_BX: { + assert(insn->bx.reg == 0 && + "relocation applied to a jump with offset in register"); + insn->bx.addr = label_info.addr; break; } default: - assert(false && "unknown reloc type"); + assert(false && "unexpected branch sub-opcode"); + } + break; + } + case RELOC_TYPE_LABELPC: { + assert((insn->alu_imm.opcode == OPCODE_ALU && insn->alu_imm.sub_opcode == SUB_OPCODE_ALU_IMM && insn->alu_imm.sel == ALU_SEL_MOV) + && "pc macro was applied to an incompatible instruction"); + insn->alu_imm.imm = label_info.addr; + break; + } + default: + assert(false && "unknown reloc type"); } return ESP_OK; } @@ -191,12 +190,12 @@ esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* prog const size_t ulp_mem_end = CONFIG_ULP_COPROC_RESERVE_MEM / sizeof(ulp_insn_t); if (load_addr > ulp_mem_end) { ESP_LOGW(TAG, "invalid load address %"PRIx32", max is %x", - load_addr, ulp_mem_end); + load_addr, ulp_mem_end); return ESP_ERR_ULP_INVALID_LOAD_ADDR; } if (real_program_size + load_addr > ulp_mem_end) { ESP_LOGE(TAG, "program too big: %d words, max is %d words", - real_program_size, ulp_mem_end); + real_program_size, ulp_mem_end); return ESP_ERR_ULP_SIZE_TOO_BIG; } // If no macros found, copy the program and return. @@ -205,7 +204,7 @@ esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* prog return ESP_OK; } reloc_info_t* reloc_info = - (reloc_info_t*) malloc(sizeof(reloc_info_t) * macro_count); + (reloc_info_t*) malloc(sizeof(reloc_info_t) * macro_count); if (reloc_info == NULL) { return ESP_ERR_NO_MEM; } @@ -221,20 +220,20 @@ esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* prog ulp_insn_t r_insn = *read_ptr; if (r_insn.macro.opcode == OPCODE_MACRO) { switch (r_insn.macro.sub_opcode) { - case SUB_OPCODE_MACRO_LABEL: - *cur_reloc = RELOC_INFO_LABEL(r_insn.macro.label, - cur_insn_addr); - break; - case SUB_OPCODE_MACRO_BRANCH: - *cur_reloc = RELOC_INFO_BRANCH(r_insn.macro.label, - cur_insn_addr); - break; - case SUB_OPCODE_MACRO_LABELPC: - *cur_reloc = RELOC_INFO_LABELPC(r_insn.macro.label, - cur_insn_addr); - break; - default: - assert(0 && "invalid sub_opcode for macro insn"); + case SUB_OPCODE_MACRO_LABEL: + *cur_reloc = RELOC_INFO_LABEL(r_insn.macro.label, + cur_insn_addr); + break; + case SUB_OPCODE_MACRO_BRANCH: + *cur_reloc = RELOC_INFO_BRANCH(r_insn.macro.label, + cur_insn_addr); + break; + case SUB_OPCODE_MACRO_LABELPC: + *cur_reloc = RELOC_INFO_LABELPC(r_insn.macro.label, + cur_insn_addr); + break; + default: + assert(0 && "invalid sub_opcode for macro insn"); } ++read_ptr; assert(read_ptr != end && "program can not end with macro insn"); @@ -250,20 +249,20 @@ esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* prog // step 3: sort relocations array qsort(reloc_info, macro_count, sizeof(reloc_info_t), - reloc_sort_func); + reloc_sort_func); // step 4: walk relocations array and fix instructions reloc_info_t* reloc_end = reloc_info + macro_count; cur_reloc = reloc_info; - while(cur_reloc < reloc_end) { + while (cur_reloc < reloc_end) { reloc_info_t label_info = *cur_reloc; assert(label_info.type == RELOC_TYPE_LABEL); ++cur_reloc; while (cur_reloc < reloc_end) { if (cur_reloc->type == RELOC_TYPE_LABEL) { - if(cur_reloc->label == label_info.label) { + if (cur_reloc->label == label_info.label) { ESP_LOGE(TAG, "duplicate label definition: %d", - label_info.label); + label_info.label); free(reloc_info); return ESP_ERR_ULP_DUPLICATE_LABEL; } @@ -271,12 +270,12 @@ esp_err_t ulp_process_macros_and_load(uint32_t load_addr, const ulp_insn_t* prog } if (cur_reloc->label != label_info.label) { ESP_LOGE(TAG, "branch to an inexistent label: %d", - cur_reloc->label); + cur_reloc->label); free(reloc_info); return ESP_ERR_ULP_UNDEFINED_LABEL; } esp_err_t rc = do_single_reloc(output_program, load_addr, - label_info, *cur_reloc); + label_info, *cur_reloc); if (rc != ESP_OK) { free(reloc_info); return rc; diff --git a/components/ulp/ulp_riscv/include/ulp_riscv.h b/components/ulp/ulp_riscv/include/ulp_riscv.h index a92a27d2ff..39836a58b6 100644 --- a/components/ulp/ulp_riscv/include/ulp_riscv.h +++ b/components/ulp/ulp_riscv/include/ulp_riscv.h @@ -112,7 +112,6 @@ esp_err_t ulp_riscv_load_binary(const uint8_t* program_binary, size_t program_si */ void ulp_riscv_timer_stop(void); - /** * @brief Resumes the ULP timer * @@ -121,7 +120,6 @@ void ulp_riscv_timer_stop(void); */ void ulp_riscv_timer_resume(void); - /** * @brief Halts the program currently running on the ULP-RISC-V * diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h index 41c4dbbc2f..7deffbaab7 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_gpio.h @@ -63,13 +63,13 @@ static inline void ulp_riscv_gpio_init(gpio_num_t gpio_num) #elif CONFIG_IDF_TARGET_ESP32S3 SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_IOMUX_CLK_EN_M); #endif - SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_MUX_SEL); - REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_FUN_SEL, 0); + SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_MUX_SEL); + REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_FUN_SEL, 0); } static inline void ulp_riscv_gpio_deinit(gpio_num_t gpio_num) { - CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_MUX_SEL); + CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_MUX_SEL); } static inline void ulp_riscv_gpio_output_enable(gpio_num_t gpio_num) @@ -84,12 +84,12 @@ static inline void ulp_riscv_gpio_output_disable(gpio_num_t gpio_num) static inline void ulp_riscv_gpio_input_enable(gpio_num_t gpio_num) { - SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_FUN_IE); + SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_FUN_IE); } static inline void ulp_riscv_gpio_input_disable(gpio_num_t gpio_num) { - CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_FUN_IE); + CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_FUN_IE); } static inline void ulp_riscv_gpio_output_level(gpio_num_t gpio_num, uint8_t level) @@ -108,27 +108,27 @@ static inline uint8_t ulp_riscv_gpio_get_level(gpio_num_t gpio_num) static inline void ulp_riscv_gpio_set_output_mode(gpio_num_t gpio_num, rtc_io_out_mode_t mode) { - REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_DRV, mode); + REG_SET_FIELD(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_DRV, mode); } static inline void ulp_riscv_gpio_pullup(gpio_num_t gpio_num) { - SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_RUE); + SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_RUE); } static inline void ulp_riscv_gpio_pullup_disable(gpio_num_t gpio_num) { - CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_RUE); + CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_RUE); } static inline void ulp_riscv_gpio_pulldown(gpio_num_t gpio_num) { - SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_RDE); + SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_RDE); } static inline void ulp_riscv_gpio_pulldown_disable(gpio_num_t gpio_num) { - CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num*4, RTC_IO_TOUCH_PAD0_RDE); + CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD0_REG + gpio_num * 4, RTC_IO_TOUCH_PAD0_RDE); } /** diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h index 4f403058a1..acfd24588b 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_lock_ulp_core.h @@ -11,7 +11,6 @@ extern "C" { #endif - /** * @brief Locks are based on the Peterson's algorithm, https://en.wikipedia.org/wiki/Peterson%27s_algorithm * diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_print.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_print.h index 2085556359..39d7fa2aee 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_print.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_print.h @@ -13,7 +13,6 @@ extern "C" { /* Underlying driver function for printing a char, e.g. over UART */ typedef void (*putc_fn_t)(const void *ctx, const char c); - /** * @brief Installs a print driver that will be used for ulp_riscv_print calls * @@ -22,7 +21,6 @@ typedef void (*putc_fn_t)(const void *ctx, const char c); */ void ulp_riscv_print_install(putc_fn_t putc, void *putc_ctx); - /** * @brief Prints a null-terminated string * @@ -30,7 +28,6 @@ void ulp_riscv_print_install(putc_fn_t putc, void *putc_ctx); */ void ulp_riscv_print_str(const char *str); - /** * @brief Prints a hex number. Does not print 0x, only the digits * diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h index 52e7925b8e..6bff84e0ef 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_register_ops.h @@ -17,7 +17,7 @@ extern "C" { * When COCPU accesses the RTC memory, dont need to convert the access address. */ #define WRITE_RTC_MEM(addr, val) (*((volatile int*)(addr))) = (int) (val) -#define READ_RTC_MEM(addr) (*(volatile int*)(addr)) +#define READ_RTC_MEM(addr) (*(volatile int*)(addr)) /* * When COCPU accesses the RTC register, it needs to convert the access address. diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h index 86bdd504f5..2556e76635 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_touch_ulp_core.h @@ -83,7 +83,6 @@ esp_err_t ulp_riscv_touch_pad_sleep_channel_read_benchmark(touch_pad_t touch_num */ esp_err_t ulp_riscv_touch_pad_sleep_channel_read_smooth(touch_pad_t touch_num, uint32_t *smooth_data); - /** * @brief Reset benchmark of touch sensor sleep channel. * @note Refer `touch_pad_sleep_channel_reset_benchmark()` for more details diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_uart_ulp_core.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_uart_ulp_core.h index 42c22a9a81..53dcde55c2 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_uart_ulp_core.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_uart_ulp_core.h @@ -22,7 +22,6 @@ typedef struct { gpio_num_t tx_pin; // TX pin number } ulp_riscv_uart_t; // Context for the driver, initialized by ulp_riscv_uart_init - /** * @brief Initialize the bit-banged UART driver * diff --git a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h index 274395d3f1..e8a07d3c4d 100644 --- a/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h +++ b/components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_utils.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -67,7 +67,6 @@ void __attribute__((__noreturn__)) ulp_riscv_halt(void); */ void ulp_riscv_timer_stop(void); - /** * @brief Resumes the ULP timer * @@ -76,10 +75,9 @@ void ulp_riscv_timer_stop(void); */ void ulp_riscv_timer_resume(void); -#define ULP_RISCV_GET_CCOUNT() ({ int __ccount; \ - asm volatile("rdcycle %0;" : "=r"(__ccount)); \ - __ccount; }) - +#define ULP_RISCV_GET_CCOUNT() ({ int __ccount; \ + asm volatile("rdcycle %0;" : "=r"(__ccount)); \ + __ccount; }) #if CONFIG_IDF_TARGET_ESP32S2 /* These are only approximate default numbers, the default frequency @@ -99,7 +97,7 @@ void ulp_riscv_timer_resume(void); void static inline ulp_riscv_delay_cycles(uint32_t cycles) { uint32_t start = ULP_RISCV_GET_CCOUNT(); - /* Off with an estimate of cycles in this function to improve accuracy */ + /* Off with an estimate of cycles in this function to improve accuracy */ uint32_t end = start + cycles - 20; while (ULP_RISCV_GET_CCOUNT() < end) { diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c index 61de5a30c0..43d370644a 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_gpio.c @@ -21,7 +21,7 @@ esp_err_t ulp_riscv_gpio_isr_register(gpio_num_t gpio_num, ulp_riscv_gpio_int_ty } /* Set the interrupt type */ - REG_SET_FIELD(RTC_GPIO_PIN0_REG + 4*gpio_num, RTC_GPIO_PIN0_INT_TYPE, intr_type); + REG_SET_FIELD(RTC_GPIO_PIN0_REG + 4 * gpio_num, RTC_GPIO_PIN0_INT_TYPE, intr_type); /* Set the interrupt handler */ return ulp_riscv_intr_alloc(ULP_RISCV_RTCIO0_INTR_SOURCE + gpio_num, handler, arg); diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c index 99263d7c6b..1da395304e 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -43,27 +43,27 @@ * |----------|----------|---------|---------|----------|------------|---------| */ static void ulp_riscv_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t ack_val, - uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num) + uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num) { - uint32_t reg_addr = RTC_I2C_CMD0_REG + 4*cmd_idx; + uint32_t reg_addr = RTC_I2C_CMD0_REG + 4 * cmd_idx; CLEAR_PERI_REG_MASK(reg_addr, 0xFFFFFFFF); WRITE_PERI_REG(reg_addr, - (0 << 31) | // CMD Done + (0 << 31) | // CMD Done - ((op_code & 0x3) << 11) | // Opcode + ((op_code & 0x3) << 11) | // Opcode - ((ack_val & 0x1) << 10) | // ACK bit sent by I2C controller during READ. - // Ignored during RSTART, STOP, END and WRITE cmds. + ((ack_val & 0x1) << 10) | // ACK bit sent by I2C controller during READ. + // Ignored during RSTART, STOP, END and WRITE cmds. - ((ack_expected & 0x1) << 9) | // ACK bit expected by I2C controller during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. + ((ack_expected & 0x1) << 9) | // ACK bit expected by I2C controller during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. - ((ack_check_en & 0x1) << 8) | // I2C controller verifies that the ACK bit sent by the slave device matches - // the ACK expected bit during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. - ((byte_num & 0xFF) << 0)); // Byte Num + ((ack_check_en & 0x1) << 8) | // I2C controller verifies that the ACK bit sent by the slave device matches + // the ACK expected bit during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. + ((byte_num & 0xFF) << 0)); // Byte Num } static inline int32_t ulp_riscv_i2c_wait_for_interrupt(int32_t ticks_to_wait) @@ -76,9 +76,9 @@ static inline int32_t ulp_riscv_i2c_wait_for_interrupt(int32_t ticks_to_wait) /* Return 0 if Tx or Rx data interrupt bits are set. */ if ((status & RTC_I2C_TX_DATA_INT_ST) || - (status & RTC_I2C_RX_DATA_INT_ST)) { + (status & RTC_I2C_RX_DATA_INT_ST)) { return 0; - /* In case of error status, break and return -1 */ + /* In case of error status, break and return -1 */ #if CONFIG_IDF_TARGET_ESP32S2 } else if ((status & RTC_I2C_TIMEOUT_INT_ST) || #elif CONFIG_IDF_TARGET_ESP32S3 @@ -176,7 +176,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size) for (i = 0; i < size; i++) { /* Poll for RTC I2C Rx Data interrupt bit to be set */ - if(!ulp_riscv_i2c_wait_for_interrupt(ULP_RISCV_I2C_RW_TIMEOUT)) { + if (!ulp_riscv_i2c_wait_for_interrupt(ULP_RISCV_I2C_RW_TIMEOUT)) { /* Read the data * * Unfortunately, the RTC I2C has no fifo buffer to help us with reading and storing diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_print.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_print.c index 12e48fadd9..ae6ce8c1ee 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_print.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_print.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -25,7 +25,7 @@ void ulp_riscv_print_str(const char *str) } for (int i = 0; str[i] != 0; i++) { - s_print_ctx.putc(s_print_ctx.putc_ctx ,str[i]); + s_print_ctx.putc(s_print_ctx.putc_ctx, str[i]); } } @@ -42,9 +42,9 @@ void ulp_riscv_print_hex(int h) for (x = 0; x < 8; x++) { c = (h >> 28) & 0xf; // extract the leftmost byte if (c < 10) { - s_print_ctx.putc(s_print_ctx.putc_ctx ,'0' + c); + s_print_ctx.putc(s_print_ctx.putc_ctx, '0' + c); } else { - s_print_ctx.putc(s_print_ctx.putc_ctx ,'a' + c - 10); + s_print_ctx.putc(s_print_ctx.putc_ctx, 'a' + c - 10); } h <<= 4; // move the 2nd leftmost byte to the left, to be extracted next } diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_uart.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_uart.c index 94006659d6..b9d127f66e 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_uart.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_uart.c @@ -33,10 +33,10 @@ void ulp_riscv_uart_putc(const ulp_riscv_uart_t *uart, const char c) { ulp_riscv_gpio_output_level(uart->tx_pin, 0); - for (int i = 0; i<8; i++) { + for (int i = 0; i < 8; i++) { /* Offset the delay to account for cycles spent setting the bit */ ulp_riscv_delay_cycles(uart->bit_duration_cycles - 100); - if ( (1 << i) & c) { + if ((1 << i) & c) { ulp_riscv_gpio_output_level(uart->tx_pin, 1); } else { ulp_riscv_gpio_output_level(uart->tx_pin, 0); diff --git a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c index e1b88676b2..c4b8027fe7 100644 --- a/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c +++ b/components/ulp/ulp_riscv/ulp_core/ulp_riscv_utils.c @@ -30,7 +30,7 @@ void ulp_riscv_halt(void) /* Suspends the ulp operation and reset the ULP core. Must be the final operation before going to halt. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN); - while(1); + while (1); } void ulp_riscv_timer_stop(void) @@ -55,7 +55,7 @@ void ulp_riscv_enable_sw_intr(intr_handler_t handler, void *arg) /* Register interrupt handler */ if (handler) { - ulp_riscv_intr_alloc(ULP_RISCV_SW_INTR_SOURCE, handler, arg); + ulp_riscv_intr_alloc(ULP_RISCV_SW_INTR_SOURCE, handler, arg); } } diff --git a/components/ulp/ulp_riscv/ulp_riscv.c b/components/ulp/ulp_riscv/ulp_riscv.c index f160c2e10c..d958c4bc0b 100644 --- a/components/ulp/ulp_riscv/ulp_riscv.c +++ b/components/ulp/ulp_riscv/ulp_riscv.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -78,18 +78,18 @@ static esp_err_t ulp_riscv_config_wakeup_source(ulp_riscv_wakeup_source_t wakeup esp_err_t ret = ESP_OK; switch (wakeup_source) { - case ULP_RISCV_WAKEUP_SOURCE_TIMER: - /* start ULP_TIMER */ - CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); - SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); - break; + case ULP_RISCV_WAKEUP_SOURCE_TIMER: + /* start ULP_TIMER */ + CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_CTRL_REG, RTC_CNTL_ULP_CP_FORCE_START_TOP); + SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); + break; - case ULP_RISCV_WAKEUP_SOURCE_GPIO: - SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA); - break; + case ULP_RISCV_WAKEUP_SOURCE_GPIO: + SET_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA); + break; - default: - ret = ESP_ERR_INVALID_ARG; + default: + ret = ESP_ERR_INVALID_ARG; } return ret; @@ -99,13 +99,12 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) { esp_err_t ret = ESP_OK; - #if CONFIG_IDF_TARGET_ESP32S2 /* Reset COCPU when power on. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - /* The coprocessor cpu trap signal doesnt have a stable reset value, - force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ + /* The coprocessor cpu trap signal doesnt have a stable reset value, + force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); /* Disable ULP timer */ @@ -124,11 +123,10 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) /* Reset COCPU when power on. */ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); - /* The coprocessor cpu trap signal doesnt have a stable reset value, - force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ + /* The coprocessor cpu trap signal doesnt have a stable reset value, + force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); - /* Disable ULP timer */ CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); /* wait for at least 1 RTC_SLOW_CLK cycle */ @@ -159,7 +157,6 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg) esp_rom_delay_us(20); REG_WRITE(RTC_CNTL_INT_CLR_REG, RTC_CNTL_COCPU_INT_CLR | RTC_CNTL_COCPU_TRAP_INT_CLR | RTC_CNTL_ULP_CP_INT_CLR); - #endif return ret; diff --git a/components/ulp/ulp_riscv/ulp_riscv_i2c.c b/components/ulp/ulp_riscv/ulp_riscv_i2c.c index 816cab3ae9..d434cb4b8e 100644 --- a/components/ulp/ulp_riscv/ulp_riscv_i2c.c +++ b/components/ulp/ulp_riscv/ulp_riscv_i2c.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -200,7 +200,7 @@ static esp_err_t i2c_set_timing(const ulp_riscv_i2c_cfg_t *cfg) * |----------|----------|---------|---------|----------|------------|---------| */ static void ulp_riscv_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t ack_val, - uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num) + uint8_t ack_expected, uint8_t ack_check_en, uint8_t byte_num) { #if CONFIG_IDF_TARGET_ESP32S2 /* Reset cmd register */ @@ -210,12 +210,12 @@ static void ulp_riscv_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t i2c_dev->command[cmd_idx].done = 0; // CMD Done i2c_dev->command[cmd_idx].op_code = op_code; // Opcode i2c_dev->command[cmd_idx].ack_val = ack_val; // ACK bit sent by I2C controller during READ. - // Ignored during RSTART, STOP, END and WRITE cmds. + // Ignored during RSTART, STOP, END and WRITE cmds. i2c_dev->command[cmd_idx].ack_exp = ack_expected; // ACK bit expected by I2C controller during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. + // Ignored during RSTART, STOP, END and READ cmds. i2c_dev->command[cmd_idx].ack_en = ack_check_en; // I2C controller verifies that the ACK bit sent by the - // slave device matches the ACK expected bit during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. + // slave device matches the ACK expected bit during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. HAL_FORCE_MODIFY_U32_REG_FIELD(i2c_dev->command[cmd_idx], byte_num, byte_num); // Byte Num #elif CONFIG_IDF_TARGET_ESP32S3 @@ -226,12 +226,12 @@ static void ulp_riscv_i2c_format_cmd(uint32_t cmd_idx, uint8_t op_code, uint8_t i2c_dev->i2c_cmd[cmd_idx].i2c_command_done = 0; // CMD Done i2c_dev->i2c_cmd[cmd_idx].i2c_op_code = op_code; // Opcode i2c_dev->i2c_cmd[cmd_idx].i2c_ack_val = ack_val; // ACK bit sent by I2C controller during READ. - // Ignored during RSTART, STOP, END and WRITE cmds. + // Ignored during RSTART, STOP, END and WRITE cmds. i2c_dev->i2c_cmd[cmd_idx].i2c_ack_exp = ack_expected; // ACK bit expected by I2C controller during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. + // Ignored during RSTART, STOP, END and READ cmds. i2c_dev->i2c_cmd[cmd_idx].i2c_ack_en = ack_check_en; // I2C controller verifies that the ACK bit sent by the - // slave device matches the ACK expected bit during WRITE. - // Ignored during RSTART, STOP, END and READ cmds. + // slave device matches the ACK expected bit during WRITE. + // Ignored during RSTART, STOP, END and READ cmds. HAL_FORCE_MODIFY_U32_REG_FIELD(i2c_dev->i2c_cmd[cmd_idx], i2c_byte_num, byte_num); // Byte Num #endif // CONFIG_IDF_TARGET_ESP32S2 } @@ -247,10 +247,10 @@ static inline esp_err_t ulp_riscv_i2c_wait_for_interrupt(int32_t ticks_to_wait) /* Return ESP_OK if Tx or Rx data interrupt bits are set. */ if ((status & RTC_I2C_TX_DATA_INT_ST) || - (status & RTC_I2C_RX_DATA_INT_ST)) { + (status & RTC_I2C_RX_DATA_INT_ST)) { ret = ESP_OK; break; - /* In case of error status, break and return ESP_FAIL */ + /* In case of error status, break and return ESP_FAIL */ #if CONFIG_IDF_TARGET_ESP32S2 } else if ((status & RTC_I2C_TIMEOUT_INT_ST) || #elif CONFIG_IDF_TARGET_ESP32S3 @@ -501,13 +501,13 @@ esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg) /* Enable RTC I2C interrupts */ SET_PERI_REG_MASK(RTC_I2C_INT_ENA_REG, RTC_I2C_RX_DATA_INT_ENA | - RTC_I2C_TX_DATA_INT_ENA | - RTC_I2C_ARBITRATION_LOST_INT_ENA | - RTC_I2C_ACK_ERR_INT_ENA | + RTC_I2C_TX_DATA_INT_ENA | + RTC_I2C_ARBITRATION_LOST_INT_ENA | + RTC_I2C_ACK_ERR_INT_ENA | #if CONFIG_IDF_TARGET_ESP32S2 - RTC_I2C_TIMEOUT_INT_ENA); + RTC_I2C_TIMEOUT_INT_ENA); #elif CONFIG_IDF_TARGET_ESP32S3 - RTC_I2C_TIME_OUT_INT_ENA); + RTC_I2C_TIME_OUT_INT_ENA); #endif // CONFIG_IDF_TARGET_ESP32S2 return ESP_OK; diff --git a/tools/ci/astyle-rules.yml b/tools/ci/astyle-rules.yml index d2866b02a7..6d42d174fb 100644 --- a/tools/ci/astyle-rules.yml +++ b/tools/ci/astyle-rules.yml @@ -107,7 +107,6 @@ components_not_formatted_temporary: - "/components/spiffs/" - "/components/tcp_transport/" - "/components/touch_element/" - - "/components/ulp/" - "/components/unity/" - "/components/vfs/" - "/components/wear_levelling/"