diff --git a/components/soc/esp32s2/include/soc/rmt_reg.h b/components/soc/esp32s2/include/soc/rmt_reg.h index 8225f6a687..351eac3b5f 100644 --- a/components/soc/esp32s2/include/soc/rmt_reg.h +++ b/components/soc/esp32s2/include/soc/rmt_reg.h @@ -28,37 +28,37 @@ extern "C" { * Read and write data for channel 1 via APB FIFO */ #define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) -/** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0; +/** RMT_CH1_DATA : RO; bitpos: [31:0]; default: 0; * This register is used to read and write data for channel 1 via APB FIFO. */ -#define RMT_CH0_DATA 0xFFFFFFFFU -#define RMT_CH0_DATA_M (RMT_CH0_DATA_V << RMT_CH0_DATA_S) -#define RMT_CH0_DATA_V 0xFFFFFFFFU -#define RMT_CH0_DATA_S 0 +#define RMT_CH1_DATA 0xFFFFFFFFU +#define RMT_CH1_DATA_M (RMT_CH1_DATA_V << RMT_CH1_DATA_S) +#define RMT_CH1_DATA_V 0xFFFFFFFFU +#define RMT_CH1_DATA_S 0 /** RMT_CH2DATA_REG register * Read and write data for channel 2 via APB FIFO */ #define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) -/** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0; +/** RMT_CH2_DATA : RO; bitpos: [31:0]; default: 0; * This register is used to read and write data for channel 2 via APB FIFO. */ -#define RMT_CH0_DATA 0xFFFFFFFFU -#define RMT_CH0_DATA_M (RMT_CH0_DATA_V << RMT_CH0_DATA_S) -#define RMT_CH0_DATA_V 0xFFFFFFFFU -#define RMT_CH0_DATA_S 0 +#define RMT_CH2_DATA 0xFFFFFFFFU +#define RMT_CH2_DATA_M (RMT_CH2_DATA_V << RMT_CH2_DATA_S) +#define RMT_CH2_DATA_V 0xFFFFFFFFU +#define RMT_CH2_DATA_S 0 /** RMT_CH3DATA_REG register * Read and write data for channel 3 via APB FIFO */ #define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) -/** RMT_CH0_DATA : RO; bitpos: [31:0]; default: 0; +/** RMT_CH3_DATA : RO; bitpos: [31:0]; default: 0; * This register is used to read and write data for channel 3 via APB FIFO. */ -#define RMT_CH0_DATA 0xFFFFFFFFU -#define RMT_CH0_DATA_M (RMT_CH0_DATA_V << RMT_CH0_DATA_S) -#define RMT_CH0_DATA_V 0xFFFFFFFFU -#define RMT_CH0_DATA_S 0 +#define RMT_CH3_DATA 0xFFFFFFFFU +#define RMT_CH3_DATA_M (RMT_CH3_DATA_V << RMT_CH3_DATA_S) +#define RMT_CH3_DATA_V 0xFFFFFFFFU +#define RMT_CH3_DATA_S 0 /** RMT_CH0CONF0_REG register * Channel 0 configuration register 0 @@ -234,511 +234,511 @@ extern "C" { * Channel 1 configuration register 0 */ #define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x18) -/** RMT_DIV_CNT_CH0 : R/W; bitpos: [7:0]; default: 2; +/** RMT_DIV_CNT_CH1 : R/W; bitpos: [7:0]; default: 2; * This field is used to configure clock divider for channel 1. */ -#define RMT_DIV_CNT_CH0 0x000000FFU -#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) -#define RMT_DIV_CNT_CH0_V 0x000000FFU -#define RMT_DIV_CNT_CH0_S 0 -/** RMT_IDLE_THRES_CH0 : R/W; bitpos: [23:8]; default: 4096; +#define RMT_DIV_CNT_CH1 0x000000FFU +#define RMT_DIV_CNT_CH1_M (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S) +#define RMT_DIV_CNT_CH1_V 0x000000FFU +#define RMT_DIV_CNT_CH1_S 0 +/** RMT_IDLE_THRES_CH1 : R/W; bitpos: [23:8]; default: 4096; * Receiving ends when no edge is detected on input signals for continuous clock * cycles longer than this field value. */ -#define RMT_IDLE_THRES_CH0 0x0000FFFFU -#define RMT_IDLE_THRES_CH0_M (RMT_IDLE_THRES_CH0_V << RMT_IDLE_THRES_CH0_S) -#define RMT_IDLE_THRES_CH0_V 0x0000FFFFU -#define RMT_IDLE_THRES_CH0_S 8 -/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [26:24]; default: 1; +#define RMT_IDLE_THRES_CH1 0x0000FFFFU +#define RMT_IDLE_THRES_CH1_M (RMT_IDLE_THRES_CH1_V << RMT_IDLE_THRES_CH1_S) +#define RMT_IDLE_THRES_CH1_V 0x0000FFFFU +#define RMT_IDLE_THRES_CH1_S 8 +/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [26:24]; default: 1; * This field is used to configure the maximum blocks allocated to channel 1. The * valid range is from 1 ~ 4-1. */ -#define RMT_MEM_SIZE_CH0 0x00000007U -#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) -#define RMT_MEM_SIZE_CH0_V 0x00000007U -#define RMT_MEM_SIZE_CH0_S 24 -/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [27]; default: 1; +#define RMT_MEM_SIZE_CH1 0x00000007U +#define RMT_MEM_SIZE_CH1_M (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S) +#define RMT_MEM_SIZE_CH1_V 0x00000007U +#define RMT_MEM_SIZE_CH1_S 24 +/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [27]; default: 1; * 1: Add carrier modulation on output signals only at data sending state for channel * 1. 0: Add carrier modulation on signals at all states for channel 1. States here * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CH1 is set to 1. */ -#define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) -#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) -#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U -#define RMT_CARRIER_EFF_EN_CH0_S 27 -/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [28]; default: 1; +#define RMT_CARRIER_EFF_EN_CH1 (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH1_M (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S) +#define RMT_CARRIER_EFF_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH1_S 27 +/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [28]; default: 1; * This bit is used to enable carrier modulation for channel 1. 1: Add carrier * modulation on output signals. 0: No carrier modulation is added on output signals. */ -#define RMT_CARRIER_EN_CH0 (BIT(28)) -#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) -#define RMT_CARRIER_EN_CH0_V 0x00000001U -#define RMT_CARRIER_EN_CH0_S 28 -/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [29]; default: 1; +#define RMT_CARRIER_EN_CH1 (BIT(28)) +#define RMT_CARRIER_EN_CH1_M (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S) +#define RMT_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EN_CH1_S 28 +/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [29]; default: 1; * This bit is used to configure the position of carrier wave for channel 1. * * 1'h0: Add carrier wave on low-level output signals. * * 1'h1: Add carrier wave on high-level output signals. */ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) -#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U -#define RMT_CARRIER_OUT_LV_CH0_S 29 +#define RMT_CARRIER_OUT_LV_CH1 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH1_M (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S) +#define RMT_CARRIER_OUT_LV_CH1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH1_S 29 /** RMT_CH1CONF1_REG register * Channel 1 configuration register 1 */ #define RMT_CH1CONF1_REG (DR_REG_RMT_BASE + 0x1c) -/** RMT_TX_START_CH0 : R/W; bitpos: [0]; default: 0; +/** RMT_TX_START_CH1 : R/W; bitpos: [0]; default: 0; * Set this bit to start sending data on channel 1. */ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) -#define RMT_TX_START_CH0_V 0x00000001U -#define RMT_TX_START_CH0_S 0 -/** RMT_RX_EN_CH0 : R/W; bitpos: [1]; default: 0; +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S) +#define RMT_TX_START_CH1_V 0x00000001U +#define RMT_TX_START_CH1_S 0 +/** RMT_RX_EN_CH1 : R/W; bitpos: [1]; default: 0; * Set this bit to enable receiver to receive data on channel 1. */ -#define RMT_RX_EN_CH0 (BIT(1)) -#define RMT_RX_EN_CH0_M (RMT_RX_EN_CH0_V << RMT_RX_EN_CH0_S) -#define RMT_RX_EN_CH0_V 0x00000001U -#define RMT_RX_EN_CH0_S 1 -/** RMT_MEM_WR_RST_CH0 : WO; bitpos: [2]; default: 0; +#define RMT_RX_EN_CH1 (BIT(1)) +#define RMT_RX_EN_CH1_M (RMT_RX_EN_CH1_V << RMT_RX_EN_CH1_S) +#define RMT_RX_EN_CH1_V 0x00000001U +#define RMT_RX_EN_CH1_S 1 +/** RMT_MEM_WR_RST_CH1 : WO; bitpos: [2]; default: 0; * Set this bit to reset RAM write address accessed by the receiver for channel 1. */ -#define RMT_MEM_WR_RST_CH0 (BIT(2)) -#define RMT_MEM_WR_RST_CH0_M (RMT_MEM_WR_RST_CH0_V << RMT_MEM_WR_RST_CH0_S) -#define RMT_MEM_WR_RST_CH0_V 0x00000001U -#define RMT_MEM_WR_RST_CH0_S 2 -/** RMT_MEM_RD_RST_CH0 : WO; bitpos: [3]; default: 0; +#define RMT_MEM_WR_RST_CH1 (BIT(2)) +#define RMT_MEM_WR_RST_CH1_M (RMT_MEM_WR_RST_CH1_V << RMT_MEM_WR_RST_CH1_S) +#define RMT_MEM_WR_RST_CH1_V 0x00000001U +#define RMT_MEM_WR_RST_CH1_S 2 +/** RMT_MEM_RD_RST_CH1 : WO; bitpos: [3]; default: 0; * Set this bit to reset RAM read address accessed by the transmitter for channel 1. */ -#define RMT_MEM_RD_RST_CH0 (BIT(3)) -#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) -#define RMT_MEM_RD_RST_CH0_V 0x00000001U -#define RMT_MEM_RD_RST_CH0_S 3 -/** RMT_APB_MEM_RST_CH0 : WO; bitpos: [4]; default: 0; +#define RMT_MEM_RD_RST_CH1 (BIT(3)) +#define RMT_MEM_RD_RST_CH1_M (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S) +#define RMT_MEM_RD_RST_CH1_V 0x00000001U +#define RMT_MEM_RD_RST_CH1_S 3 +/** RMT_APB_MEM_RST_CH1 : WO; bitpos: [4]; default: 0; * Set this bit to reset W/R ram address for channel 1 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_CH0 (BIT(4)) -#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) -#define RMT_APB_MEM_RST_CH0_V 0x00000001U -#define RMT_APB_MEM_RST_CH0_S 4 -/** RMT_MEM_OWNER_CH0 : R/W; bitpos: [5]; default: 1; +#define RMT_APB_MEM_RST_CH1 (BIT(4)) +#define RMT_APB_MEM_RST_CH1_M (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S) +#define RMT_APB_MEM_RST_CH1_V 0x00000001U +#define RMT_APB_MEM_RST_CH1_S 4 +/** RMT_MEM_OWNER_CH1 : R/W; bitpos: [5]; default: 1; * This bit marks the ownership of channel 1's RAM block. * * 1'h1: Receiver is using the RAM. * * 1'h0: Transmitter is using the RAM. */ -#define RMT_MEM_OWNER_CH0 (BIT(5)) -#define RMT_MEM_OWNER_CH0_M (RMT_MEM_OWNER_CH0_V << RMT_MEM_OWNER_CH0_S) -#define RMT_MEM_OWNER_CH0_V 0x00000001U -#define RMT_MEM_OWNER_CH0_S 5 -/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [6]; default: 0; +#define RMT_MEM_OWNER_CH1 (BIT(5)) +#define RMT_MEM_OWNER_CH1_M (RMT_MEM_OWNER_CH1_V << RMT_MEM_OWNER_CH1_S) +#define RMT_MEM_OWNER_CH1_V 0x00000001U +#define RMT_MEM_OWNER_CH1_S 5 +/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [6]; default: 0; * Set this bit to restart transmission in continuous node from the first data in * channel 1. */ -#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) -#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U -#define RMT_TX_CONTI_MODE_CH0_S 6 -/** RMT_RX_FILTER_EN_CH0 : R/W; bitpos: [7]; default: 0; +#define RMT_TX_CONTI_MODE_CH1 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH1_M (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S) +#define RMT_TX_CONTI_MODE_CH1_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH1_S 6 +/** RMT_RX_FILTER_EN_CH1 : R/W; bitpos: [7]; default: 0; * Set this bit to enable the receiver's filter for channel 1. */ -#define RMT_RX_FILTER_EN_CH0 (BIT(7)) -#define RMT_RX_FILTER_EN_CH0_M (RMT_RX_FILTER_EN_CH0_V << RMT_RX_FILTER_EN_CH0_S) -#define RMT_RX_FILTER_EN_CH0_V 0x00000001U -#define RMT_RX_FILTER_EN_CH0_S 7 -/** RMT_RX_FILTER_THRES_CH0 : R/W; bitpos: [15:8]; default: 15; +#define RMT_RX_FILTER_EN_CH1 (BIT(7)) +#define RMT_RX_FILTER_EN_CH1_M (RMT_RX_FILTER_EN_CH1_V << RMT_RX_FILTER_EN_CH1_S) +#define RMT_RX_FILTER_EN_CH1_V 0x00000001U +#define RMT_RX_FILTER_EN_CH1_S 7 +/** RMT_RX_FILTER_THRES_CH1 : R/W; bitpos: [15:8]; default: 15; * Set this field to ignore the input pulse when its width is less than * RMT_RX_FILTER_THRES_CH1 APB clock cycles in receive mode. */ -#define RMT_RX_FILTER_THRES_CH0 0x000000FFU -#define RMT_RX_FILTER_THRES_CH0_M (RMT_RX_FILTER_THRES_CH0_V << RMT_RX_FILTER_THRES_CH0_S) -#define RMT_RX_FILTER_THRES_CH0_V 0x000000FFU -#define RMT_RX_FILTER_THRES_CH0_S 8 -/** RMT_CHK_RX_CARRIER_EN_CH0 : R/W; bitpos: [16]; default: 0; +#define RMT_RX_FILTER_THRES_CH1 0x000000FFU +#define RMT_RX_FILTER_THRES_CH1_M (RMT_RX_FILTER_THRES_CH1_V << RMT_RX_FILTER_THRES_CH1_S) +#define RMT_RX_FILTER_THRES_CH1_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH1_S 8 +/** RMT_CHK_RX_CARRIER_EN_CH1 : R/W; bitpos: [16]; default: 0; * Set this bit to enable memory loop read mode when carrier modulation is enabled for * channel 1. */ -#define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) -#define RMT_CHK_RX_CARRIER_EN_CH0_M (RMT_CHK_RX_CARRIER_EN_CH0_V << RMT_CHK_RX_CARRIER_EN_CH0_S) -#define RMT_CHK_RX_CARRIER_EN_CH0_V 0x00000001U -#define RMT_CHK_RX_CARRIER_EN_CH0_S 16 -/** RMT_REF_ALWAYS_ON_CH0 : R/W; bitpos: [17]; default: 0; +#define RMT_CHK_RX_CARRIER_EN_CH1 (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH1_M (RMT_CHK_RX_CARRIER_EN_CH1_V << RMT_CHK_RX_CARRIER_EN_CH1_S) +#define RMT_CHK_RX_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CHK_RX_CARRIER_EN_CH1_S 16 +/** RMT_REF_ALWAYS_ON_CH1 : R/W; bitpos: [17]; default: 0; * Set this bit to select a base clock for channel 1. * * 1'h1: APB_CLK 1'h0: REF_TICK */ -#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH0_M (RMT_REF_ALWAYS_ON_CH0_V << RMT_REF_ALWAYS_ON_CH0_S) -#define RMT_REF_ALWAYS_ON_CH0_V 0x00000001U -#define RMT_REF_ALWAYS_ON_CH0_S 17 -/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [18]; default: 0; +#define RMT_REF_ALWAYS_ON_CH1 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH1_M (RMT_REF_ALWAYS_ON_CH1_V << RMT_REF_ALWAYS_ON_CH1_S) +#define RMT_REF_ALWAYS_ON_CH1_V 0x00000001U +#define RMT_REF_ALWAYS_ON_CH1_S 17 +/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [18]; default: 0; * This bit configures the level of output signals in channel 1 when the transmitter * is in idle state. */ -#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) -#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U -#define RMT_IDLE_OUT_LV_CH0_S 18 -/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [19]; default: 0; +#define RMT_IDLE_OUT_LV_CH1 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH1_M (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S) +#define RMT_IDLE_OUT_LV_CH1_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH1_S 18 +/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [19]; default: 0; * This is the output enable bit for channel 1 in idle state. */ -#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) -#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U -#define RMT_IDLE_OUT_EN_CH0_S 19 -/** RMT_TX_STOP_CH0 : R/W; bitpos: [20]; default: 0; +#define RMT_IDLE_OUT_EN_CH1 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH1_M (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S) +#define RMT_IDLE_OUT_EN_CH1_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH1_S 19 +/** RMT_TX_STOP_CH1 : R/W; bitpos: [20]; default: 0; * Set this bit to stop the transmitter of channel 1 sending data out. */ -#define RMT_TX_STOP_CH0 (BIT(20)) -#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) -#define RMT_TX_STOP_CH0_V 0x00000001U -#define RMT_TX_STOP_CH0_S 20 +#define RMT_TX_STOP_CH1 (BIT(20)) +#define RMT_TX_STOP_CH1_M (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S) +#define RMT_TX_STOP_CH1_V 0x00000001U +#define RMT_TX_STOP_CH1_S 20 /** RMT_CH2CONF0_REG register * Channel 2 configuration register 0 */ #define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x20) -/** RMT_DIV_CNT_CH0 : R/W; bitpos: [7:0]; default: 2; +/** RMT_DIV_CNT_CH2 : R/W; bitpos: [7:0]; default: 2; * This field is used to configure clock divider for channel 2. */ -#define RMT_DIV_CNT_CH0 0x000000FFU -#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) -#define RMT_DIV_CNT_CH0_V 0x000000FFU -#define RMT_DIV_CNT_CH0_S 0 -/** RMT_IDLE_THRES_CH0 : R/W; bitpos: [23:8]; default: 4096; +#define RMT_DIV_CNT_CH2 0x000000FFU +#define RMT_DIV_CNT_CH2_M (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S) +#define RMT_DIV_CNT_CH2_V 0x000000FFU +#define RMT_DIV_CNT_CH2_S 0 +/** RMT_IDLE_THRES_CH2 : R/W; bitpos: [23:8]; default: 4096; * Receiving ends when no edge is detected on input signals for continuous clock * cycles longer than this field value. */ -#define RMT_IDLE_THRES_CH0 0x0000FFFFU -#define RMT_IDLE_THRES_CH0_M (RMT_IDLE_THRES_CH0_V << RMT_IDLE_THRES_CH0_S) -#define RMT_IDLE_THRES_CH0_V 0x0000FFFFU -#define RMT_IDLE_THRES_CH0_S 8 -/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [26:24]; default: 1; +#define RMT_IDLE_THRES_CH2 0x0000FFFFU +#define RMT_IDLE_THRES_CH2_M (RMT_IDLE_THRES_CH2_V << RMT_IDLE_THRES_CH2_S) +#define RMT_IDLE_THRES_CH2_V 0x0000FFFFU +#define RMT_IDLE_THRES_CH2_S 8 +/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [26:24]; default: 1; * This field is used to configure the maximum blocks allocated to channel 2. The * valid range is from 1 ~ 4-2. */ -#define RMT_MEM_SIZE_CH0 0x00000007U -#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) -#define RMT_MEM_SIZE_CH0_V 0x00000007U -#define RMT_MEM_SIZE_CH0_S 24 -/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [27]; default: 1; +#define RMT_MEM_SIZE_CH2 0x00000007U +#define RMT_MEM_SIZE_CH2_M (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S) +#define RMT_MEM_SIZE_CH2_V 0x00000007U +#define RMT_MEM_SIZE_CH2_S 24 +/** RMT_CARRIER_EFF_EN_CH2 : R/W; bitpos: [27]; default: 1; * 1: Add carrier modulation on output signals only at data sending state for channel * 2. 0: Add carrier modulation on signals at all states for channel 2. States here * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CH2 is set to 1. */ -#define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) -#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) -#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U -#define RMT_CARRIER_EFF_EN_CH0_S 27 -/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [28]; default: 1; +#define RMT_CARRIER_EFF_EN_CH2 (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH2_M (RMT_CARRIER_EFF_EN_CH2_V << RMT_CARRIER_EFF_EN_CH2_S) +#define RMT_CARRIER_EFF_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH2_S 27 +/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [28]; default: 1; * This bit is used to enable carrier modulation for channel 2. 1: Add carrier * modulation on output signals. 0: No carrier modulation is added on output signals. */ -#define RMT_CARRIER_EN_CH0 (BIT(28)) -#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) -#define RMT_CARRIER_EN_CH0_V 0x00000001U -#define RMT_CARRIER_EN_CH0_S 28 -/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [29]; default: 1; +#define RMT_CARRIER_EN_CH2 (BIT(28)) +#define RMT_CARRIER_EN_CH2_M (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S) +#define RMT_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EN_CH2_S 28 +/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [29]; default: 1; * This bit is used to configure the position of carrier wave for channel 2. * * 1'h0: Add carrier wave on low-level output signals. * * 1'h1: Add carrier wave on high-level output signals. */ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) -#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U -#define RMT_CARRIER_OUT_LV_CH0_S 29 +#define RMT_CARRIER_OUT_LV_CH2 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH2_M (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S) +#define RMT_CARRIER_OUT_LV_CH2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH2_S 29 /** RMT_CH2CONF1_REG register * Channel 2 configuration register 1 */ #define RMT_CH2CONF1_REG (DR_REG_RMT_BASE + 0x24) -/** RMT_TX_START_CH0 : R/W; bitpos: [0]; default: 0; +/** RMT_TX_START_CH2 : R/W; bitpos: [0]; default: 0; * Set this bit to start sending data on channel 2. */ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) -#define RMT_TX_START_CH0_V 0x00000001U -#define RMT_TX_START_CH0_S 0 -/** RMT_RX_EN_CH0 : R/W; bitpos: [1]; default: 0; +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (RMT_TX_START_CH2_V << RMT_TX_START_CH2_S) +#define RMT_TX_START_CH2_V 0x00000001U +#define RMT_TX_START_CH2_S 0 +/** RMT_RX_EN_CH2 : R/W; bitpos: [1]; default: 0; * Set this bit to enable receiver to receive data on channel 2. */ -#define RMT_RX_EN_CH0 (BIT(1)) -#define RMT_RX_EN_CH0_M (RMT_RX_EN_CH0_V << RMT_RX_EN_CH0_S) -#define RMT_RX_EN_CH0_V 0x00000001U -#define RMT_RX_EN_CH0_S 1 -/** RMT_MEM_WR_RST_CH0 : WO; bitpos: [2]; default: 0; +#define RMT_RX_EN_CH2 (BIT(1)) +#define RMT_RX_EN_CH2_M (RMT_RX_EN_CH2_V << RMT_RX_EN_CH2_S) +#define RMT_RX_EN_CH2_V 0x00000001U +#define RMT_RX_EN_CH2_S 1 +/** RMT_MEM_WR_RST_CH2 : WO; bitpos: [2]; default: 0; * Set this bit to reset RAM write address accessed by the receiver for channel 2. */ -#define RMT_MEM_WR_RST_CH0 (BIT(2)) -#define RMT_MEM_WR_RST_CH0_M (RMT_MEM_WR_RST_CH0_V << RMT_MEM_WR_RST_CH0_S) -#define RMT_MEM_WR_RST_CH0_V 0x00000001U -#define RMT_MEM_WR_RST_CH0_S 2 -/** RMT_MEM_RD_RST_CH0 : WO; bitpos: [3]; default: 0; +#define RMT_MEM_WR_RST_CH2 (BIT(2)) +#define RMT_MEM_WR_RST_CH2_M (RMT_MEM_WR_RST_CH2_V << RMT_MEM_WR_RST_CH2_S) +#define RMT_MEM_WR_RST_CH2_V 0x00000001U +#define RMT_MEM_WR_RST_CH2_S 2 +/** RMT_MEM_RD_RST_CH2 : WO; bitpos: [3]; default: 0; * Set this bit to reset RAM read address accessed by the transmitter for channel 2. */ -#define RMT_MEM_RD_RST_CH0 (BIT(3)) -#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) -#define RMT_MEM_RD_RST_CH0_V 0x00000001U -#define RMT_MEM_RD_RST_CH0_S 3 -/** RMT_APB_MEM_RST_CH0 : WO; bitpos: [4]; default: 0; +#define RMT_MEM_RD_RST_CH2 (BIT(3)) +#define RMT_MEM_RD_RST_CH2_M (RMT_MEM_RD_RST_CH2_V << RMT_MEM_RD_RST_CH2_S) +#define RMT_MEM_RD_RST_CH2_V 0x00000001U +#define RMT_MEM_RD_RST_CH2_S 3 +/** RMT_APB_MEM_RST_CH2 : WO; bitpos: [4]; default: 0; * Set this bit to reset W/R ram address for channel 2 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_CH0 (BIT(4)) -#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) -#define RMT_APB_MEM_RST_CH0_V 0x00000001U -#define RMT_APB_MEM_RST_CH0_S 4 -/** RMT_MEM_OWNER_CH0 : R/W; bitpos: [5]; default: 1; +#define RMT_APB_MEM_RST_CH2 (BIT(4)) +#define RMT_APB_MEM_RST_CH2_M (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S) +#define RMT_APB_MEM_RST_CH2_V 0x00000001U +#define RMT_APB_MEM_RST_CH2_S 4 +/** RMT_MEM_OWNER_CH2 : R/W; bitpos: [5]; default: 1; * This bit marks the ownership of channel 2's RAM block. * * 1'h1: Receiver is using the RAM. * * 1'h0: Transmitter is using the RAM. */ -#define RMT_MEM_OWNER_CH0 (BIT(5)) -#define RMT_MEM_OWNER_CH0_M (RMT_MEM_OWNER_CH0_V << RMT_MEM_OWNER_CH0_S) -#define RMT_MEM_OWNER_CH0_V 0x00000001U -#define RMT_MEM_OWNER_CH0_S 5 -/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [6]; default: 0; +#define RMT_MEM_OWNER_CH2 (BIT(5)) +#define RMT_MEM_OWNER_CH2_M (RMT_MEM_OWNER_CH2_V << RMT_MEM_OWNER_CH2_S) +#define RMT_MEM_OWNER_CH2_V 0x00000001U +#define RMT_MEM_OWNER_CH2_S 5 +/** RMT_TX_CONTI_MODE_CH2 : R/W; bitpos: [6]; default: 0; * Set this bit to restart transmission in continuous node from the first data in * channel 2. */ -#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) -#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U -#define RMT_TX_CONTI_MODE_CH0_S 6 -/** RMT_RX_FILTER_EN_CH0 : R/W; bitpos: [7]; default: 0; +#define RMT_TX_CONTI_MODE_CH2 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH2_M (RMT_TX_CONTI_MODE_CH2_V << RMT_TX_CONTI_MODE_CH2_S) +#define RMT_TX_CONTI_MODE_CH2_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH2_S 6 +/** RMT_RX_FILTER_EN_CH2 : R/W; bitpos: [7]; default: 0; * Set this bit to enable the receiver's filter for channel 2. */ -#define RMT_RX_FILTER_EN_CH0 (BIT(7)) -#define RMT_RX_FILTER_EN_CH0_M (RMT_RX_FILTER_EN_CH0_V << RMT_RX_FILTER_EN_CH0_S) -#define RMT_RX_FILTER_EN_CH0_V 0x00000001U -#define RMT_RX_FILTER_EN_CH0_S 7 -/** RMT_RX_FILTER_THRES_CH0 : R/W; bitpos: [15:8]; default: 15; +#define RMT_RX_FILTER_EN_CH2 (BIT(7)) +#define RMT_RX_FILTER_EN_CH2_M (RMT_RX_FILTER_EN_CH2_V << RMT_RX_FILTER_EN_CH2_S) +#define RMT_RX_FILTER_EN_CH2_V 0x00000001U +#define RMT_RX_FILTER_EN_CH2_S 7 +/** RMT_RX_FILTER_THRES_CH2 : R/W; bitpos: [15:8]; default: 15; * Set this field to ignore the input pulse when its width is less than * RMT_RX_FILTER_THRES_CH2 APB clock cycles in receive mode. */ -#define RMT_RX_FILTER_THRES_CH0 0x000000FFU -#define RMT_RX_FILTER_THRES_CH0_M (RMT_RX_FILTER_THRES_CH0_V << RMT_RX_FILTER_THRES_CH0_S) -#define RMT_RX_FILTER_THRES_CH0_V 0x000000FFU -#define RMT_RX_FILTER_THRES_CH0_S 8 -/** RMT_CHK_RX_CARRIER_EN_CH0 : R/W; bitpos: [16]; default: 0; +#define RMT_RX_FILTER_THRES_CH2 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_M (RMT_RX_FILTER_THRES_CH2_V << RMT_RX_FILTER_THRES_CH2_S) +#define RMT_RX_FILTER_THRES_CH2_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH2_S 8 +/** RMT_CHK_RX_CARRIER_EN_CH2 : R/W; bitpos: [16]; default: 0; * Set this bit to enable memory loop read mode when carrier modulation is enabled for * channel 2. */ -#define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) -#define RMT_CHK_RX_CARRIER_EN_CH0_M (RMT_CHK_RX_CARRIER_EN_CH0_V << RMT_CHK_RX_CARRIER_EN_CH0_S) -#define RMT_CHK_RX_CARRIER_EN_CH0_V 0x00000001U -#define RMT_CHK_RX_CARRIER_EN_CH0_S 16 -/** RMT_REF_ALWAYS_ON_CH0 : R/W; bitpos: [17]; default: 0; +#define RMT_CHK_RX_CARRIER_EN_CH2 (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH2_M (RMT_CHK_RX_CARRIER_EN_CH2_V << RMT_CHK_RX_CARRIER_EN_CH2_S) +#define RMT_CHK_RX_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CHK_RX_CARRIER_EN_CH2_S 16 +/** RMT_REF_ALWAYS_ON_CH2 : R/W; bitpos: [17]; default: 0; * Set this bit to select a base clock for channel 2. * * 1'h1: APB_CLK 1'h0: REF_TICK */ -#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH0_M (RMT_REF_ALWAYS_ON_CH0_V << RMT_REF_ALWAYS_ON_CH0_S) -#define RMT_REF_ALWAYS_ON_CH0_V 0x00000001U -#define RMT_REF_ALWAYS_ON_CH0_S 17 -/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [18]; default: 0; +#define RMT_REF_ALWAYS_ON_CH2 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH2_M (RMT_REF_ALWAYS_ON_CH2_V << RMT_REF_ALWAYS_ON_CH2_S) +#define RMT_REF_ALWAYS_ON_CH2_V 0x00000001U +#define RMT_REF_ALWAYS_ON_CH2_S 17 +/** RMT_IDLE_OUT_LV_CH2 : R/W; bitpos: [18]; default: 0; * This bit configures the level of output signals in channel 2 when the transmitter * is in idle state. */ -#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) -#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U -#define RMT_IDLE_OUT_LV_CH0_S 18 -/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [19]; default: 0; +#define RMT_IDLE_OUT_LV_CH2 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH2_M (RMT_IDLE_OUT_LV_CH2_V << RMT_IDLE_OUT_LV_CH2_S) +#define RMT_IDLE_OUT_LV_CH2_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH2_S 18 +/** RMT_IDLE_OUT_EN_CH2 : R/W; bitpos: [19]; default: 0; * This is the output enable bit for channel 2 in idle state. */ -#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) -#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U -#define RMT_IDLE_OUT_EN_CH0_S 19 -/** RMT_TX_STOP_CH0 : R/W; bitpos: [20]; default: 0; +#define RMT_IDLE_OUT_EN_CH2 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH2_M (RMT_IDLE_OUT_EN_CH2_V << RMT_IDLE_OUT_EN_CH2_S) +#define RMT_IDLE_OUT_EN_CH2_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH2_S 19 +/** RMT_TX_STOP_CH2 : R/W; bitpos: [20]; default: 0; * Set this bit to stop the transmitter of channel 2 sending data out. */ -#define RMT_TX_STOP_CH0 (BIT(20)) -#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) -#define RMT_TX_STOP_CH0_V 0x00000001U -#define RMT_TX_STOP_CH0_S 20 +#define RMT_TX_STOP_CH2 (BIT(20)) +#define RMT_TX_STOP_CH2_M (RMT_TX_STOP_CH2_V << RMT_TX_STOP_CH2_S) +#define RMT_TX_STOP_CH2_V 0x00000001U +#define RMT_TX_STOP_CH2_S 20 /** RMT_CH3CONF0_REG register * Channel 3 configuration register 0 */ #define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x28) -/** RMT_DIV_CNT_CH0 : R/W; bitpos: [7:0]; default: 2; +/** RMT_DIV_CNT_CH3 : R/W; bitpos: [7:0]; default: 2; * This field is used to configure clock divider for channel 3. */ -#define RMT_DIV_CNT_CH0 0x000000FFU -#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) -#define RMT_DIV_CNT_CH0_V 0x000000FFU -#define RMT_DIV_CNT_CH0_S 0 -/** RMT_IDLE_THRES_CH0 : R/W; bitpos: [23:8]; default: 4096; +#define RMT_DIV_CNT_CH3 0x000000FFU +#define RMT_DIV_CNT_CH3_M (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S) +#define RMT_DIV_CNT_CH3_V 0x000000FFU +#define RMT_DIV_CNT_CH3_S 0 +/** RMT_IDLE_THRES_CH3 : R/W; bitpos: [23:8]; default: 4096; * Receiving ends when no edge is detected on input signals for continuous clock * cycles longer than this field value. */ -#define RMT_IDLE_THRES_CH0 0x0000FFFFU -#define RMT_IDLE_THRES_CH0_M (RMT_IDLE_THRES_CH0_V << RMT_IDLE_THRES_CH0_S) -#define RMT_IDLE_THRES_CH0_V 0x0000FFFFU -#define RMT_IDLE_THRES_CH0_S 8 -/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [26:24]; default: 1; +#define RMT_IDLE_THRES_CH3 0x0000FFFFU +#define RMT_IDLE_THRES_CH3_M (RMT_IDLE_THRES_CH3_V << RMT_IDLE_THRES_CH3_S) +#define RMT_IDLE_THRES_CH3_V 0x0000FFFFU +#define RMT_IDLE_THRES_CH3_S 8 +/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [26:24]; default: 1; * This field is used to configure the maximum blocks allocated to channel 3. The * valid range is from 1 ~ 4-3. */ -#define RMT_MEM_SIZE_CH0 0x00000007U -#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) -#define RMT_MEM_SIZE_CH0_V 0x00000007U -#define RMT_MEM_SIZE_CH0_S 24 -/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [27]; default: 1; +#define RMT_MEM_SIZE_CH3 0x00000007U +#define RMT_MEM_SIZE_CH3_M (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S) +#define RMT_MEM_SIZE_CH3_V 0x00000007U +#define RMT_MEM_SIZE_CH3_S 24 +/** RMT_CARRIER_EFF_EN_CH3 : R/W; bitpos: [27]; default: 1; * 1: Add carrier modulation on output signals only at data sending state for channel * 3. 0: Add carrier modulation on signals at all states for channel 3. States here * include idle state (ST_IDLE), reading data from RAM (ST_RD_MEM), and sending data * stored in RAM (ST_SEND). Only valid when RMT_CARRIER_EN_CH3 is set to 1. */ -#define RMT_CARRIER_EFF_EN_CH0 (BIT(27)) -#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) -#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U -#define RMT_CARRIER_EFF_EN_CH0_S 27 -/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [28]; default: 1; +#define RMT_CARRIER_EFF_EN_CH3 (BIT(27)) +#define RMT_CARRIER_EFF_EN_CH3_M (RMT_CARRIER_EFF_EN_CH3_V << RMT_CARRIER_EFF_EN_CH3_S) +#define RMT_CARRIER_EFF_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH3_S 27 +/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [28]; default: 1; * This bit is used to enable carrier modulation for channel 3. 1: Add carrier * modulation on output signals. 0: No carrier modulation is added on output signals. */ -#define RMT_CARRIER_EN_CH0 (BIT(28)) -#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) -#define RMT_CARRIER_EN_CH0_V 0x00000001U -#define RMT_CARRIER_EN_CH0_S 28 -/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [29]; default: 1; +#define RMT_CARRIER_EN_CH3 (BIT(28)) +#define RMT_CARRIER_EN_CH3_M (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S) +#define RMT_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EN_CH3_S 28 +/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [29]; default: 1; * This bit is used to configure the position of carrier wave for channel 3. * * 1'h0: Add carrier wave on low-level output signals. * * 1'h1: Add carrier wave on high-level output signals. */ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) -#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U -#define RMT_CARRIER_OUT_LV_CH0_S 29 +#define RMT_CARRIER_OUT_LV_CH3 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH3_M (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S) +#define RMT_CARRIER_OUT_LV_CH3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH3_S 29 /** RMT_CH3CONF1_REG register * Channel 3 configuration register 1 */ #define RMT_CH3CONF1_REG (DR_REG_RMT_BASE + 0x2c) -/** RMT_TX_START_CH0 : R/W; bitpos: [0]; default: 0; +/** RMT_TX_START_CH3 : R/W; bitpos: [0]; default: 0; * Set this bit to start sending data on channel 3. */ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) -#define RMT_TX_START_CH0_V 0x00000001U -#define RMT_TX_START_CH0_S 0 -/** RMT_RX_EN_CH0 : R/W; bitpos: [1]; default: 0; +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (RMT_TX_START_CH3_V << RMT_TX_START_CH3_S) +#define RMT_TX_START_CH3_V 0x00000001U +#define RMT_TX_START_CH3_S 0 +/** RMT_RX_EN_CH3 : R/W; bitpos: [1]; default: 0; * Set this bit to enable receiver to receive data on channel 3. */ -#define RMT_RX_EN_CH0 (BIT(1)) -#define RMT_RX_EN_CH0_M (RMT_RX_EN_CH0_V << RMT_RX_EN_CH0_S) -#define RMT_RX_EN_CH0_V 0x00000001U -#define RMT_RX_EN_CH0_S 1 -/** RMT_MEM_WR_RST_CH0 : WO; bitpos: [2]; default: 0; +#define RMT_RX_EN_CH3 (BIT(1)) +#define RMT_RX_EN_CH3_M (RMT_RX_EN_CH3_V << RMT_RX_EN_CH3_S) +#define RMT_RX_EN_CH3_V 0x00000001U +#define RMT_RX_EN_CH3_S 1 +/** RMT_MEM_WR_RST_CH3 : WO; bitpos: [2]; default: 0; * Set this bit to reset RAM write address accessed by the receiver for channel 3. */ -#define RMT_MEM_WR_RST_CH0 (BIT(2)) -#define RMT_MEM_WR_RST_CH0_M (RMT_MEM_WR_RST_CH0_V << RMT_MEM_WR_RST_CH0_S) -#define RMT_MEM_WR_RST_CH0_V 0x00000001U -#define RMT_MEM_WR_RST_CH0_S 2 -/** RMT_MEM_RD_RST_CH0 : WO; bitpos: [3]; default: 0; +#define RMT_MEM_WR_RST_CH3 (BIT(2)) +#define RMT_MEM_WR_RST_CH3_M (RMT_MEM_WR_RST_CH3_V << RMT_MEM_WR_RST_CH3_S) +#define RMT_MEM_WR_RST_CH3_V 0x00000001U +#define RMT_MEM_WR_RST_CH3_S 2 +/** RMT_MEM_RD_RST_CH3 : WO; bitpos: [3]; default: 0; * Set this bit to reset RAM read address accessed by the transmitter for channel 3. */ -#define RMT_MEM_RD_RST_CH0 (BIT(3)) -#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) -#define RMT_MEM_RD_RST_CH0_V 0x00000001U -#define RMT_MEM_RD_RST_CH0_S 3 -/** RMT_APB_MEM_RST_CH0 : WO; bitpos: [4]; default: 0; +#define RMT_MEM_RD_RST_CH3 (BIT(3)) +#define RMT_MEM_RD_RST_CH3_M (RMT_MEM_RD_RST_CH3_V << RMT_MEM_RD_RST_CH3_S) +#define RMT_MEM_RD_RST_CH3_V 0x00000001U +#define RMT_MEM_RD_RST_CH3_S 3 +/** RMT_APB_MEM_RST_CH3 : WO; bitpos: [4]; default: 0; * Set this bit to reset W/R ram address for channel 3 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_CH0 (BIT(4)) -#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) -#define RMT_APB_MEM_RST_CH0_V 0x00000001U -#define RMT_APB_MEM_RST_CH0_S 4 -/** RMT_MEM_OWNER_CH0 : R/W; bitpos: [5]; default: 1; +#define RMT_APB_MEM_RST_CH3 (BIT(4)) +#define RMT_APB_MEM_RST_CH3_M (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S) +#define RMT_APB_MEM_RST_CH3_V 0x00000001U +#define RMT_APB_MEM_RST_CH3_S 4 +/** RMT_MEM_OWNER_CH3 : R/W; bitpos: [5]; default: 1; * This bit marks the ownership of channel 3's RAM block. * * 1'h1: Receiver is using the RAM. * * 1'h0: Transmitter is using the RAM. */ -#define RMT_MEM_OWNER_CH0 (BIT(5)) -#define RMT_MEM_OWNER_CH0_M (RMT_MEM_OWNER_CH0_V << RMT_MEM_OWNER_CH0_S) -#define RMT_MEM_OWNER_CH0_V 0x00000001U -#define RMT_MEM_OWNER_CH0_S 5 -/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [6]; default: 0; +#define RMT_MEM_OWNER_CH3 (BIT(5)) +#define RMT_MEM_OWNER_CH3_M (RMT_MEM_OWNER_CH3_V << RMT_MEM_OWNER_CH3_S) +#define RMT_MEM_OWNER_CH3_V 0x00000001U +#define RMT_MEM_OWNER_CH3_S 5 +/** RMT_TX_CONTI_MODE_CH3 : R/W; bitpos: [6]; default: 0; * Set this bit to restart transmission in continuous node from the first data in * channel 3. */ -#define RMT_TX_CONTI_MODE_CH0 (BIT(6)) -#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) -#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U -#define RMT_TX_CONTI_MODE_CH0_S 6 -/** RMT_RX_FILTER_EN_CH0 : R/W; bitpos: [7]; default: 0; +#define RMT_TX_CONTI_MODE_CH3 (BIT(6)) +#define RMT_TX_CONTI_MODE_CH3_M (RMT_TX_CONTI_MODE_CH3_V << RMT_TX_CONTI_MODE_CH3_S) +#define RMT_TX_CONTI_MODE_CH3_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH3_S 6 +/** RMT_RX_FILTER_EN_CH3 : R/W; bitpos: [7]; default: 0; * Set this bit to enable the receiver's filter for channel 3. */ -#define RMT_RX_FILTER_EN_CH0 (BIT(7)) -#define RMT_RX_FILTER_EN_CH0_M (RMT_RX_FILTER_EN_CH0_V << RMT_RX_FILTER_EN_CH0_S) -#define RMT_RX_FILTER_EN_CH0_V 0x00000001U -#define RMT_RX_FILTER_EN_CH0_S 7 -/** RMT_RX_FILTER_THRES_CH0 : R/W; bitpos: [15:8]; default: 15; +#define RMT_RX_FILTER_EN_CH3 (BIT(7)) +#define RMT_RX_FILTER_EN_CH3_M (RMT_RX_FILTER_EN_CH3_V << RMT_RX_FILTER_EN_CH3_S) +#define RMT_RX_FILTER_EN_CH3_V 0x00000001U +#define RMT_RX_FILTER_EN_CH3_S 7 +/** RMT_RX_FILTER_THRES_CH3 : R/W; bitpos: [15:8]; default: 15; * Set this field to ignore the input pulse when its width is less than * RMT_RX_FILTER_THRES_CH3 APB clock cycles in receive mode. */ -#define RMT_RX_FILTER_THRES_CH0 0x000000FFU -#define RMT_RX_FILTER_THRES_CH0_M (RMT_RX_FILTER_THRES_CH0_V << RMT_RX_FILTER_THRES_CH0_S) -#define RMT_RX_FILTER_THRES_CH0_V 0x000000FFU -#define RMT_RX_FILTER_THRES_CH0_S 8 -/** RMT_CHK_RX_CARRIER_EN_CH0 : R/W; bitpos: [16]; default: 0; +#define RMT_RX_FILTER_THRES_CH3 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_M (RMT_RX_FILTER_THRES_CH3_V << RMT_RX_FILTER_THRES_CH3_S) +#define RMT_RX_FILTER_THRES_CH3_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH3_S 8 +/** RMT_CHK_RX_CARRIER_EN_CH3 : R/W; bitpos: [16]; default: 0; * Set this bit to enable memory loop read mode when carrier modulation is enabled for * channel 3. */ -#define RMT_CHK_RX_CARRIER_EN_CH0 (BIT(16)) -#define RMT_CHK_RX_CARRIER_EN_CH0_M (RMT_CHK_RX_CARRIER_EN_CH0_V << RMT_CHK_RX_CARRIER_EN_CH0_S) -#define RMT_CHK_RX_CARRIER_EN_CH0_V 0x00000001U -#define RMT_CHK_RX_CARRIER_EN_CH0_S 16 -/** RMT_REF_ALWAYS_ON_CH0 : R/W; bitpos: [17]; default: 0; +#define RMT_CHK_RX_CARRIER_EN_CH3 (BIT(16)) +#define RMT_CHK_RX_CARRIER_EN_CH3_M (RMT_CHK_RX_CARRIER_EN_CH3_V << RMT_CHK_RX_CARRIER_EN_CH3_S) +#define RMT_CHK_RX_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CHK_RX_CARRIER_EN_CH3_S 16 +/** RMT_REF_ALWAYS_ON_CH3 : R/W; bitpos: [17]; default: 0; * Set this bit to select a base clock for channel 3. * * 1'h1: APB_CLK 1'h0: REF_TICK */ -#define RMT_REF_ALWAYS_ON_CH0 (BIT(17)) -#define RMT_REF_ALWAYS_ON_CH0_M (RMT_REF_ALWAYS_ON_CH0_V << RMT_REF_ALWAYS_ON_CH0_S) -#define RMT_REF_ALWAYS_ON_CH0_V 0x00000001U -#define RMT_REF_ALWAYS_ON_CH0_S 17 -/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [18]; default: 0; +#define RMT_REF_ALWAYS_ON_CH3 (BIT(17)) +#define RMT_REF_ALWAYS_ON_CH3_M (RMT_REF_ALWAYS_ON_CH3_V << RMT_REF_ALWAYS_ON_CH3_S) +#define RMT_REF_ALWAYS_ON_CH3_V 0x00000001U +#define RMT_REF_ALWAYS_ON_CH3_S 17 +/** RMT_IDLE_OUT_LV_CH3 : R/W; bitpos: [18]; default: 0; * This bit configures the level of output signals in channel 3 when the transmitter * is in idle state. */ -#define RMT_IDLE_OUT_LV_CH0 (BIT(18)) -#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) -#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U -#define RMT_IDLE_OUT_LV_CH0_S 18 -/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [19]; default: 0; +#define RMT_IDLE_OUT_LV_CH3 (BIT(18)) +#define RMT_IDLE_OUT_LV_CH3_M (RMT_IDLE_OUT_LV_CH3_V << RMT_IDLE_OUT_LV_CH3_S) +#define RMT_IDLE_OUT_LV_CH3_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH3_S 18 +/** RMT_IDLE_OUT_EN_CH3 : R/W; bitpos: [19]; default: 0; * This is the output enable bit for channel 3 in idle state. */ -#define RMT_IDLE_OUT_EN_CH0 (BIT(19)) -#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) -#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U -#define RMT_IDLE_OUT_EN_CH0_S 19 -/** RMT_TX_STOP_CH0 : R/W; bitpos: [20]; default: 0; +#define RMT_IDLE_OUT_EN_CH3 (BIT(19)) +#define RMT_IDLE_OUT_EN_CH3_M (RMT_IDLE_OUT_EN_CH3_V << RMT_IDLE_OUT_EN_CH3_S) +#define RMT_IDLE_OUT_EN_CH3_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH3_S 19 +/** RMT_TX_STOP_CH3 : R/W; bitpos: [20]; default: 0; * Set this bit to stop the transmitter of channel 3 sending data out. */ -#define RMT_TX_STOP_CH0 (BIT(20)) -#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) -#define RMT_TX_STOP_CH0_V 0x00000001U -#define RMT_TX_STOP_CH0_S 20 +#define RMT_TX_STOP_CH3 (BIT(20)) +#define RMT_TX_STOP_CH3_M (RMT_TX_STOP_CH3_V << RMT_TX_STOP_CH3_S) +#define RMT_TX_STOP_CH3_V 0x00000001U +#define RMT_TX_STOP_CH3_S 20 /** RMT_CH0STATUS_REG register * Channel 0 status register @@ -811,202 +811,202 @@ extern "C" { * Channel 1 status register */ #define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x34) -/** RMT_MEM_WADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; +/** RMT_MEM_WADDR_EX_CH1 : RO; bitpos: [8:0]; default: 0; * This field records the memory address offset when receiver of channel 1 is using * the RAM. */ -#define RMT_MEM_WADDR_EX_CH0 0x000001FFU -#define RMT_MEM_WADDR_EX_CH0_M (RMT_MEM_WADDR_EX_CH0_V << RMT_MEM_WADDR_EX_CH0_S) -#define RMT_MEM_WADDR_EX_CH0_V 0x000001FFU -#define RMT_MEM_WADDR_EX_CH0_S 0 -/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [18:10]; default: 0; +#define RMT_MEM_WADDR_EX_CH1 0x000001FFU +#define RMT_MEM_WADDR_EX_CH1_M (RMT_MEM_WADDR_EX_CH1_V << RMT_MEM_WADDR_EX_CH1_S) +#define RMT_MEM_WADDR_EX_CH1_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH1_S 0 +/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [18:10]; default: 0; * This field records the memory address offset when transmitter of channel 1 is using * the RAM. */ -#define RMT_MEM_RADDR_EX_CH0 0x000001FFU -#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) -#define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU -#define RMT_MEM_RADDR_EX_CH0_S 10 -/** RMT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; +#define RMT_MEM_RADDR_EX_CH1 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_M (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S) +#define RMT_MEM_RADDR_EX_CH1_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH1_S 10 +/** RMT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; * This field records the FSM status of channel 1. */ -#define RMT_STATE_CH0 0x00000007U -#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) -#define RMT_STATE_CH0_V 0x00000007U -#define RMT_STATE_CH0_S 20 -/** RMT_MEM_OWNER_ERR_CH0 : RO; bitpos: [23]; default: 0; +#define RMT_STATE_CH1 0x00000007U +#define RMT_STATE_CH1_M (RMT_STATE_CH1_V << RMT_STATE_CH1_S) +#define RMT_STATE_CH1_V 0x00000007U +#define RMT_STATE_CH1_S 20 +/** RMT_MEM_OWNER_ERR_CH1 : RO; bitpos: [23]; default: 0; * This status bit will be set when the ownership of memory block is violated. */ -#define RMT_MEM_OWNER_ERR_CH0 (BIT(23)) -#define RMT_MEM_OWNER_ERR_CH0_M (RMT_MEM_OWNER_ERR_CH0_V << RMT_MEM_OWNER_ERR_CH0_S) -#define RMT_MEM_OWNER_ERR_CH0_V 0x00000001U -#define RMT_MEM_OWNER_ERR_CH0_S 23 -/** RMT_MEM_FULL_CH0 : RO; bitpos: [24]; default: 0; +#define RMT_MEM_OWNER_ERR_CH1 (BIT(23)) +#define RMT_MEM_OWNER_ERR_CH1_M (RMT_MEM_OWNER_ERR_CH1_V << RMT_MEM_OWNER_ERR_CH1_S) +#define RMT_MEM_OWNER_ERR_CH1_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH1_S 23 +/** RMT_MEM_FULL_CH1 : RO; bitpos: [24]; default: 0; * This status bit will be set if the receiver receives more data than the memory * allows. */ -#define RMT_MEM_FULL_CH0 (BIT(24)) -#define RMT_MEM_FULL_CH0_M (RMT_MEM_FULL_CH0_V << RMT_MEM_FULL_CH0_S) -#define RMT_MEM_FULL_CH0_V 0x00000001U -#define RMT_MEM_FULL_CH0_S 24 -/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; +#define RMT_MEM_FULL_CH1 (BIT(24)) +#define RMT_MEM_FULL_CH1_M (RMT_MEM_FULL_CH1_V << RMT_MEM_FULL_CH1_S) +#define RMT_MEM_FULL_CH1_V 0x00000001U +#define RMT_MEM_FULL_CH1_S 24 +/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [25]; default: 0; * This status bit will be set when the data to be sent is more than memory allows and * the wrap mode is disabled. */ -#define RMT_MEM_EMPTY_CH0 (BIT(25)) -#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) -#define RMT_MEM_EMPTY_CH0_V 0x00000001U -#define RMT_MEM_EMPTY_CH0_S 25 -/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_EMPTY_CH1 (BIT(25)) +#define RMT_MEM_EMPTY_CH1_M (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S) +#define RMT_MEM_EMPTY_CH1_V 0x00000001U +#define RMT_MEM_EMPTY_CH1_S 25 +/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [26]; default: 0; * This status bit will be set if the offset address out of memory size when writes * RAM via APB bus. */ -#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) -#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U -#define RMT_APB_MEM_WR_ERR_CH0_S 26 -/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [27]; default: 0; +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH1_M (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH1_S 26 +/** RMT_APB_MEM_RD_ERR_CH1 : RO; bitpos: [27]; default: 0; * This status bit will be set if the offset address out of memory size when reads RAM * via APB bus. */ -#define RMT_APB_MEM_RD_ERR_CH0 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) -#define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U -#define RMT_APB_MEM_RD_ERR_CH0_S 27 +#define RMT_APB_MEM_RD_ERR_CH1 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH1_M (RMT_APB_MEM_RD_ERR_CH1_V << RMT_APB_MEM_RD_ERR_CH1_S) +#define RMT_APB_MEM_RD_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH1_S 27 /** RMT_CH2STATUS_REG register * Channel 2 status register */ #define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x38) -/** RMT_MEM_WADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; +/** RMT_MEM_WADDR_EX_CH2 : RO; bitpos: [8:0]; default: 0; * This field records the memory address offset when receiver of channel 2 is using * the RAM. */ -#define RMT_MEM_WADDR_EX_CH0 0x000001FFU -#define RMT_MEM_WADDR_EX_CH0_M (RMT_MEM_WADDR_EX_CH0_V << RMT_MEM_WADDR_EX_CH0_S) -#define RMT_MEM_WADDR_EX_CH0_V 0x000001FFU -#define RMT_MEM_WADDR_EX_CH0_S 0 -/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [18:10]; default: 0; +#define RMT_MEM_WADDR_EX_CH2 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_M (RMT_MEM_WADDR_EX_CH2_V << RMT_MEM_WADDR_EX_CH2_S) +#define RMT_MEM_WADDR_EX_CH2_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH2_S 0 +/** RMT_MEM_RADDR_EX_CH2 : RO; bitpos: [18:10]; default: 0; * This field records the memory address offset when transmitter of channel 2 is using * the RAM. */ -#define RMT_MEM_RADDR_EX_CH0 0x000001FFU -#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) -#define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU -#define RMT_MEM_RADDR_EX_CH0_S 10 -/** RMT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; +#define RMT_MEM_RADDR_EX_CH2 0x000001FFU +#define RMT_MEM_RADDR_EX_CH2_M (RMT_MEM_RADDR_EX_CH2_V << RMT_MEM_RADDR_EX_CH2_S) +#define RMT_MEM_RADDR_EX_CH2_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH2_S 10 +/** RMT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; * This field records the FSM status of channel 2. */ -#define RMT_STATE_CH0 0x00000007U -#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) -#define RMT_STATE_CH0_V 0x00000007U -#define RMT_STATE_CH0_S 20 -/** RMT_MEM_OWNER_ERR_CH0 : RO; bitpos: [23]; default: 0; +#define RMT_STATE_CH2 0x00000007U +#define RMT_STATE_CH2_M (RMT_STATE_CH2_V << RMT_STATE_CH2_S) +#define RMT_STATE_CH2_V 0x00000007U +#define RMT_STATE_CH2_S 20 +/** RMT_MEM_OWNER_ERR_CH2 : RO; bitpos: [23]; default: 0; * This status bit will be set when the ownership of memory block is violated. */ -#define RMT_MEM_OWNER_ERR_CH0 (BIT(23)) -#define RMT_MEM_OWNER_ERR_CH0_M (RMT_MEM_OWNER_ERR_CH0_V << RMT_MEM_OWNER_ERR_CH0_S) -#define RMT_MEM_OWNER_ERR_CH0_V 0x00000001U -#define RMT_MEM_OWNER_ERR_CH0_S 23 -/** RMT_MEM_FULL_CH0 : RO; bitpos: [24]; default: 0; +#define RMT_MEM_OWNER_ERR_CH2 (BIT(23)) +#define RMT_MEM_OWNER_ERR_CH2_M (RMT_MEM_OWNER_ERR_CH2_V << RMT_MEM_OWNER_ERR_CH2_S) +#define RMT_MEM_OWNER_ERR_CH2_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH2_S 23 +/** RMT_MEM_FULL_CH2 : RO; bitpos: [24]; default: 0; * This status bit will be set if the receiver receives more data than the memory * allows. */ -#define RMT_MEM_FULL_CH0 (BIT(24)) -#define RMT_MEM_FULL_CH0_M (RMT_MEM_FULL_CH0_V << RMT_MEM_FULL_CH0_S) -#define RMT_MEM_FULL_CH0_V 0x00000001U -#define RMT_MEM_FULL_CH0_S 24 -/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; +#define RMT_MEM_FULL_CH2 (BIT(24)) +#define RMT_MEM_FULL_CH2_M (RMT_MEM_FULL_CH2_V << RMT_MEM_FULL_CH2_S) +#define RMT_MEM_FULL_CH2_V 0x00000001U +#define RMT_MEM_FULL_CH2_S 24 +/** RMT_MEM_EMPTY_CH2 : RO; bitpos: [25]; default: 0; * This status bit will be set when the data to be sent is more than memory allows and * the wrap mode is disabled. */ -#define RMT_MEM_EMPTY_CH0 (BIT(25)) -#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) -#define RMT_MEM_EMPTY_CH0_V 0x00000001U -#define RMT_MEM_EMPTY_CH0_S 25 -/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_EMPTY_CH2 (BIT(25)) +#define RMT_MEM_EMPTY_CH2_M (RMT_MEM_EMPTY_CH2_V << RMT_MEM_EMPTY_CH2_S) +#define RMT_MEM_EMPTY_CH2_V 0x00000001U +#define RMT_MEM_EMPTY_CH2_S 25 +/** RMT_APB_MEM_WR_ERR_CH2 : RO; bitpos: [26]; default: 0; * This status bit will be set if the offset address out of memory size when writes * RAM via APB bus. */ -#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) -#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U -#define RMT_APB_MEM_WR_ERR_CH0_S 26 -/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [27]; default: 0; +#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH2_M (RMT_APB_MEM_WR_ERR_CH2_V << RMT_APB_MEM_WR_ERR_CH2_S) +#define RMT_APB_MEM_WR_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH2_S 26 +/** RMT_APB_MEM_RD_ERR_CH2 : RO; bitpos: [27]; default: 0; * This status bit will be set if the offset address out of memory size when reads RAM * via APB bus. */ -#define RMT_APB_MEM_RD_ERR_CH0 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) -#define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U -#define RMT_APB_MEM_RD_ERR_CH0_S 27 +#define RMT_APB_MEM_RD_ERR_CH2 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH2_M (RMT_APB_MEM_RD_ERR_CH2_V << RMT_APB_MEM_RD_ERR_CH2_S) +#define RMT_APB_MEM_RD_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH2_S 27 /** RMT_CH3STATUS_REG register * Channel 3 status register */ #define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x3c) -/** RMT_MEM_WADDR_EX_CH0 : RO; bitpos: [8:0]; default: 0; +/** RMT_MEM_WADDR_EX_CH3 : RO; bitpos: [8:0]; default: 0; * This field records the memory address offset when receiver of channel 3 is using * the RAM. */ -#define RMT_MEM_WADDR_EX_CH0 0x000001FFU -#define RMT_MEM_WADDR_EX_CH0_M (RMT_MEM_WADDR_EX_CH0_V << RMT_MEM_WADDR_EX_CH0_S) -#define RMT_MEM_WADDR_EX_CH0_V 0x000001FFU -#define RMT_MEM_WADDR_EX_CH0_S 0 -/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [18:10]; default: 0; +#define RMT_MEM_WADDR_EX_CH3 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_M (RMT_MEM_WADDR_EX_CH3_V << RMT_MEM_WADDR_EX_CH3_S) +#define RMT_MEM_WADDR_EX_CH3_V 0x000001FFU +#define RMT_MEM_WADDR_EX_CH3_S 0 +/** RMT_MEM_RADDR_EX_CH3 : RO; bitpos: [18:10]; default: 0; * This field records the memory address offset when transmitter of channel 3 is using * the RAM. */ -#define RMT_MEM_RADDR_EX_CH0 0x000001FFU -#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) -#define RMT_MEM_RADDR_EX_CH0_V 0x000001FFU -#define RMT_MEM_RADDR_EX_CH0_S 10 -/** RMT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; +#define RMT_MEM_RADDR_EX_CH3 0x000001FFU +#define RMT_MEM_RADDR_EX_CH3_M (RMT_MEM_RADDR_EX_CH3_V << RMT_MEM_RADDR_EX_CH3_S) +#define RMT_MEM_RADDR_EX_CH3_V 0x000001FFU +#define RMT_MEM_RADDR_EX_CH3_S 10 +/** RMT_STATE_CH3 : RO; bitpos: [22:20]; default: 0; * This field records the FSM status of channel 3. */ -#define RMT_STATE_CH0 0x00000007U -#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) -#define RMT_STATE_CH0_V 0x00000007U -#define RMT_STATE_CH0_S 20 -/** RMT_MEM_OWNER_ERR_CH0 : RO; bitpos: [23]; default: 0; +#define RMT_STATE_CH3 0x00000007U +#define RMT_STATE_CH3_M (RMT_STATE_CH3_V << RMT_STATE_CH3_S) +#define RMT_STATE_CH3_V 0x00000007U +#define RMT_STATE_CH3_S 20 +/** RMT_MEM_OWNER_ERR_CH3 : RO; bitpos: [23]; default: 0; * This status bit will be set when the ownership of memory block is violated. */ -#define RMT_MEM_OWNER_ERR_CH0 (BIT(23)) -#define RMT_MEM_OWNER_ERR_CH0_M (RMT_MEM_OWNER_ERR_CH0_V << RMT_MEM_OWNER_ERR_CH0_S) -#define RMT_MEM_OWNER_ERR_CH0_V 0x00000001U -#define RMT_MEM_OWNER_ERR_CH0_S 23 -/** RMT_MEM_FULL_CH0 : RO; bitpos: [24]; default: 0; +#define RMT_MEM_OWNER_ERR_CH3 (BIT(23)) +#define RMT_MEM_OWNER_ERR_CH3_M (RMT_MEM_OWNER_ERR_CH3_V << RMT_MEM_OWNER_ERR_CH3_S) +#define RMT_MEM_OWNER_ERR_CH3_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH3_S 23 +/** RMT_MEM_FULL_CH3 : RO; bitpos: [24]; default: 0; * This status bit will be set if the receiver receives more data than the memory * allows. */ -#define RMT_MEM_FULL_CH0 (BIT(24)) -#define RMT_MEM_FULL_CH0_M (RMT_MEM_FULL_CH0_V << RMT_MEM_FULL_CH0_S) -#define RMT_MEM_FULL_CH0_V 0x00000001U -#define RMT_MEM_FULL_CH0_S 24 -/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; +#define RMT_MEM_FULL_CH3 (BIT(24)) +#define RMT_MEM_FULL_CH3_M (RMT_MEM_FULL_CH3_V << RMT_MEM_FULL_CH3_S) +#define RMT_MEM_FULL_CH3_V 0x00000001U +#define RMT_MEM_FULL_CH3_S 24 +/** RMT_MEM_EMPTY_CH3 : RO; bitpos: [25]; default: 0; * This status bit will be set when the data to be sent is more than memory allows and * the wrap mode is disabled. */ -#define RMT_MEM_EMPTY_CH0 (BIT(25)) -#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) -#define RMT_MEM_EMPTY_CH0_V 0x00000001U -#define RMT_MEM_EMPTY_CH0_S 25 -/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_EMPTY_CH3 (BIT(25)) +#define RMT_MEM_EMPTY_CH3_M (RMT_MEM_EMPTY_CH3_V << RMT_MEM_EMPTY_CH3_S) +#define RMT_MEM_EMPTY_CH3_V 0x00000001U +#define RMT_MEM_EMPTY_CH3_S 25 +/** RMT_APB_MEM_WR_ERR_CH3 : RO; bitpos: [26]; default: 0; * This status bit will be set if the offset address out of memory size when writes * RAM via APB bus. */ -#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) -#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U -#define RMT_APB_MEM_WR_ERR_CH0_S 26 -/** RMT_APB_MEM_RD_ERR_CH0 : RO; bitpos: [27]; default: 0; +#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH3_M (RMT_APB_MEM_WR_ERR_CH3_V << RMT_APB_MEM_WR_ERR_CH3_S) +#define RMT_APB_MEM_WR_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH3_S 26 +/** RMT_APB_MEM_RD_ERR_CH3 : RO; bitpos: [27]; default: 0; * This status bit will be set if the offset address out of memory size when reads RAM * via APB bus. */ -#define RMT_APB_MEM_RD_ERR_CH0 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH0_M (RMT_APB_MEM_RD_ERR_CH0_V << RMT_APB_MEM_RD_ERR_CH0_S) -#define RMT_APB_MEM_RD_ERR_CH0_V 0x00000001U -#define RMT_APB_MEM_RD_ERR_CH0_S 27 +#define RMT_APB_MEM_RD_ERR_CH3 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH3_M (RMT_APB_MEM_RD_ERR_CH3_V << RMT_APB_MEM_RD_ERR_CH3_S) +#define RMT_APB_MEM_RD_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH3_S 27 /** RMT_CH0ADDR_REG register * Channel 0 address register @@ -1031,58 +1031,58 @@ extern "C" { * Channel 1 address register */ #define RMT_CH1ADDR_REG (DR_REG_RMT_BASE + 0x44) -/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [8:0]; default: 0; +/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [8:0]; default: 0; * This field records the memory address offset when channel 1 writes RAM via APB bus. */ -#define RMT_APB_MEM_WADDR_CH0 0x000001FFU -#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) -#define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU -#define RMT_APB_MEM_WADDR_CH0_S 0 -/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [18:10]; default: 0; +#define RMT_APB_MEM_WADDR_CH1 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_M (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S) +#define RMT_APB_MEM_WADDR_CH1_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH1_S 0 +/** RMT_APB_MEM_RADDR_CH1 : RO; bitpos: [18:10]; default: 0; * This field records the memory address offset when channel 1 reads RAM via APB bus. */ -#define RMT_APB_MEM_RADDR_CH0 0x000001FFU -#define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) -#define RMT_APB_MEM_RADDR_CH0_V 0x000001FFU -#define RMT_APB_MEM_RADDR_CH0_S 10 +#define RMT_APB_MEM_RADDR_CH1 0x000001FFU +#define RMT_APB_MEM_RADDR_CH1_M (RMT_APB_MEM_RADDR_CH1_V << RMT_APB_MEM_RADDR_CH1_S) +#define RMT_APB_MEM_RADDR_CH1_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH1_S 10 /** RMT_CH2ADDR_REG register * Channel 2 address register */ #define RMT_CH2ADDR_REG (DR_REG_RMT_BASE + 0x48) -/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [8:0]; default: 0; +/** RMT_APB_MEM_WADDR_CH2 : RO; bitpos: [8:0]; default: 0; * This field records the memory address offset when channel 2 writes RAM via APB bus. */ -#define RMT_APB_MEM_WADDR_CH0 0x000001FFU -#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) -#define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU -#define RMT_APB_MEM_WADDR_CH0_S 0 -/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [18:10]; default: 0; +#define RMT_APB_MEM_WADDR_CH2 0x000001FFU +#define RMT_APB_MEM_WADDR_CH2_M (RMT_APB_MEM_WADDR_CH2_V << RMT_APB_MEM_WADDR_CH2_S) +#define RMT_APB_MEM_WADDR_CH2_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH2_S 0 +/** RMT_APB_MEM_RADDR_CH2 : RO; bitpos: [18:10]; default: 0; * This field records the memory address offset when channel 2 reads RAM via APB bus. */ -#define RMT_APB_MEM_RADDR_CH0 0x000001FFU -#define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) -#define RMT_APB_MEM_RADDR_CH0_V 0x000001FFU -#define RMT_APB_MEM_RADDR_CH0_S 10 +#define RMT_APB_MEM_RADDR_CH2 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_M (RMT_APB_MEM_RADDR_CH2_V << RMT_APB_MEM_RADDR_CH2_S) +#define RMT_APB_MEM_RADDR_CH2_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH2_S 10 /** RMT_CH3ADDR_REG register * Channel 3 address register */ #define RMT_CH3ADDR_REG (DR_REG_RMT_BASE + 0x4c) -/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [8:0]; default: 0; +/** RMT_APB_MEM_WADDR_CH3 : RO; bitpos: [8:0]; default: 0; * This field records the memory address offset when channel 3 writes RAM via APB bus. */ -#define RMT_APB_MEM_WADDR_CH0 0x000001FFU -#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) -#define RMT_APB_MEM_WADDR_CH0_V 0x000001FFU -#define RMT_APB_MEM_WADDR_CH0_S 0 -/** RMT_APB_MEM_RADDR_CH0 : RO; bitpos: [18:10]; default: 0; +#define RMT_APB_MEM_WADDR_CH3 0x000001FFU +#define RMT_APB_MEM_WADDR_CH3_M (RMT_APB_MEM_WADDR_CH3_V << RMT_APB_MEM_WADDR_CH3_S) +#define RMT_APB_MEM_WADDR_CH3_V 0x000001FFU +#define RMT_APB_MEM_WADDR_CH3_S 0 +/** RMT_APB_MEM_RADDR_CH3 : RO; bitpos: [18:10]; default: 0; * This field records the memory address offset when channel 3 reads RAM via APB bus. */ -#define RMT_APB_MEM_RADDR_CH0 0x000001FFU -#define RMT_APB_MEM_RADDR_CH0_M (RMT_APB_MEM_RADDR_CH0_V << RMT_APB_MEM_RADDR_CH0_S) -#define RMT_APB_MEM_RADDR_CH0_V 0x000001FFU -#define RMT_APB_MEM_RADDR_CH0_S 10 +#define RMT_APB_MEM_RADDR_CH3 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_M (RMT_APB_MEM_RADDR_CH3_V << RMT_APB_MEM_RADDR_CH3_S) +#define RMT_APB_MEM_RADDR_CH3_V 0x000001FFU +#define RMT_APB_MEM_RADDR_CH3_S 10 /** RMT_INT_RAW_REG register * Raw interrupt status register @@ -1697,64 +1697,64 @@ extern "C" { * Channel 1 duty cycle configuration register */ #define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x64) -/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; * This field is used to configure the clock cycles of carrier wave at low level for * channel 1. */ -#define RMT_CARRIER_LOW_CH0 0x0000FFFFU -#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) -#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU -#define RMT_CARRIER_LOW_CH0_S 0 -/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; +#define RMT_CARRIER_LOW_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; * This field is used to configure the clock cycles of carrier wave at high level for * channel 1. */ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU -#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) -#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU -#define RMT_CARRIER_HIGH_CH0_S 16 +#define RMT_CARRIER_HIGH_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_S 16 /** RMT_CH2CARRIER_DUTY_REG register * Channel 2 duty cycle configuration register */ #define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x68) -/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; +/** RMT_CARRIER_LOW_CH2 : R/W; bitpos: [15:0]; default: 64; * This field is used to configure the clock cycles of carrier wave at low level for * channel 2. */ -#define RMT_CARRIER_LOW_CH0 0x0000FFFFU -#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) -#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU -#define RMT_CARRIER_LOW_CH0_S 0 -/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; +#define RMT_CARRIER_LOW_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_CH2_M (RMT_CARRIER_LOW_CH2_V << RMT_CARRIER_LOW_CH2_S) +#define RMT_CARRIER_LOW_CH2_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH2_S 0 +/** RMT_CARRIER_HIGH_CH2 : R/W; bitpos: [31:16]; default: 64; * This field is used to configure the clock cycles of carrier wave at high level for * channel 2. */ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU -#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) -#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU -#define RMT_CARRIER_HIGH_CH0_S 16 +#define RMT_CARRIER_HIGH_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH2_M (RMT_CARRIER_HIGH_CH2_V << RMT_CARRIER_HIGH_CH2_S) +#define RMT_CARRIER_HIGH_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH2_S 16 /** RMT_CH3CARRIER_DUTY_REG register * Channel 3 duty cycle configuration register */ #define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x6c) -/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; +/** RMT_CARRIER_LOW_CH3 : R/W; bitpos: [15:0]; default: 64; * This field is used to configure the clock cycles of carrier wave at low level for * channel 3. */ -#define RMT_CARRIER_LOW_CH0 0x0000FFFFU -#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) -#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU -#define RMT_CARRIER_LOW_CH0_S 0 -/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; +#define RMT_CARRIER_LOW_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_CH3_M (RMT_CARRIER_LOW_CH3_V << RMT_CARRIER_LOW_CH3_S) +#define RMT_CARRIER_LOW_CH3_V 0x0000FFFFU +#define RMT_CARRIER_LOW_CH3_S 0 +/** RMT_CARRIER_HIGH_CH3 : R/W; bitpos: [31:16]; default: 64; * This field is used to configure the clock cycles of carrier wave at high level for * channel 3. */ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU -#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) -#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU -#define RMT_CARRIER_HIGH_CH0_S 16 +#define RMT_CARRIER_HIGH_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH3_M (RMT_CARRIER_HIGH_CH3_V << RMT_CARRIER_HIGH_CH3_S) +#define RMT_CARRIER_HIGH_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH3_S 16 /** RMT_CH0_TX_LIM_REG register * Channel 0 Tx event configuration register @@ -1797,112 +1797,112 @@ extern "C" { * Channel 1 Tx event configuration register */ #define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x74) -/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; * This field is used to configure the maximum entries that channel 1 can send out. * When RMT_MEM_SIZE_CH1 = 1, this field can be set to any value among 0 ~ 128 * (64*32/16 = 128). When RMT_MEM_SIZE_CH1 > 1, this field can be set to any value * among (0 ~ 128)*RMT_MEM_SIZE_CH1. */ -#define RMT_TX_LIM_CH0 0x000001FFU -#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) -#define RMT_TX_LIM_CH0_V 0x000001FFU -#define RMT_TX_LIM_CH0_S 0 -/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; +#define RMT_TX_LIM_CH1 0x000001FFU +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FFU +#define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; * This field is used to configure the maximum loop times when continuous transmission * mode is enabled. */ -#define RMT_TX_LOOP_NUM_CH0 0x000003FFU -#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) -#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU -#define RMT_TX_LOOP_NUM_CH0_S 9 -/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; +#define RMT_TX_LOOP_NUM_CH1 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; * This bit is used to enable loop counting. */ -#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) -#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U -#define RMT_TX_LOOP_CNT_EN_CH0_S 19 -/** RMT_LOOP_COUNT_RESET_CH0 : WO; bitpos: [20]; default: 0; +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WO; bitpos: [20]; default: 0; * This bit is used to reset loop counting when continuous transmission mode is valid. */ -#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) -#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U -#define RMT_LOOP_COUNT_RESET_CH0_S 20 +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH1_S 20 /** RMT_CH2_TX_LIM_REG register * Channel 2 Tx event configuration register */ #define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x78) -/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; +/** RMT_TX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; * This field is used to configure the maximum entries that channel 2 can send out. * When RMT_MEM_SIZE_CH2 = 1, this field can be set to any value among 0 ~ 128 * (64*32/16 = 128). When RMT_MEM_SIZE_CH2 > 1, this field can be set to any value * among (0 ~ 128)*RMT_MEM_SIZE_CH2. */ -#define RMT_TX_LIM_CH0 0x000001FFU -#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) -#define RMT_TX_LIM_CH0_V 0x000001FFU -#define RMT_TX_LIM_CH0_S 0 -/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; +#define RMT_TX_LIM_CH2 0x000001FFU +#define RMT_TX_LIM_CH2_M (RMT_TX_LIM_CH2_V << RMT_TX_LIM_CH2_S) +#define RMT_TX_LIM_CH2_V 0x000001FFU +#define RMT_TX_LIM_CH2_S 0 +/** RMT_TX_LOOP_NUM_CH2 : R/W; bitpos: [18:9]; default: 0; * This field is used to configure the maximum loop times when continuous transmission * mode is enabled. */ -#define RMT_TX_LOOP_NUM_CH0 0x000003FFU -#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) -#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU -#define RMT_TX_LOOP_NUM_CH0_S 9 -/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; +#define RMT_TX_LOOP_NUM_CH2 0x000003FFU +#define RMT_TX_LOOP_NUM_CH2_M (RMT_TX_LOOP_NUM_CH2_V << RMT_TX_LOOP_NUM_CH2_S) +#define RMT_TX_LOOP_NUM_CH2_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH2_S 9 +/** RMT_TX_LOOP_CNT_EN_CH2 : R/W; bitpos: [19]; default: 0; * This bit is used to enable loop counting. */ -#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) -#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U -#define RMT_TX_LOOP_CNT_EN_CH0_S 19 -/** RMT_LOOP_COUNT_RESET_CH0 : WO; bitpos: [20]; default: 0; +#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_M (RMT_TX_LOOP_CNT_EN_CH2_V << RMT_TX_LOOP_CNT_EN_CH2_S) +#define RMT_TX_LOOP_CNT_EN_CH2_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH2_S 19 +/** RMT_LOOP_COUNT_RESET_CH2 : WO; bitpos: [20]; default: 0; * This bit is used to reset loop counting when continuous transmission mode is valid. */ -#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) -#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U -#define RMT_LOOP_COUNT_RESET_CH0_S 20 +#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_M (RMT_LOOP_COUNT_RESET_CH2_V << RMT_LOOP_COUNT_RESET_CH2_S) +#define RMT_LOOP_COUNT_RESET_CH2_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH2_S 20 /** RMT_CH3_TX_LIM_REG register * Channel 3 Tx event configuration register */ #define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x7c) -/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; +/** RMT_TX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128; * This field is used to configure the maximum entries that channel 3 can send out. * When RMT_MEM_SIZE_CH3 = 1, this field can be set to any value among 0 ~ 128 * (64*32/16 = 128). When RMT_MEM_SIZE_CH3 > 1, this field can be set to any value * among (0 ~ 128)*RMT_MEM_SIZE_CH3. */ -#define RMT_TX_LIM_CH0 0x000001FFU -#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) -#define RMT_TX_LIM_CH0_V 0x000001FFU -#define RMT_TX_LIM_CH0_S 0 -/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; +#define RMT_TX_LIM_CH3 0x000001FFU +#define RMT_TX_LIM_CH3_M (RMT_TX_LIM_CH3_V << RMT_TX_LIM_CH3_S) +#define RMT_TX_LIM_CH3_V 0x000001FFU +#define RMT_TX_LIM_CH3_S 0 +/** RMT_TX_LOOP_NUM_CH3 : R/W; bitpos: [18:9]; default: 0; * This field is used to configure the maximum loop times when continuous transmission * mode is enabled. */ -#define RMT_TX_LOOP_NUM_CH0 0x000003FFU -#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) -#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU -#define RMT_TX_LOOP_NUM_CH0_S 9 -/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; +#define RMT_TX_LOOP_NUM_CH3 0x000003FFU +#define RMT_TX_LOOP_NUM_CH3_M (RMT_TX_LOOP_NUM_CH3_V << RMT_TX_LOOP_NUM_CH3_S) +#define RMT_TX_LOOP_NUM_CH3_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH3_S 9 +/** RMT_TX_LOOP_CNT_EN_CH3 : R/W; bitpos: [19]; default: 0; * This bit is used to enable loop counting. */ -#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) -#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U -#define RMT_TX_LOOP_CNT_EN_CH0_S 19 -/** RMT_LOOP_COUNT_RESET_CH0 : WO; bitpos: [20]; default: 0; +#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_M (RMT_TX_LOOP_CNT_EN_CH3_V << RMT_TX_LOOP_CNT_EN_CH3_S) +#define RMT_TX_LOOP_CNT_EN_CH3_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH3_S 19 +/** RMT_LOOP_COUNT_RESET_CH3 : WO; bitpos: [20]; default: 0; * This bit is used to reset loop counting when continuous transmission mode is valid. */ -#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) -#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U -#define RMT_LOOP_COUNT_RESET_CH0_S 20 +#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_M (RMT_LOOP_COUNT_RESET_CH3_V << RMT_LOOP_COUNT_RESET_CH3_S) +#define RMT_LOOP_COUNT_RESET_CH3_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH3_S 20 /** RMT_APB_CONF_REG register * RMT APB configuration register @@ -2056,64 +2056,64 @@ extern "C" { * Channel 1 carrier remove register */ #define RMT_CH1_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90) -/** RMT_CARRIER_LOW_THRES_CH0 : R/W; bitpos: [15:0]; default: 0; +/** RMT_CARRIER_LOW_THRES_CH1 : R/W; bitpos: [15:0]; default: 0; * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CH1 + 1) * clock cycles for channel 1. */ -#define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFFU -#define RMT_CARRIER_LOW_THRES_CH0_M (RMT_CARRIER_LOW_THRES_CH0_V << RMT_CARRIER_LOW_THRES_CH0_S) -#define RMT_CARRIER_LOW_THRES_CH0_V 0x0000FFFFU -#define RMT_CARRIER_LOW_THRES_CH0_S 0 -/** RMT_CARRIER_HIGH_THRES_CH0 : R/W; bitpos: [31:16]; default: 0; +#define RMT_CARRIER_LOW_THRES_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH1_M (RMT_CARRIER_LOW_THRES_CH1_V << RMT_CARRIER_LOW_THRES_CH1_S) +#define RMT_CARRIER_LOW_THRES_CH1_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH1_S 0 +/** RMT_CARRIER_HIGH_THRES_CH1 : R/W; bitpos: [31:16]; default: 0; * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CH1 + * 1) clock cycles for channel 1. */ -#define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFFU -#define RMT_CARRIER_HIGH_THRES_CH0_M (RMT_CARRIER_HIGH_THRES_CH0_V << RMT_CARRIER_HIGH_THRES_CH0_S) -#define RMT_CARRIER_HIGH_THRES_CH0_V 0x0000FFFFU -#define RMT_CARRIER_HIGH_THRES_CH0_S 16 +#define RMT_CARRIER_HIGH_THRES_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH1_M (RMT_CARRIER_HIGH_THRES_CH1_V << RMT_CARRIER_HIGH_THRES_CH1_S) +#define RMT_CARRIER_HIGH_THRES_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH1_S 16 /** RMT_CH2_RX_CARRIER_RM_REG register * Channel 2 carrier remove register */ #define RMT_CH2_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94) -/** RMT_CARRIER_LOW_THRES_CH0 : R/W; bitpos: [15:0]; default: 0; +/** RMT_CARRIER_LOW_THRES_CH2 : R/W; bitpos: [15:0]; default: 0; * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CH2 + 1) * clock cycles for channel 2. */ -#define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFFU -#define RMT_CARRIER_LOW_THRES_CH0_M (RMT_CARRIER_LOW_THRES_CH0_V << RMT_CARRIER_LOW_THRES_CH0_S) -#define RMT_CARRIER_LOW_THRES_CH0_V 0x0000FFFFU -#define RMT_CARRIER_LOW_THRES_CH0_S 0 -/** RMT_CARRIER_HIGH_THRES_CH0 : R/W; bitpos: [31:16]; default: 0; +#define RMT_CARRIER_LOW_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_M (RMT_CARRIER_LOW_THRES_CH2_V << RMT_CARRIER_LOW_THRES_CH2_S) +#define RMT_CARRIER_LOW_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH2_S 0 +/** RMT_CARRIER_HIGH_THRES_CH2 : R/W; bitpos: [31:16]; default: 0; * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CH2 + * 1) clock cycles for channel 2. */ -#define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFFU -#define RMT_CARRIER_HIGH_THRES_CH0_M (RMT_CARRIER_HIGH_THRES_CH0_V << RMT_CARRIER_HIGH_THRES_CH0_S) -#define RMT_CARRIER_HIGH_THRES_CH0_V 0x0000FFFFU -#define RMT_CARRIER_HIGH_THRES_CH0_S 16 +#define RMT_CARRIER_HIGH_THRES_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_M (RMT_CARRIER_HIGH_THRES_CH2_V << RMT_CARRIER_HIGH_THRES_CH2_S) +#define RMT_CARRIER_HIGH_THRES_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH2_S 16 /** RMT_CH3_RX_CARRIER_RM_REG register * Channel 3 carrier remove register */ #define RMT_CH3_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98) -/** RMT_CARRIER_LOW_THRES_CH0 : R/W; bitpos: [15:0]; default: 0; +/** RMT_CARRIER_LOW_THRES_CH3 : R/W; bitpos: [15:0]; default: 0; * The low level period in carrier modulation mode is (RMT_CARRIER_LOW_THRES_CH3 + 1) * clock cycles for channel 3. */ -#define RMT_CARRIER_LOW_THRES_CH0 0x0000FFFFU -#define RMT_CARRIER_LOW_THRES_CH0_M (RMT_CARRIER_LOW_THRES_CH0_V << RMT_CARRIER_LOW_THRES_CH0_S) -#define RMT_CARRIER_LOW_THRES_CH0_V 0x0000FFFFU -#define RMT_CARRIER_LOW_THRES_CH0_S 0 -/** RMT_CARRIER_HIGH_THRES_CH0 : R/W; bitpos: [31:16]; default: 0; +#define RMT_CARRIER_LOW_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_M (RMT_CARRIER_LOW_THRES_CH3_V << RMT_CARRIER_LOW_THRES_CH3_S) +#define RMT_CARRIER_LOW_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH3_S 0 +/** RMT_CARRIER_HIGH_THRES_CH3 : R/W; bitpos: [31:16]; default: 0; * The high level period in carrier modulation mode is (RMT_CARRIER_HIGH_THRES_CH3 + * 1) clock cycles for channel 3. */ -#define RMT_CARRIER_HIGH_THRES_CH0 0x0000FFFFU -#define RMT_CARRIER_HIGH_THRES_CH0_M (RMT_CARRIER_HIGH_THRES_CH0_V << RMT_CARRIER_HIGH_THRES_CH0_S) -#define RMT_CARRIER_HIGH_THRES_CH0_V 0x0000FFFFU -#define RMT_CARRIER_HIGH_THRES_CH0_S 16 +#define RMT_CARRIER_HIGH_THRES_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_M (RMT_CARRIER_HIGH_THRES_CH3_V << RMT_CARRIER_HIGH_THRES_CH3_S) +#define RMT_CARRIER_HIGH_THRES_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH3_S 16 /** RMT_DATE_REG register * Version control register diff --git a/components/soc/esp32s3/include/soc/rmt_reg.h b/components/soc/esp32s3/include/soc/rmt_reg.h index 55513e5e97..767467adce 100644 --- a/components/soc/esp32s3/include/soc/rmt_reg.h +++ b/components/soc/esp32s3/include/soc/rmt_reg.h @@ -120,1329 +120,1329 @@ extern "C" { * Channel 0 configure register 0 */ #define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x20) -/** RMT_TX_START_0 : WT; bitpos: [0]; default: 0; +/** RMT_TX_START_CH0 : WT; bitpos: [0]; default: 0; * Set this bit to start sending data on CHANNEL0. */ -#define RMT_TX_START_0 (BIT(0)) -#define RMT_TX_START_0_M (RMT_TX_START_0_V << RMT_TX_START_0_S) -#define RMT_TX_START_0_V 0x00000001U -#define RMT_TX_START_0_S 0 -/** RMT_MEM_RD_RST_0 : WT; bitpos: [1]; default: 0; +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (RMT_TX_START_CH0_V << RMT_TX_START_CH0_S) +#define RMT_TX_START_CH0_V 0x00000001U +#define RMT_TX_START_CH0_S 0 +/** RMT_MEM_RD_RST_CH0 : WT; bitpos: [1]; default: 0; * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. */ -#define RMT_MEM_RD_RST_0 (BIT(1)) -#define RMT_MEM_RD_RST_0_M (RMT_MEM_RD_RST_0_V << RMT_MEM_RD_RST_0_S) -#define RMT_MEM_RD_RST_0_V 0x00000001U -#define RMT_MEM_RD_RST_0_S 1 -/** RMT_APB_MEM_RST_0 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (RMT_MEM_RD_RST_CH0_V << RMT_MEM_RD_RST_CH0_S) +#define RMT_MEM_RD_RST_CH0_V 0x00000001U +#define RMT_MEM_RD_RST_CH0_S 1 +/** RMT_APB_MEM_RST_CH0 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_0 (BIT(2)) -#define RMT_APB_MEM_RST_0_M (RMT_APB_MEM_RST_0_V << RMT_APB_MEM_RST_0_S) -#define RMT_APB_MEM_RST_0_V 0x00000001U -#define RMT_APB_MEM_RST_0_S 2 -/** RMT_TX_CONTI_MODE_0 : R/W; bitpos: [3]; default: 0; +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (RMT_APB_MEM_RST_CH0_V << RMT_APB_MEM_RST_CH0_S) +#define RMT_APB_MEM_RST_CH0_V 0x00000001U +#define RMT_APB_MEM_RST_CH0_S 2 +/** RMT_TX_CONTI_MODE_CH0 : R/W; bitpos: [3]; default: 0; * Set this bit to restart transmission from the first data to the last data in * CHANNEL0. */ -#define RMT_TX_CONTI_MODE_0 (BIT(3)) -#define RMT_TX_CONTI_MODE_0_M (RMT_TX_CONTI_MODE_0_V << RMT_TX_CONTI_MODE_0_S) -#define RMT_TX_CONTI_MODE_0_V 0x00000001U -#define RMT_TX_CONTI_MODE_0_S 3 -/** RMT_MEM_TX_WRAP_EN_0 : R/W; bitpos: [4]; default: 0; +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (RMT_TX_CONTI_MODE_CH0_V << RMT_TX_CONTI_MODE_CH0_S) +#define RMT_TX_CONTI_MODE_CH0_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH0_S 3 +/** RMT_MEM_TX_WRAP_EN_CH0 : R/W; bitpos: [4]; default: 0; * This is the channel 0 enable bit for wraparound mode: it will resume sending at the * start when the data to be sent is more than its memory size. */ -#define RMT_MEM_TX_WRAP_EN_0 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_0_M (RMT_MEM_TX_WRAP_EN_0_V << RMT_MEM_TX_WRAP_EN_0_S) -#define RMT_MEM_TX_WRAP_EN_0_V 0x00000001U -#define RMT_MEM_TX_WRAP_EN_0_S 4 -/** RMT_IDLE_OUT_LV_0 : R/W; bitpos: [5]; default: 0; +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (RMT_MEM_TX_WRAP_EN_CH0_V << RMT_MEM_TX_WRAP_EN_CH0_S) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/** RMT_IDLE_OUT_LV_CH0 : R/W; bitpos: [5]; default: 0; * This bit configures the level of output signal in CHANNEL0 when the latter is in * IDLE state. */ -#define RMT_IDLE_OUT_LV_0 (BIT(5)) -#define RMT_IDLE_OUT_LV_0_M (RMT_IDLE_OUT_LV_0_V << RMT_IDLE_OUT_LV_0_S) -#define RMT_IDLE_OUT_LV_0_V 0x00000001U -#define RMT_IDLE_OUT_LV_0_S 5 -/** RMT_IDLE_OUT_EN_0 : R/W; bitpos: [6]; default: 0; +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (RMT_IDLE_OUT_LV_CH0_V << RMT_IDLE_OUT_LV_CH0_S) +#define RMT_IDLE_OUT_LV_CH0_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH0_S 5 +/** RMT_IDLE_OUT_EN_CH0 : R/W; bitpos: [6]; default: 0; * This is the output enable-control bit for CHANNEL0 in IDLE state. */ -#define RMT_IDLE_OUT_EN_0 (BIT(6)) -#define RMT_IDLE_OUT_EN_0_M (RMT_IDLE_OUT_EN_0_V << RMT_IDLE_OUT_EN_0_S) -#define RMT_IDLE_OUT_EN_0_V 0x00000001U -#define RMT_IDLE_OUT_EN_0_S 6 -/** RMT_TX_STOP_0 : R/W/SC; bitpos: [7]; default: 0; +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (RMT_IDLE_OUT_EN_CH0_V << RMT_IDLE_OUT_EN_CH0_S) +#define RMT_IDLE_OUT_EN_CH0_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH0_S 6 +/** RMT_TX_STOP_CH0 : R/W/SC; bitpos: [7]; default: 0; * Set this bit to stop the transmitter of CHANNEL0 sending data out. */ -#define RMT_TX_STOP_0 (BIT(7)) -#define RMT_TX_STOP_0_M (RMT_TX_STOP_0_V << RMT_TX_STOP_0_S) -#define RMT_TX_STOP_0_V 0x00000001U -#define RMT_TX_STOP_0_S 7 -/** RMT_DIV_CNT_0 : R/W; bitpos: [15:8]; default: 2; +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (RMT_TX_STOP_CH0_V << RMT_TX_STOP_CH0_S) +#define RMT_TX_STOP_CH0_V 0x00000001U +#define RMT_TX_STOP_CH0_S 7 +/** RMT_DIV_CNT_CH0 : R/W; bitpos: [15:8]; default: 2; * This register is used to configure the divider for clock of CHANNEL0. */ -#define RMT_DIV_CNT_0 0x000000FFU -#define RMT_DIV_CNT_0_M (RMT_DIV_CNT_0_V << RMT_DIV_CNT_0_S) -#define RMT_DIV_CNT_0_V 0x000000FFU -#define RMT_DIV_CNT_0_S 8 -/** RMT_MEM_SIZE_0 : R/W; bitpos: [19:16]; default: 1; +#define RMT_DIV_CNT_CH0 0x000000FFU +#define RMT_DIV_CNT_CH0_M (RMT_DIV_CNT_CH0_V << RMT_DIV_CNT_CH0_S) +#define RMT_DIV_CNT_CH0_V 0x000000FFU +#define RMT_DIV_CNT_CH0_S 8 +/** RMT_MEM_SIZE_CH0 : R/W; bitpos: [19:16]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL0. */ -#define RMT_MEM_SIZE_0 0x0000000FU -#define RMT_MEM_SIZE_0_M (RMT_MEM_SIZE_0_V << RMT_MEM_SIZE_0_S) -#define RMT_MEM_SIZE_0_V 0x0000000FU -#define RMT_MEM_SIZE_0_S 16 -/** RMT_CARRIER_EFF_EN_0 : R/W; bitpos: [20]; default: 1; +#define RMT_MEM_SIZE_CH0 0x0000000FU +#define RMT_MEM_SIZE_CH0_M (RMT_MEM_SIZE_CH0_V << RMT_MEM_SIZE_CH0_S) +#define RMT_MEM_SIZE_CH0_V 0x0000000FU +#define RMT_MEM_SIZE_CH0_S 16 +/** RMT_CARRIER_EFF_EN_CH0 : R/W; bitpos: [20]; default: 1; * 1: Add carrier modulation on the output signal only at the send data state for * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. * Only valid when RMT_CARRIER_EN_CH0 is 1. */ -#define RMT_CARRIER_EFF_EN_0 (BIT(20)) -#define RMT_CARRIER_EFF_EN_0_M (RMT_CARRIER_EFF_EN_0_V << RMT_CARRIER_EFF_EN_0_S) -#define RMT_CARRIER_EFF_EN_0_V 0x00000001U -#define RMT_CARRIER_EFF_EN_0_S 20 -/** RMT_CARRIER_EN_0 : R/W; bitpos: [21]; default: 1; +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (RMT_CARRIER_EFF_EN_CH0_V << RMT_CARRIER_EFF_EN_CH0_S) +#define RMT_CARRIER_EFF_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/** RMT_CARRIER_EN_CH0 : R/W; bitpos: [21]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_0 (BIT(21)) -#define RMT_CARRIER_EN_0_M (RMT_CARRIER_EN_0_V << RMT_CARRIER_EN_0_S) -#define RMT_CARRIER_EN_0_V 0x00000001U -#define RMT_CARRIER_EN_0_S 21 -/** RMT_CARRIER_OUT_LV_0 : R/W; bitpos: [22]; default: 1; +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (RMT_CARRIER_EN_CH0_V << RMT_CARRIER_EN_CH0_S) +#define RMT_CARRIER_EN_CH0_V 0x00000001U +#define RMT_CARRIER_EN_CH0_S 21 +/** RMT_CARRIER_OUT_LV_CH0 : R/W; bitpos: [22]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL0. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_0 (BIT(22)) -#define RMT_CARRIER_OUT_LV_0_M (RMT_CARRIER_OUT_LV_0_V << RMT_CARRIER_OUT_LV_0_S) -#define RMT_CARRIER_OUT_LV_0_V 0x00000001U -#define RMT_CARRIER_OUT_LV_0_S 22 -/** RMT_AFIFO_RST_0 : WT; bitpos: [23]; default: 0; +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (RMT_CARRIER_OUT_LV_CH0_V << RMT_CARRIER_OUT_LV_CH0_S) +#define RMT_CARRIER_OUT_LV_CH0_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/** RMT_AFIFO_RST_CH0 : WT; bitpos: [23]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_0 (BIT(23)) -#define RMT_AFIFO_RST_0_M (RMT_AFIFO_RST_0_V << RMT_AFIFO_RST_0_S) -#define RMT_AFIFO_RST_0_V 0x00000001U -#define RMT_AFIFO_RST_0_S 23 -/** RMT_CONF_UPDATE_0 : WT; bitpos: [24]; default: 0; +#define RMT_AFIFO_RST_CH0 (BIT(23)) +#define RMT_AFIFO_RST_CH0_M (RMT_AFIFO_RST_CH0_V << RMT_AFIFO_RST_CH0_S) +#define RMT_AFIFO_RST_CH0_V 0x00000001U +#define RMT_AFIFO_RST_CH0_S 23 +/** RMT_CONF_UPDATE_CH0 : WT; bitpos: [24]; default: 0; * synchronization bit for CHANNEL0 */ -#define RMT_CONF_UPDATE_0 (BIT(24)) -#define RMT_CONF_UPDATE_0_M (RMT_CONF_UPDATE_0_V << RMT_CONF_UPDATE_0_S) -#define RMT_CONF_UPDATE_0_V 0x00000001U -#define RMT_CONF_UPDATE_0_S 24 +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (RMT_CONF_UPDATE_CH0_V << RMT_CONF_UPDATE_CH0_S) +#define RMT_CONF_UPDATE_CH0_V 0x00000001U +#define RMT_CONF_UPDATE_CH0_S 24 /** RMT_CH1CONF0_REG register * Channel 1 configure register 0 */ #define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x24) -/** RMT_TX_START_1 : WT; bitpos: [0]; default: 0; +/** RMT_TX_START_CH1 : WT; bitpos: [0]; default: 0; * Set this bit to start sending data on CHANNEL1. */ -#define RMT_TX_START_1 (BIT(0)) -#define RMT_TX_START_1_M (RMT_TX_START_1_V << RMT_TX_START_1_S) -#define RMT_TX_START_1_V 0x00000001U -#define RMT_TX_START_1_S 0 -/** RMT_MEM_RD_RST_1 : WT; bitpos: [1]; default: 0; +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (RMT_TX_START_CH1_V << RMT_TX_START_CH1_S) +#define RMT_TX_START_CH1_V 0x00000001U +#define RMT_TX_START_CH1_S 0 +/** RMT_MEM_RD_RST_CH1 : WT; bitpos: [1]; default: 0; * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. */ -#define RMT_MEM_RD_RST_1 (BIT(1)) -#define RMT_MEM_RD_RST_1_M (RMT_MEM_RD_RST_1_V << RMT_MEM_RD_RST_1_S) -#define RMT_MEM_RD_RST_1_V 0x00000001U -#define RMT_MEM_RD_RST_1_S 1 -/** RMT_APB_MEM_RST_1 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (RMT_MEM_RD_RST_CH1_V << RMT_MEM_RD_RST_CH1_S) +#define RMT_MEM_RD_RST_CH1_V 0x00000001U +#define RMT_MEM_RD_RST_CH1_S 1 +/** RMT_APB_MEM_RST_CH1 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_1 (BIT(2)) -#define RMT_APB_MEM_RST_1_M (RMT_APB_MEM_RST_1_V << RMT_APB_MEM_RST_1_S) -#define RMT_APB_MEM_RST_1_V 0x00000001U -#define RMT_APB_MEM_RST_1_S 2 -/** RMT_TX_CONTI_MODE_1 : R/W; bitpos: [3]; default: 0; +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (RMT_APB_MEM_RST_CH1_V << RMT_APB_MEM_RST_CH1_S) +#define RMT_APB_MEM_RST_CH1_V 0x00000001U +#define RMT_APB_MEM_RST_CH1_S 2 +/** RMT_TX_CONTI_MODE_CH1 : R/W; bitpos: [3]; default: 0; * Set this bit to restart transmission from the first data to the last data in * CHANNEL1. */ -#define RMT_TX_CONTI_MODE_1 (BIT(3)) -#define RMT_TX_CONTI_MODE_1_M (RMT_TX_CONTI_MODE_1_V << RMT_TX_CONTI_MODE_1_S) -#define RMT_TX_CONTI_MODE_1_V 0x00000001U -#define RMT_TX_CONTI_MODE_1_S 3 -/** RMT_MEM_TX_WRAP_EN_1 : R/W; bitpos: [4]; default: 0; +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (RMT_TX_CONTI_MODE_CH1_V << RMT_TX_CONTI_MODE_CH1_S) +#define RMT_TX_CONTI_MODE_CH1_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH1_S 3 +/** RMT_MEM_TX_WRAP_EN_CH1 : R/W; bitpos: [4]; default: 0; * This is the channel 1 enable bit for wraparound mode: it will resume sending at the * start when the data to be sent is more than its memory size. */ -#define RMT_MEM_TX_WRAP_EN_1 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_1_M (RMT_MEM_TX_WRAP_EN_1_V << RMT_MEM_TX_WRAP_EN_1_S) -#define RMT_MEM_TX_WRAP_EN_1_V 0x00000001U -#define RMT_MEM_TX_WRAP_EN_1_S 4 -/** RMT_IDLE_OUT_LV_1 : R/W; bitpos: [5]; default: 0; +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (RMT_MEM_TX_WRAP_EN_CH1_V << RMT_MEM_TX_WRAP_EN_CH1_S) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/** RMT_IDLE_OUT_LV_CH1 : R/W; bitpos: [5]; default: 0; * This bit configures the level of output signal in CHANNEL1 when the latter is in * IDLE state. */ -#define RMT_IDLE_OUT_LV_1 (BIT(5)) -#define RMT_IDLE_OUT_LV_1_M (RMT_IDLE_OUT_LV_1_V << RMT_IDLE_OUT_LV_1_S) -#define RMT_IDLE_OUT_LV_1_V 0x00000001U -#define RMT_IDLE_OUT_LV_1_S 5 -/** RMT_IDLE_OUT_EN_1 : R/W; bitpos: [6]; default: 0; +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (RMT_IDLE_OUT_LV_CH1_V << RMT_IDLE_OUT_LV_CH1_S) +#define RMT_IDLE_OUT_LV_CH1_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH1_S 5 +/** RMT_IDLE_OUT_EN_CH1 : R/W; bitpos: [6]; default: 0; * This is the output enable-control bit for CHANNEL1 in IDLE state. */ -#define RMT_IDLE_OUT_EN_1 (BIT(6)) -#define RMT_IDLE_OUT_EN_1_M (RMT_IDLE_OUT_EN_1_V << RMT_IDLE_OUT_EN_1_S) -#define RMT_IDLE_OUT_EN_1_V 0x00000001U -#define RMT_IDLE_OUT_EN_1_S 6 -/** RMT_TX_STOP_1 : R/W/SC; bitpos: [7]; default: 0; +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (RMT_IDLE_OUT_EN_CH1_V << RMT_IDLE_OUT_EN_CH1_S) +#define RMT_IDLE_OUT_EN_CH1_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH1_S 6 +/** RMT_TX_STOP_CH1 : R/W/SC; bitpos: [7]; default: 0; * Set this bit to stop the transmitter of CHANNEL1 sending data out. */ -#define RMT_TX_STOP_1 (BIT(7)) -#define RMT_TX_STOP_1_M (RMT_TX_STOP_1_V << RMT_TX_STOP_1_S) -#define RMT_TX_STOP_1_V 0x00000001U -#define RMT_TX_STOP_1_S 7 -/** RMT_DIV_CNT_1 : R/W; bitpos: [15:8]; default: 2; +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (RMT_TX_STOP_CH1_V << RMT_TX_STOP_CH1_S) +#define RMT_TX_STOP_CH1_V 0x00000001U +#define RMT_TX_STOP_CH1_S 7 +/** RMT_DIV_CNT_CH1 : R/W; bitpos: [15:8]; default: 2; * This register is used to configure the divider for clock of CHANNEL1. */ -#define RMT_DIV_CNT_1 0x000000FFU -#define RMT_DIV_CNT_1_M (RMT_DIV_CNT_1_V << RMT_DIV_CNT_1_S) -#define RMT_DIV_CNT_1_V 0x000000FFU -#define RMT_DIV_CNT_1_S 8 -/** RMT_MEM_SIZE_1 : R/W; bitpos: [19:16]; default: 1; +#define RMT_DIV_CNT_CH1 0x000000FFU +#define RMT_DIV_CNT_CH1_M (RMT_DIV_CNT_CH1_V << RMT_DIV_CNT_CH1_S) +#define RMT_DIV_CNT_CH1_V 0x000000FFU +#define RMT_DIV_CNT_CH1_S 8 +/** RMT_MEM_SIZE_CH1 : R/W; bitpos: [19:16]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL1. */ -#define RMT_MEM_SIZE_1 0x0000000FU -#define RMT_MEM_SIZE_1_M (RMT_MEM_SIZE_1_V << RMT_MEM_SIZE_1_S) -#define RMT_MEM_SIZE_1_V 0x0000000FU -#define RMT_MEM_SIZE_1_S 16 -/** RMT_CARRIER_EFF_EN_1 : R/W; bitpos: [20]; default: 1; +#define RMT_MEM_SIZE_CH1 0x0000000FU +#define RMT_MEM_SIZE_CH1_M (RMT_MEM_SIZE_CH1_V << RMT_MEM_SIZE_CH1_S) +#define RMT_MEM_SIZE_CH1_V 0x0000000FU +#define RMT_MEM_SIZE_CH1_S 16 +/** RMT_CARRIER_EFF_EN_CH1 : R/W; bitpos: [20]; default: 1; * 1: Add carrier modulation on the output signal only at the send data state for * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. * Only valid when RMT_CARRIER_EN_CH1 is 1. */ -#define RMT_CARRIER_EFF_EN_1 (BIT(20)) -#define RMT_CARRIER_EFF_EN_1_M (RMT_CARRIER_EFF_EN_1_V << RMT_CARRIER_EFF_EN_1_S) -#define RMT_CARRIER_EFF_EN_1_V 0x00000001U -#define RMT_CARRIER_EFF_EN_1_S 20 -/** RMT_CARRIER_EN_1 : R/W; bitpos: [21]; default: 1; +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (RMT_CARRIER_EFF_EN_CH1_V << RMT_CARRIER_EFF_EN_CH1_S) +#define RMT_CARRIER_EFF_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/** RMT_CARRIER_EN_CH1 : R/W; bitpos: [21]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_1 (BIT(21)) -#define RMT_CARRIER_EN_1_M (RMT_CARRIER_EN_1_V << RMT_CARRIER_EN_1_S) -#define RMT_CARRIER_EN_1_V 0x00000001U -#define RMT_CARRIER_EN_1_S 21 -/** RMT_CARRIER_OUT_LV_1 : R/W; bitpos: [22]; default: 1; +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (RMT_CARRIER_EN_CH1_V << RMT_CARRIER_EN_CH1_S) +#define RMT_CARRIER_EN_CH1_V 0x00000001U +#define RMT_CARRIER_EN_CH1_S 21 +/** RMT_CARRIER_OUT_LV_CH1 : R/W; bitpos: [22]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL1. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_1 (BIT(22)) -#define RMT_CARRIER_OUT_LV_1_M (RMT_CARRIER_OUT_LV_1_V << RMT_CARRIER_OUT_LV_1_S) -#define RMT_CARRIER_OUT_LV_1_V 0x00000001U -#define RMT_CARRIER_OUT_LV_1_S 22 -/** RMT_AFIFO_RST_1 : WT; bitpos: [23]; default: 0; +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (RMT_CARRIER_OUT_LV_CH1_V << RMT_CARRIER_OUT_LV_CH1_S) +#define RMT_CARRIER_OUT_LV_CH1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/** RMT_AFIFO_RST_CH1 : WT; bitpos: [23]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_1 (BIT(23)) -#define RMT_AFIFO_RST_1_M (RMT_AFIFO_RST_1_V << RMT_AFIFO_RST_1_S) -#define RMT_AFIFO_RST_1_V 0x00000001U -#define RMT_AFIFO_RST_1_S 23 -/** RMT_CONF_UPDATE_1 : WT; bitpos: [24]; default: 0; +#define RMT_AFIFO_RST_CH1 (BIT(23)) +#define RMT_AFIFO_RST_CH1_M (RMT_AFIFO_RST_CH1_V << RMT_AFIFO_RST_CH1_S) +#define RMT_AFIFO_RST_CH1_V 0x00000001U +#define RMT_AFIFO_RST_CH1_S 23 +/** RMT_CONF_UPDATE_CH1 : WT; bitpos: [24]; default: 0; * synchronization bit for CHANNEL1 */ -#define RMT_CONF_UPDATE_1 (BIT(24)) -#define RMT_CONF_UPDATE_1_M (RMT_CONF_UPDATE_1_V << RMT_CONF_UPDATE_1_S) -#define RMT_CONF_UPDATE_1_V 0x00000001U -#define RMT_CONF_UPDATE_1_S 24 +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (RMT_CONF_UPDATE_CH1_V << RMT_CONF_UPDATE_CH1_S) +#define RMT_CONF_UPDATE_CH1_V 0x00000001U +#define RMT_CONF_UPDATE_CH1_S 24 /** RMT_CH2CONF0_REG register * Channel 2 configure register 0 */ #define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x28) -/** RMT_TX_START_2 : WT; bitpos: [0]; default: 0; +/** RMT_TX_START_CH2 : WT; bitpos: [0]; default: 0; * Set this bit to start sending data on CHANNEL2. */ -#define RMT_TX_START_2 (BIT(0)) -#define RMT_TX_START_2_M (RMT_TX_START_2_V << RMT_TX_START_2_S) -#define RMT_TX_START_2_V 0x00000001U -#define RMT_TX_START_2_S 0 -/** RMT_MEM_RD_RST_2 : WT; bitpos: [1]; default: 0; +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (RMT_TX_START_CH2_V << RMT_TX_START_CH2_S) +#define RMT_TX_START_CH2_V 0x00000001U +#define RMT_TX_START_CH2_S 0 +/** RMT_MEM_RD_RST_CH2 : WT; bitpos: [1]; default: 0; * Set this bit to reset read ram address for CHANNEL2 by accessing transmitter. */ -#define RMT_MEM_RD_RST_2 (BIT(1)) -#define RMT_MEM_RD_RST_2_M (RMT_MEM_RD_RST_2_V << RMT_MEM_RD_RST_2_S) -#define RMT_MEM_RD_RST_2_V 0x00000001U -#define RMT_MEM_RD_RST_2_S 1 -/** RMT_APB_MEM_RST_2 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_RD_RST_CH2 (BIT(1)) +#define RMT_MEM_RD_RST_CH2_M (RMT_MEM_RD_RST_CH2_V << RMT_MEM_RD_RST_CH2_S) +#define RMT_MEM_RD_RST_CH2_V 0x00000001U +#define RMT_MEM_RD_RST_CH2_S 1 +/** RMT_APB_MEM_RST_CH2 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_2 (BIT(2)) -#define RMT_APB_MEM_RST_2_M (RMT_APB_MEM_RST_2_V << RMT_APB_MEM_RST_2_S) -#define RMT_APB_MEM_RST_2_V 0x00000001U -#define RMT_APB_MEM_RST_2_S 2 -/** RMT_TX_CONTI_MODE_2 : R/W; bitpos: [3]; default: 0; +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (RMT_APB_MEM_RST_CH2_V << RMT_APB_MEM_RST_CH2_S) +#define RMT_APB_MEM_RST_CH2_V 0x00000001U +#define RMT_APB_MEM_RST_CH2_S 2 +/** RMT_TX_CONTI_MODE_CH2 : R/W; bitpos: [3]; default: 0; * Set this bit to restart transmission from the first data to the last data in * CHANNEL2. */ -#define RMT_TX_CONTI_MODE_2 (BIT(3)) -#define RMT_TX_CONTI_MODE_2_M (RMT_TX_CONTI_MODE_2_V << RMT_TX_CONTI_MODE_2_S) -#define RMT_TX_CONTI_MODE_2_V 0x00000001U -#define RMT_TX_CONTI_MODE_2_S 3 -/** RMT_MEM_TX_WRAP_EN_2 : R/W; bitpos: [4]; default: 0; +#define RMT_TX_CONTI_MODE_CH2 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH2_M (RMT_TX_CONTI_MODE_CH2_V << RMT_TX_CONTI_MODE_CH2_S) +#define RMT_TX_CONTI_MODE_CH2_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH2_S 3 +/** RMT_MEM_TX_WRAP_EN_CH2 : R/W; bitpos: [4]; default: 0; * This is the channel 2 enable bit for wraparound mode: it will resume sending at the * start when the data to be sent is more than its memory size. */ -#define RMT_MEM_TX_WRAP_EN_2 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_2_M (RMT_MEM_TX_WRAP_EN_2_V << RMT_MEM_TX_WRAP_EN_2_S) -#define RMT_MEM_TX_WRAP_EN_2_V 0x00000001U -#define RMT_MEM_TX_WRAP_EN_2_S 4 -/** RMT_IDLE_OUT_LV_2 : R/W; bitpos: [5]; default: 0; +#define RMT_MEM_TX_WRAP_EN_CH2 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH2_M (RMT_MEM_TX_WRAP_EN_CH2_V << RMT_MEM_TX_WRAP_EN_CH2_S) +#define RMT_MEM_TX_WRAP_EN_CH2_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH2_S 4 +/** RMT_IDLE_OUT_LV_CH2 : R/W; bitpos: [5]; default: 0; * This bit configures the level of output signal in CHANNEL2 when the latter is in * IDLE state. */ -#define RMT_IDLE_OUT_LV_2 (BIT(5)) -#define RMT_IDLE_OUT_LV_2_M (RMT_IDLE_OUT_LV_2_V << RMT_IDLE_OUT_LV_2_S) -#define RMT_IDLE_OUT_LV_2_V 0x00000001U -#define RMT_IDLE_OUT_LV_2_S 5 -/** RMT_IDLE_OUT_EN_2 : R/W; bitpos: [6]; default: 0; +#define RMT_IDLE_OUT_LV_CH2 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH2_M (RMT_IDLE_OUT_LV_CH2_V << RMT_IDLE_OUT_LV_CH2_S) +#define RMT_IDLE_OUT_LV_CH2_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH2_S 5 +/** RMT_IDLE_OUT_EN_CH2 : R/W; bitpos: [6]; default: 0; * This is the output enable-control bit for CHANNEL2 in IDLE state. */ -#define RMT_IDLE_OUT_EN_2 (BIT(6)) -#define RMT_IDLE_OUT_EN_2_M (RMT_IDLE_OUT_EN_2_V << RMT_IDLE_OUT_EN_2_S) -#define RMT_IDLE_OUT_EN_2_V 0x00000001U -#define RMT_IDLE_OUT_EN_2_S 6 -/** RMT_TX_STOP_2 : R/W/SC; bitpos: [7]; default: 0; +#define RMT_IDLE_OUT_EN_CH2 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH2_M (RMT_IDLE_OUT_EN_CH2_V << RMT_IDLE_OUT_EN_CH2_S) +#define RMT_IDLE_OUT_EN_CH2_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH2_S 6 +/** RMT_TX_STOP_CH2 : R/W/SC; bitpos: [7]; default: 0; * Set this bit to stop the transmitter of CHANNEL2 sending data out. */ -#define RMT_TX_STOP_2 (BIT(7)) -#define RMT_TX_STOP_2_M (RMT_TX_STOP_2_V << RMT_TX_STOP_2_S) -#define RMT_TX_STOP_2_V 0x00000001U -#define RMT_TX_STOP_2_S 7 -/** RMT_DIV_CNT_2 : R/W; bitpos: [15:8]; default: 2; +#define RMT_TX_STOP_CH2 (BIT(7)) +#define RMT_TX_STOP_CH2_M (RMT_TX_STOP_CH2_V << RMT_TX_STOP_CH2_S) +#define RMT_TX_STOP_CH2_V 0x00000001U +#define RMT_TX_STOP_CH2_S 7 +/** RMT_DIV_CNT_CH2 : R/W; bitpos: [15:8]; default: 2; * This register is used to configure the divider for clock of CHANNEL2. */ -#define RMT_DIV_CNT_2 0x000000FFU -#define RMT_DIV_CNT_2_M (RMT_DIV_CNT_2_V << RMT_DIV_CNT_2_S) -#define RMT_DIV_CNT_2_V 0x000000FFU -#define RMT_DIV_CNT_2_S 8 -/** RMT_MEM_SIZE_2 : R/W; bitpos: [19:16]; default: 1; +#define RMT_DIV_CNT_CH2 0x000000FFU +#define RMT_DIV_CNT_CH2_M (RMT_DIV_CNT_CH2_V << RMT_DIV_CNT_CH2_S) +#define RMT_DIV_CNT_CH2_V 0x000000FFU +#define RMT_DIV_CNT_CH2_S 8 +/** RMT_MEM_SIZE_CH2 : R/W; bitpos: [19:16]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL2. */ -#define RMT_MEM_SIZE_2 0x0000000FU -#define RMT_MEM_SIZE_2_M (RMT_MEM_SIZE_2_V << RMT_MEM_SIZE_2_S) -#define RMT_MEM_SIZE_2_V 0x0000000FU -#define RMT_MEM_SIZE_2_S 16 -/** RMT_CARRIER_EFF_EN_2 : R/W; bitpos: [20]; default: 1; +#define RMT_MEM_SIZE_CH2 0x0000000FU +#define RMT_MEM_SIZE_CH2_M (RMT_MEM_SIZE_CH2_V << RMT_MEM_SIZE_CH2_S) +#define RMT_MEM_SIZE_CH2_V 0x0000000FU +#define RMT_MEM_SIZE_CH2_S 16 +/** RMT_CARRIER_EFF_EN_CH2 : R/W; bitpos: [20]; default: 1; * 1: Add carrier modulation on the output signal only at the send data state for * CHANNEL2. 0: Add carrier modulation on the output signal at all state for CHANNEL2. * Only valid when RMT_CARRIER_EN_CH2 is 1. */ -#define RMT_CARRIER_EFF_EN_2 (BIT(20)) -#define RMT_CARRIER_EFF_EN_2_M (RMT_CARRIER_EFF_EN_2_V << RMT_CARRIER_EFF_EN_2_S) -#define RMT_CARRIER_EFF_EN_2_V 0x00000001U -#define RMT_CARRIER_EFF_EN_2_S 20 -/** RMT_CARRIER_EN_2 : R/W; bitpos: [21]; default: 1; +#define RMT_CARRIER_EFF_EN_CH2 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH2_M (RMT_CARRIER_EFF_EN_CH2_V << RMT_CARRIER_EFF_EN_CH2_S) +#define RMT_CARRIER_EFF_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH2_S 20 +/** RMT_CARRIER_EN_CH2 : R/W; bitpos: [21]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_2 (BIT(21)) -#define RMT_CARRIER_EN_2_M (RMT_CARRIER_EN_2_V << RMT_CARRIER_EN_2_S) -#define RMT_CARRIER_EN_2_V 0x00000001U -#define RMT_CARRIER_EN_2_S 21 -/** RMT_CARRIER_OUT_LV_2 : R/W; bitpos: [22]; default: 1; +#define RMT_CARRIER_EN_CH2 (BIT(21)) +#define RMT_CARRIER_EN_CH2_M (RMT_CARRIER_EN_CH2_V << RMT_CARRIER_EN_CH2_S) +#define RMT_CARRIER_EN_CH2_V 0x00000001U +#define RMT_CARRIER_EN_CH2_S 21 +/** RMT_CARRIER_OUT_LV_CH2 : R/W; bitpos: [22]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL2. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_2 (BIT(22)) -#define RMT_CARRIER_OUT_LV_2_M (RMT_CARRIER_OUT_LV_2_V << RMT_CARRIER_OUT_LV_2_S) -#define RMT_CARRIER_OUT_LV_2_V 0x00000001U -#define RMT_CARRIER_OUT_LV_2_S 22 -/** RMT_AFIFO_RST_2 : WT; bitpos: [23]; default: 0; +#define RMT_CARRIER_OUT_LV_CH2 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH2_M (RMT_CARRIER_OUT_LV_CH2_V << RMT_CARRIER_OUT_LV_CH2_S) +#define RMT_CARRIER_OUT_LV_CH2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH2_S 22 +/** RMT_AFIFO_RST_CH2 : WT; bitpos: [23]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_2 (BIT(23)) -#define RMT_AFIFO_RST_2_M (RMT_AFIFO_RST_2_V << RMT_AFIFO_RST_2_S) -#define RMT_AFIFO_RST_2_V 0x00000001U -#define RMT_AFIFO_RST_2_S 23 -/** RMT_CONF_UPDATE_2 : WT; bitpos: [24]; default: 0; +#define RMT_AFIFO_RST_CH2 (BIT(23)) +#define RMT_AFIFO_RST_CH2_M (RMT_AFIFO_RST_CH2_V << RMT_AFIFO_RST_CH2_S) +#define RMT_AFIFO_RST_CH2_V 0x00000001U +#define RMT_AFIFO_RST_CH2_S 23 +/** RMT_CONF_UPDATE_CH2 : WT; bitpos: [24]; default: 0; * synchronization bit for CHANNEL2 */ -#define RMT_CONF_UPDATE_2 (BIT(24)) -#define RMT_CONF_UPDATE_2_M (RMT_CONF_UPDATE_2_V << RMT_CONF_UPDATE_2_S) -#define RMT_CONF_UPDATE_2_V 0x00000001U -#define RMT_CONF_UPDATE_2_S 24 +#define RMT_CONF_UPDATE_CH2 (BIT(24)) +#define RMT_CONF_UPDATE_CH2_M (RMT_CONF_UPDATE_CH2_V << RMT_CONF_UPDATE_CH2_S) +#define RMT_CONF_UPDATE_CH2_V 0x00000001U +#define RMT_CONF_UPDATE_CH2_S 24 /** RMT_CH3CONF0_REG register * Channel 3 configure register 0 */ #define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x2c) -/** RMT_TX_START_3 : WT; bitpos: [0]; default: 0; +/** RMT_TX_START_CH3 : WT; bitpos: [0]; default: 0; * Set this bit to start sending data on CHANNEL3. */ -#define RMT_TX_START_3 (BIT(0)) -#define RMT_TX_START_3_M (RMT_TX_START_3_V << RMT_TX_START_3_S) -#define RMT_TX_START_3_V 0x00000001U -#define RMT_TX_START_3_S 0 -/** RMT_MEM_RD_RST_3 : WT; bitpos: [1]; default: 0; +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (RMT_TX_START_CH3_V << RMT_TX_START_CH3_S) +#define RMT_TX_START_CH3_V 0x00000001U +#define RMT_TX_START_CH3_S 0 +/** RMT_MEM_RD_RST_CH3 : WT; bitpos: [1]; default: 0; * Set this bit to reset read ram address for CHANNEL3 by accessing transmitter. */ -#define RMT_MEM_RD_RST_3 (BIT(1)) -#define RMT_MEM_RD_RST_3_M (RMT_MEM_RD_RST_3_V << RMT_MEM_RD_RST_3_S) -#define RMT_MEM_RD_RST_3_V 0x00000001U -#define RMT_MEM_RD_RST_3_S 1 -/** RMT_APB_MEM_RST_3 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_RD_RST_CH3 (BIT(1)) +#define RMT_MEM_RD_RST_CH3_M (RMT_MEM_RD_RST_CH3_V << RMT_MEM_RD_RST_CH3_S) +#define RMT_MEM_RD_RST_CH3_V 0x00000001U +#define RMT_MEM_RD_RST_CH3_S 1 +/** RMT_APB_MEM_RST_CH3 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_3 (BIT(2)) -#define RMT_APB_MEM_RST_3_M (RMT_APB_MEM_RST_3_V << RMT_APB_MEM_RST_3_S) -#define RMT_APB_MEM_RST_3_V 0x00000001U -#define RMT_APB_MEM_RST_3_S 2 -/** RMT_TX_CONTI_MODE_3 : R/W; bitpos: [3]; default: 0; +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (RMT_APB_MEM_RST_CH3_V << RMT_APB_MEM_RST_CH3_S) +#define RMT_APB_MEM_RST_CH3_V 0x00000001U +#define RMT_APB_MEM_RST_CH3_S 2 +/** RMT_TX_CONTI_MODE_CH3 : R/W; bitpos: [3]; default: 0; * Set this bit to restart transmission from the first data to the last data in * CHANNEL3. */ -#define RMT_TX_CONTI_MODE_3 (BIT(3)) -#define RMT_TX_CONTI_MODE_3_M (RMT_TX_CONTI_MODE_3_V << RMT_TX_CONTI_MODE_3_S) -#define RMT_TX_CONTI_MODE_3_V 0x00000001U -#define RMT_TX_CONTI_MODE_3_S 3 -/** RMT_MEM_TX_WRAP_EN_3 : R/W; bitpos: [4]; default: 0; +#define RMT_TX_CONTI_MODE_CH3 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH3_M (RMT_TX_CONTI_MODE_CH3_V << RMT_TX_CONTI_MODE_CH3_S) +#define RMT_TX_CONTI_MODE_CH3_V 0x00000001U +#define RMT_TX_CONTI_MODE_CH3_S 3 +/** RMT_MEM_TX_WRAP_EN_CH3 : R/W; bitpos: [4]; default: 0; * This is the channel 3 enable bit for wraparound mode: it will resume sending at the * start when the data to be sent is more than its memory size. */ -#define RMT_MEM_TX_WRAP_EN_3 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_3_M (RMT_MEM_TX_WRAP_EN_3_V << RMT_MEM_TX_WRAP_EN_3_S) -#define RMT_MEM_TX_WRAP_EN_3_V 0x00000001U -#define RMT_MEM_TX_WRAP_EN_3_S 4 -/** RMT_IDLE_OUT_LV_3 : R/W; bitpos: [5]; default: 0; +#define RMT_MEM_TX_WRAP_EN_CH3 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH3_M (RMT_MEM_TX_WRAP_EN_CH3_V << RMT_MEM_TX_WRAP_EN_CH3_S) +#define RMT_MEM_TX_WRAP_EN_CH3_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_CH3_S 4 +/** RMT_IDLE_OUT_LV_CH3 : R/W; bitpos: [5]; default: 0; * This bit configures the level of output signal in CHANNEL3 when the latter is in * IDLE state. */ -#define RMT_IDLE_OUT_LV_3 (BIT(5)) -#define RMT_IDLE_OUT_LV_3_M (RMT_IDLE_OUT_LV_3_V << RMT_IDLE_OUT_LV_3_S) -#define RMT_IDLE_OUT_LV_3_V 0x00000001U -#define RMT_IDLE_OUT_LV_3_S 5 -/** RMT_IDLE_OUT_EN_3 : R/W; bitpos: [6]; default: 0; +#define RMT_IDLE_OUT_LV_CH3 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH3_M (RMT_IDLE_OUT_LV_CH3_V << RMT_IDLE_OUT_LV_CH3_S) +#define RMT_IDLE_OUT_LV_CH3_V 0x00000001U +#define RMT_IDLE_OUT_LV_CH3_S 5 +/** RMT_IDLE_OUT_EN_CH3 : R/W; bitpos: [6]; default: 0; * This is the output enable-control bit for CHANNEL3 in IDLE state. */ -#define RMT_IDLE_OUT_EN_3 (BIT(6)) -#define RMT_IDLE_OUT_EN_3_M (RMT_IDLE_OUT_EN_3_V << RMT_IDLE_OUT_EN_3_S) -#define RMT_IDLE_OUT_EN_3_V 0x00000001U -#define RMT_IDLE_OUT_EN_3_S 6 -/** RMT_TX_STOP_3 : R/W/SC; bitpos: [7]; default: 0; +#define RMT_IDLE_OUT_EN_CH3 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH3_M (RMT_IDLE_OUT_EN_CH3_V << RMT_IDLE_OUT_EN_CH3_S) +#define RMT_IDLE_OUT_EN_CH3_V 0x00000001U +#define RMT_IDLE_OUT_EN_CH3_S 6 +/** RMT_TX_STOP_CH3 : R/W/SC; bitpos: [7]; default: 0; * Set this bit to stop the transmitter of CHANNEL3 sending data out. */ -#define RMT_TX_STOP_3 (BIT(7)) -#define RMT_TX_STOP_3_M (RMT_TX_STOP_3_V << RMT_TX_STOP_3_S) -#define RMT_TX_STOP_3_V 0x00000001U -#define RMT_TX_STOP_3_S 7 -/** RMT_DIV_CNT_3 : R/W; bitpos: [15:8]; default: 2; +#define RMT_TX_STOP_CH3 (BIT(7)) +#define RMT_TX_STOP_CH3_M (RMT_TX_STOP_CH3_V << RMT_TX_STOP_CH3_S) +#define RMT_TX_STOP_CH3_V 0x00000001U +#define RMT_TX_STOP_CH3_S 7 +/** RMT_DIV_CNT_CH3 : R/W; bitpos: [15:8]; default: 2; * This register is used to configure the divider for clock of CHANNEL3. */ -#define RMT_DIV_CNT_3 0x000000FFU -#define RMT_DIV_CNT_3_M (RMT_DIV_CNT_3_V << RMT_DIV_CNT_3_S) -#define RMT_DIV_CNT_3_V 0x000000FFU -#define RMT_DIV_CNT_3_S 8 -/** RMT_MEM_SIZE_3 : R/W; bitpos: [19:16]; default: 1; +#define RMT_DIV_CNT_CH3 0x000000FFU +#define RMT_DIV_CNT_CH3_M (RMT_DIV_CNT_CH3_V << RMT_DIV_CNT_CH3_S) +#define RMT_DIV_CNT_CH3_V 0x000000FFU +#define RMT_DIV_CNT_CH3_S 8 +/** RMT_MEM_SIZE_CH3 : R/W; bitpos: [19:16]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL3. */ -#define RMT_MEM_SIZE_3 0x0000000FU -#define RMT_MEM_SIZE_3_M (RMT_MEM_SIZE_3_V << RMT_MEM_SIZE_3_S) -#define RMT_MEM_SIZE_3_V 0x0000000FU -#define RMT_MEM_SIZE_3_S 16 -/** RMT_CARRIER_EFF_EN_3 : R/W; bitpos: [20]; default: 1; +#define RMT_MEM_SIZE_CH3 0x0000000FU +#define RMT_MEM_SIZE_CH3_M (RMT_MEM_SIZE_CH3_V << RMT_MEM_SIZE_CH3_S) +#define RMT_MEM_SIZE_CH3_V 0x0000000FU +#define RMT_MEM_SIZE_CH3_S 16 +/** RMT_CARRIER_EFF_EN_CH3 : R/W; bitpos: [20]; default: 1; * 1: Add carrier modulation on the output signal only at the send data state for * CHANNEL3. 0: Add carrier modulation on the output signal at all state for CHANNEL3. * Only valid when RMT_CARRIER_EN_CH3 is 1. */ -#define RMT_CARRIER_EFF_EN_3 (BIT(20)) -#define RMT_CARRIER_EFF_EN_3_M (RMT_CARRIER_EFF_EN_3_V << RMT_CARRIER_EFF_EN_3_S) -#define RMT_CARRIER_EFF_EN_3_V 0x00000001U -#define RMT_CARRIER_EFF_EN_3_S 20 -/** RMT_CARRIER_EN_3 : R/W; bitpos: [21]; default: 1; +#define RMT_CARRIER_EFF_EN_CH3 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH3_M (RMT_CARRIER_EFF_EN_CH3_V << RMT_CARRIER_EFF_EN_CH3_S) +#define RMT_CARRIER_EFF_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EFF_EN_CH3_S 20 +/** RMT_CARRIER_EN_CH3 : R/W; bitpos: [21]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_3 (BIT(21)) -#define RMT_CARRIER_EN_3_M (RMT_CARRIER_EN_3_V << RMT_CARRIER_EN_3_S) -#define RMT_CARRIER_EN_3_V 0x00000001U -#define RMT_CARRIER_EN_3_S 21 -/** RMT_CARRIER_OUT_LV_3 : R/W; bitpos: [22]; default: 1; +#define RMT_CARRIER_EN_CH3 (BIT(21)) +#define RMT_CARRIER_EN_CH3_M (RMT_CARRIER_EN_CH3_V << RMT_CARRIER_EN_CH3_S) +#define RMT_CARRIER_EN_CH3_V 0x00000001U +#define RMT_CARRIER_EN_CH3_S 21 +/** RMT_CARRIER_OUT_LV_CH3 : R/W; bitpos: [22]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL3. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_3 (BIT(22)) -#define RMT_CARRIER_OUT_LV_3_M (RMT_CARRIER_OUT_LV_3_V << RMT_CARRIER_OUT_LV_3_S) -#define RMT_CARRIER_OUT_LV_3_V 0x00000001U -#define RMT_CARRIER_OUT_LV_3_S 22 -/** RMT_AFIFO_RST_3 : WT; bitpos: [23]; default: 0; +#define RMT_CARRIER_OUT_LV_CH3 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH3_M (RMT_CARRIER_OUT_LV_CH3_V << RMT_CARRIER_OUT_LV_CH3_S) +#define RMT_CARRIER_OUT_LV_CH3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH3_S 22 +/** RMT_AFIFO_RST_CH3 : WT; bitpos: [23]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_3 (BIT(23)) -#define RMT_AFIFO_RST_3_M (RMT_AFIFO_RST_3_V << RMT_AFIFO_RST_3_S) -#define RMT_AFIFO_RST_3_V 0x00000001U -#define RMT_AFIFO_RST_3_S 23 -/** RMT_CONF_UPDATE_3 : WT; bitpos: [24]; default: 0; +#define RMT_AFIFO_RST_CH3 (BIT(23)) +#define RMT_AFIFO_RST_CH3_M (RMT_AFIFO_RST_CH3_V << RMT_AFIFO_RST_CH3_S) +#define RMT_AFIFO_RST_CH3_V 0x00000001U +#define RMT_AFIFO_RST_CH3_S 23 +/** RMT_CONF_UPDATE_CH3 : WT; bitpos: [24]; default: 0; * synchronization bit for CHANNEL3 */ -#define RMT_CONF_UPDATE_3 (BIT(24)) -#define RMT_CONF_UPDATE_3_M (RMT_CONF_UPDATE_3_V << RMT_CONF_UPDATE_3_S) -#define RMT_CONF_UPDATE_3_V 0x00000001U -#define RMT_CONF_UPDATE_3_S 24 +#define RMT_CONF_UPDATE_CH3 (BIT(24)) +#define RMT_CONF_UPDATE_CH3_M (RMT_CONF_UPDATE_CH3_V << RMT_CONF_UPDATE_CH3_S) +#define RMT_CONF_UPDATE_CH3_V 0x00000001U +#define RMT_CONF_UPDATE_CH3_S 24 /** RMT_CH4CONF0_REG register * Channel 4 configure register 0 */ #define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x30) -/** RMT_DIV_CNT_4 : R/W; bitpos: [7:0]; default: 2; +/** RMT_DIV_CNT_CH4 : R/W; bitpos: [7:0]; default: 2; * This register is used to configure the divider for clock of CHANNEL4. */ -#define RMT_DIV_CNT_4 0x000000FFU -#define RMT_DIV_CNT_4_M (RMT_DIV_CNT_4_V << RMT_DIV_CNT_4_S) -#define RMT_DIV_CNT_4_V 0x000000FFU -#define RMT_DIV_CNT_4_S 0 -/** RMT_IDLE_THRES_4 : R/W; bitpos: [22:8]; default: 32767; +#define RMT_DIV_CNT_CH4 0x000000FFU +#define RMT_DIV_CNT_CH4_M (RMT_DIV_CNT_CH4_V << RMT_DIV_CNT_CH4_S) +#define RMT_DIV_CNT_CH4_V 0x000000FFU +#define RMT_DIV_CNT_CH4_S 0 +/** RMT_IDLE_THRES_CH4 : R/W; bitpos: [22:8]; default: 32767; * When no edge is detected on the input signal and continuous clock cycles is longer * than this register value, received process is finished. */ -#define RMT_IDLE_THRES_4 0x00007FFFU -#define RMT_IDLE_THRES_4_M (RMT_IDLE_THRES_4_V << RMT_IDLE_THRES_4_S) -#define RMT_IDLE_THRES_4_V 0x00007FFFU -#define RMT_IDLE_THRES_4_S 8 -/** RMT_MEM_SIZE_4 : R/W; bitpos: [27:24]; default: 1; +#define RMT_IDLE_THRES_CH4 0x00007FFFU +#define RMT_IDLE_THRES_CH4_M (RMT_IDLE_THRES_CH4_V << RMT_IDLE_THRES_CH4_S) +#define RMT_IDLE_THRES_CH4_V 0x00007FFFU +#define RMT_IDLE_THRES_CH4_S 8 +/** RMT_MEM_SIZE_CH4 : R/W; bitpos: [27:24]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL4. */ -#define RMT_MEM_SIZE_4 0x0000000FU -#define RMT_MEM_SIZE_4_M (RMT_MEM_SIZE_4_V << RMT_MEM_SIZE_4_S) -#define RMT_MEM_SIZE_4_V 0x0000000FU -#define RMT_MEM_SIZE_4_S 24 -/** RMT_CARRIER_EN_4 : R/W; bitpos: [28]; default: 1; +#define RMT_MEM_SIZE_CH4 0x0000000FU +#define RMT_MEM_SIZE_CH4_M (RMT_MEM_SIZE_CH4_V << RMT_MEM_SIZE_CH4_S) +#define RMT_MEM_SIZE_CH4_V 0x0000000FU +#define RMT_MEM_SIZE_CH4_S 24 +/** RMT_CARRIER_EN_CH4 : R/W; bitpos: [28]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL4. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_4 (BIT(28)) -#define RMT_CARRIER_EN_4_M (RMT_CARRIER_EN_4_V << RMT_CARRIER_EN_4_S) -#define RMT_CARRIER_EN_4_V 0x00000001U -#define RMT_CARRIER_EN_4_S 28 -/** RMT_CARRIER_OUT_LV_4 : R/W; bitpos: [29]; default: 1; +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (RMT_CARRIER_EN_CH4_V << RMT_CARRIER_EN_CH4_S) +#define RMT_CARRIER_EN_CH4_V 0x00000001U +#define RMT_CARRIER_EN_CH4_S 28 +/** RMT_CARRIER_OUT_LV_CH4 : R/W; bitpos: [29]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL4. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_4 (BIT(29)) -#define RMT_CARRIER_OUT_LV_4_M (RMT_CARRIER_OUT_LV_4_V << RMT_CARRIER_OUT_LV_4_S) -#define RMT_CARRIER_OUT_LV_4_V 0x00000001U -#define RMT_CARRIER_OUT_LV_4_S 29 +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (RMT_CARRIER_OUT_LV_CH4_V << RMT_CARRIER_OUT_LV_CH4_S) +#define RMT_CARRIER_OUT_LV_CH4_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH4_S 29 /** RMT_CH4CONF1_REG register * Channel 4 configure register 1 */ #define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x34) -/** RMT_RX_EN_4 : R/W; bitpos: [0]; default: 0; +/** RMT_RX_EN_CH4 : R/W; bitpos: [0]; default: 0; * Set this bit to enable receiver to receive data on CHANNEL4. */ -#define RMT_RX_EN_4 (BIT(0)) -#define RMT_RX_EN_4_M (RMT_RX_EN_4_V << RMT_RX_EN_4_S) -#define RMT_RX_EN_4_V 0x00000001U -#define RMT_RX_EN_4_S 0 -/** RMT_MEM_WR_RST_4 : WT; bitpos: [1]; default: 0; +#define RMT_RX_EN_CH4 (BIT(0)) +#define RMT_RX_EN_CH4_M (RMT_RX_EN_CH4_V << RMT_RX_EN_CH4_S) +#define RMT_RX_EN_CH4_V 0x00000001U +#define RMT_RX_EN_CH4_S 0 +/** RMT_MEM_WR_RST_CH4 : WT; bitpos: [1]; default: 0; * Set this bit to reset write ram address for CHANNEL4 by accessing receiver. */ -#define RMT_MEM_WR_RST_4 (BIT(1)) -#define RMT_MEM_WR_RST_4_M (RMT_MEM_WR_RST_4_V << RMT_MEM_WR_RST_4_S) -#define RMT_MEM_WR_RST_4_V 0x00000001U -#define RMT_MEM_WR_RST_4_S 1 -/** RMT_APB_MEM_RST_4 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_WR_RST_CH4 (BIT(1)) +#define RMT_MEM_WR_RST_CH4_M (RMT_MEM_WR_RST_CH4_V << RMT_MEM_WR_RST_CH4_S) +#define RMT_MEM_WR_RST_CH4_V 0x00000001U +#define RMT_MEM_WR_RST_CH4_S 1 +/** RMT_APB_MEM_RST_CH4 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL4 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_4 (BIT(2)) -#define RMT_APB_MEM_RST_4_M (RMT_APB_MEM_RST_4_V << RMT_APB_MEM_RST_4_S) -#define RMT_APB_MEM_RST_4_V 0x00000001U -#define RMT_APB_MEM_RST_4_S 2 -/** RMT_MEM_OWNER_4 : R/W/SC; bitpos: [3]; default: 1; +#define RMT_APB_MEM_RST_CH4 (BIT(2)) +#define RMT_APB_MEM_RST_CH4_M (RMT_APB_MEM_RST_CH4_V << RMT_APB_MEM_RST_CH4_S) +#define RMT_APB_MEM_RST_CH4_V 0x00000001U +#define RMT_APB_MEM_RST_CH4_S 2 +/** RMT_MEM_OWNER_CH4 : R/W/SC; bitpos: [3]; default: 1; * This register marks the ownership of CHANNEL4's ram block. * * 1'h1: Receiver is using the ram. * * 1'h0: APB bus is using the ram. */ -#define RMT_MEM_OWNER_4 (BIT(3)) -#define RMT_MEM_OWNER_4_M (RMT_MEM_OWNER_4_V << RMT_MEM_OWNER_4_S) -#define RMT_MEM_OWNER_4_V 0x00000001U -#define RMT_MEM_OWNER_4_S 3 -/** RMT_RX_FILTER_EN_4 : R/W; bitpos: [4]; default: 0; +#define RMT_MEM_OWNER_CH4 (BIT(3)) +#define RMT_MEM_OWNER_CH4_M (RMT_MEM_OWNER_CH4_V << RMT_MEM_OWNER_CH4_S) +#define RMT_MEM_OWNER_CH4_V 0x00000001U +#define RMT_MEM_OWNER_CH4_S 3 +/** RMT_RX_FILTER_EN_CH4 : R/W; bitpos: [4]; default: 0; * This is the receive filter's enable bit for CHANNEL4. */ -#define RMT_RX_FILTER_EN_4 (BIT(4)) -#define RMT_RX_FILTER_EN_4_M (RMT_RX_FILTER_EN_4_V << RMT_RX_FILTER_EN_4_S) -#define RMT_RX_FILTER_EN_4_V 0x00000001U -#define RMT_RX_FILTER_EN_4_S 4 -/** RMT_RX_FILTER_THRES_4 : R/W; bitpos: [12:5]; default: 15; +#define RMT_RX_FILTER_EN_CH4 (BIT(4)) +#define RMT_RX_FILTER_EN_CH4_M (RMT_RX_FILTER_EN_CH4_V << RMT_RX_FILTER_EN_CH4_S) +#define RMT_RX_FILTER_EN_CH4_V 0x00000001U +#define RMT_RX_FILTER_EN_CH4_S 4 +/** RMT_RX_FILTER_THRES_CH4 : R/W; bitpos: [12:5]; default: 15; * Ignores the input pulse when its width is smaller than this register value in APB * clock periods (in receive mode). */ -#define RMT_RX_FILTER_THRES_4 0x000000FFU -#define RMT_RX_FILTER_THRES_4_M (RMT_RX_FILTER_THRES_4_V << RMT_RX_FILTER_THRES_4_S) -#define RMT_RX_FILTER_THRES_4_V 0x000000FFU -#define RMT_RX_FILTER_THRES_4_S 5 -/** RMT_MEM_RX_WRAP_EN_4 : R/W; bitpos: [13]; default: 0; +#define RMT_RX_FILTER_THRES_CH4 0x000000FFU +#define RMT_RX_FILTER_THRES_CH4_M (RMT_RX_FILTER_THRES_CH4_V << RMT_RX_FILTER_THRES_CH4_S) +#define RMT_RX_FILTER_THRES_CH4_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH4_S 5 +/** RMT_MEM_RX_WRAP_EN_CH4 : R/W; bitpos: [13]; default: 0; * This is the channel 4 enable bit for wraparound mode: it will resume receiving at * the start when the data to be received is more than its memory size. */ -#define RMT_MEM_RX_WRAP_EN_4 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_4_M (RMT_MEM_RX_WRAP_EN_4_V << RMT_MEM_RX_WRAP_EN_4_S) -#define RMT_MEM_RX_WRAP_EN_4_V 0x00000001U -#define RMT_MEM_RX_WRAP_EN_4_S 13 -/** RMT_AFIFO_RST_4 : WT; bitpos: [14]; default: 0; +#define RMT_MEM_RX_WRAP_EN_CH4 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH4_M (RMT_MEM_RX_WRAP_EN_CH4_V << RMT_MEM_RX_WRAP_EN_CH4_S) +#define RMT_MEM_RX_WRAP_EN_CH4_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH4_S 13 +/** RMT_AFIFO_RST_CH4 : WT; bitpos: [14]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_4 (BIT(14)) -#define RMT_AFIFO_RST_4_M (RMT_AFIFO_RST_4_V << RMT_AFIFO_RST_4_S) -#define RMT_AFIFO_RST_4_V 0x00000001U -#define RMT_AFIFO_RST_4_S 14 -/** RMT_CONF_UPDATE_4 : WT; bitpos: [15]; default: 0; +#define RMT_AFIFO_RST_CH4 (BIT(14)) +#define RMT_AFIFO_RST_CH4_M (RMT_AFIFO_RST_CH4_V << RMT_AFIFO_RST_CH4_S) +#define RMT_AFIFO_RST_CH4_V 0x00000001U +#define RMT_AFIFO_RST_CH4_S 14 +/** RMT_CONF_UPDATE_CH4 : WT; bitpos: [15]; default: 0; * synchronization bit for CHANNEL4 */ -#define RMT_CONF_UPDATE_4 (BIT(15)) -#define RMT_CONF_UPDATE_4_M (RMT_CONF_UPDATE_4_V << RMT_CONF_UPDATE_4_S) -#define RMT_CONF_UPDATE_4_V 0x00000001U -#define RMT_CONF_UPDATE_4_S 15 +#define RMT_CONF_UPDATE_CH4 (BIT(15)) +#define RMT_CONF_UPDATE_CH4_M (RMT_CONF_UPDATE_CH4_V << RMT_CONF_UPDATE_CH4_S) +#define RMT_CONF_UPDATE_CH4_V 0x00000001U +#define RMT_CONF_UPDATE_CH4_S 15 /** RMT_CH5CONF0_REG register * Channel 5 configure register 0 */ #define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x38) -/** RMT_DIV_CNT_5 : R/W; bitpos: [7:0]; default: 2; +/** RMT_DIV_CNT_CH5 : R/W; bitpos: [7:0]; default: 2; * This register is used to configure the divider for clock of CHANNEL5. */ -#define RMT_DIV_CNT_5 0x000000FFU -#define RMT_DIV_CNT_5_M (RMT_DIV_CNT_5_V << RMT_DIV_CNT_5_S) -#define RMT_DIV_CNT_5_V 0x000000FFU -#define RMT_DIV_CNT_5_S 0 -/** RMT_IDLE_THRES_5 : R/W; bitpos: [22:8]; default: 32767; +#define RMT_DIV_CNT_CH5 0x000000FFU +#define RMT_DIV_CNT_CH5_M (RMT_DIV_CNT_CH5_V << RMT_DIV_CNT_CH5_S) +#define RMT_DIV_CNT_CH5_V 0x000000FFU +#define RMT_DIV_CNT_CH5_S 0 +/** RMT_IDLE_THRES_CH5 : R/W; bitpos: [22:8]; default: 32767; * When no edge is detected on the input signal and continuous clock cycles is longer * than this register value, received process is finished. */ -#define RMT_IDLE_THRES_5 0x00007FFFU -#define RMT_IDLE_THRES_5_M (RMT_IDLE_THRES_5_V << RMT_IDLE_THRES_5_S) -#define RMT_IDLE_THRES_5_V 0x00007FFFU -#define RMT_IDLE_THRES_5_S 8 -/** RMT_MEM_SIZE_5 : R/W; bitpos: [27:24]; default: 1; +#define RMT_IDLE_THRES_CH5 0x00007FFFU +#define RMT_IDLE_THRES_CH5_M (RMT_IDLE_THRES_CH5_V << RMT_IDLE_THRES_CH5_S) +#define RMT_IDLE_THRES_CH5_V 0x00007FFFU +#define RMT_IDLE_THRES_CH5_S 8 +/** RMT_MEM_SIZE_CH5 : R/W; bitpos: [27:24]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL5. */ -#define RMT_MEM_SIZE_5 0x0000000FU -#define RMT_MEM_SIZE_5_M (RMT_MEM_SIZE_5_V << RMT_MEM_SIZE_5_S) -#define RMT_MEM_SIZE_5_V 0x0000000FU -#define RMT_MEM_SIZE_5_S 24 -/** RMT_CARRIER_EN_5 : R/W; bitpos: [28]; default: 1; +#define RMT_MEM_SIZE_CH5 0x0000000FU +#define RMT_MEM_SIZE_CH5_M (RMT_MEM_SIZE_CH5_V << RMT_MEM_SIZE_CH5_S) +#define RMT_MEM_SIZE_CH5_V 0x0000000FU +#define RMT_MEM_SIZE_CH5_S 24 +/** RMT_CARRIER_EN_CH5 : R/W; bitpos: [28]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL5. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_5 (BIT(28)) -#define RMT_CARRIER_EN_5_M (RMT_CARRIER_EN_5_V << RMT_CARRIER_EN_5_S) -#define RMT_CARRIER_EN_5_V 0x00000001U -#define RMT_CARRIER_EN_5_S 28 -/** RMT_CARRIER_OUT_LV_5 : R/W; bitpos: [29]; default: 1; +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (RMT_CARRIER_EN_CH5_V << RMT_CARRIER_EN_CH5_S) +#define RMT_CARRIER_EN_CH5_V 0x00000001U +#define RMT_CARRIER_EN_CH5_S 28 +/** RMT_CARRIER_OUT_LV_CH5 : R/W; bitpos: [29]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL5. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_5 (BIT(29)) -#define RMT_CARRIER_OUT_LV_5_M (RMT_CARRIER_OUT_LV_5_V << RMT_CARRIER_OUT_LV_5_S) -#define RMT_CARRIER_OUT_LV_5_V 0x00000001U -#define RMT_CARRIER_OUT_LV_5_S 29 +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (RMT_CARRIER_OUT_LV_CH5_V << RMT_CARRIER_OUT_LV_CH5_S) +#define RMT_CARRIER_OUT_LV_CH5_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH5_S 29 /** RMT_CH5CONF1_REG register * Channel 5 configure register 1 */ #define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x3c) -/** RMT_RX_EN_5 : R/W; bitpos: [0]; default: 0; +/** RMT_RX_EN_CH5 : R/W; bitpos: [0]; default: 0; * Set this bit to enable receiver to receive data on CHANNEL5. */ -#define RMT_RX_EN_5 (BIT(0)) -#define RMT_RX_EN_5_M (RMT_RX_EN_5_V << RMT_RX_EN_5_S) -#define RMT_RX_EN_5_V 0x00000001U -#define RMT_RX_EN_5_S 0 -/** RMT_MEM_WR_RST_5 : WT; bitpos: [1]; default: 0; +#define RMT_RX_EN_CH5 (BIT(0)) +#define RMT_RX_EN_CH5_M (RMT_RX_EN_CH5_V << RMT_RX_EN_CH5_S) +#define RMT_RX_EN_CH5_V 0x00000001U +#define RMT_RX_EN_CH5_S 0 +/** RMT_MEM_WR_RST_CH5 : WT; bitpos: [1]; default: 0; * Set this bit to reset write ram address for CHANNEL5 by accessing receiver. */ -#define RMT_MEM_WR_RST_5 (BIT(1)) -#define RMT_MEM_WR_RST_5_M (RMT_MEM_WR_RST_5_V << RMT_MEM_WR_RST_5_S) -#define RMT_MEM_WR_RST_5_V 0x00000001U -#define RMT_MEM_WR_RST_5_S 1 -/** RMT_APB_MEM_RST_5 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_WR_RST_CH5 (BIT(1)) +#define RMT_MEM_WR_RST_CH5_M (RMT_MEM_WR_RST_CH5_V << RMT_MEM_WR_RST_CH5_S) +#define RMT_MEM_WR_RST_CH5_V 0x00000001U +#define RMT_MEM_WR_RST_CH5_S 1 +/** RMT_APB_MEM_RST_CH5 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL5 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_5 (BIT(2)) -#define RMT_APB_MEM_RST_5_M (RMT_APB_MEM_RST_5_V << RMT_APB_MEM_RST_5_S) -#define RMT_APB_MEM_RST_5_V 0x00000001U -#define RMT_APB_MEM_RST_5_S 2 -/** RMT_MEM_OWNER_5 : R/W/SC; bitpos: [3]; default: 1; +#define RMT_APB_MEM_RST_CH5 (BIT(2)) +#define RMT_APB_MEM_RST_CH5_M (RMT_APB_MEM_RST_CH5_V << RMT_APB_MEM_RST_CH5_S) +#define RMT_APB_MEM_RST_CH5_V 0x00000001U +#define RMT_APB_MEM_RST_CH5_S 2 +/** RMT_MEM_OWNER_CH5 : R/W/SC; bitpos: [3]; default: 1; * This register marks the ownership of CHANNEL5's ram block. * * 1'h1: Receiver is using the ram. * * 1'h0: APB bus is using the ram. */ -#define RMT_MEM_OWNER_5 (BIT(3)) -#define RMT_MEM_OWNER_5_M (RMT_MEM_OWNER_5_V << RMT_MEM_OWNER_5_S) -#define RMT_MEM_OWNER_5_V 0x00000001U -#define RMT_MEM_OWNER_5_S 3 -/** RMT_RX_FILTER_EN_5 : R/W; bitpos: [4]; default: 0; +#define RMT_MEM_OWNER_CH5 (BIT(3)) +#define RMT_MEM_OWNER_CH5_M (RMT_MEM_OWNER_CH5_V << RMT_MEM_OWNER_CH5_S) +#define RMT_MEM_OWNER_CH5_V 0x00000001U +#define RMT_MEM_OWNER_CH5_S 3 +/** RMT_RX_FILTER_EN_CH5 : R/W; bitpos: [4]; default: 0; * This is the receive filter's enable bit for CHANNEL5. */ -#define RMT_RX_FILTER_EN_5 (BIT(4)) -#define RMT_RX_FILTER_EN_5_M (RMT_RX_FILTER_EN_5_V << RMT_RX_FILTER_EN_5_S) -#define RMT_RX_FILTER_EN_5_V 0x00000001U -#define RMT_RX_FILTER_EN_5_S 4 -/** RMT_RX_FILTER_THRES_5 : R/W; bitpos: [12:5]; default: 15; +#define RMT_RX_FILTER_EN_CH5 (BIT(4)) +#define RMT_RX_FILTER_EN_CH5_M (RMT_RX_FILTER_EN_CH5_V << RMT_RX_FILTER_EN_CH5_S) +#define RMT_RX_FILTER_EN_CH5_V 0x00000001U +#define RMT_RX_FILTER_EN_CH5_S 4 +/** RMT_RX_FILTER_THRES_CH5 : R/W; bitpos: [12:5]; default: 15; * Ignores the input pulse when its width is smaller than this register value in APB * clock periods (in receive mode). */ -#define RMT_RX_FILTER_THRES_5 0x000000FFU -#define RMT_RX_FILTER_THRES_5_M (RMT_RX_FILTER_THRES_5_V << RMT_RX_FILTER_THRES_5_S) -#define RMT_RX_FILTER_THRES_5_V 0x000000FFU -#define RMT_RX_FILTER_THRES_5_S 5 -/** RMT_MEM_RX_WRAP_EN_5 : R/W; bitpos: [13]; default: 0; +#define RMT_RX_FILTER_THRES_CH5 0x000000FFU +#define RMT_RX_FILTER_THRES_CH5_M (RMT_RX_FILTER_THRES_CH5_V << RMT_RX_FILTER_THRES_CH5_S) +#define RMT_RX_FILTER_THRES_CH5_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH5_S 5 +/** RMT_MEM_RX_WRAP_EN_CH5 : R/W; bitpos: [13]; default: 0; * This is the channel 5 enable bit for wraparound mode: it will resume receiving at * the start when the data to be received is more than its memory size. */ -#define RMT_MEM_RX_WRAP_EN_5 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_5_M (RMT_MEM_RX_WRAP_EN_5_V << RMT_MEM_RX_WRAP_EN_5_S) -#define RMT_MEM_RX_WRAP_EN_5_V 0x00000001U -#define RMT_MEM_RX_WRAP_EN_5_S 13 -/** RMT_AFIFO_RST_5 : WT; bitpos: [14]; default: 0; +#define RMT_MEM_RX_WRAP_EN_CH5 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH5_M (RMT_MEM_RX_WRAP_EN_CH5_V << RMT_MEM_RX_WRAP_EN_CH5_S) +#define RMT_MEM_RX_WRAP_EN_CH5_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH5_S 13 +/** RMT_AFIFO_RST_CH5 : WT; bitpos: [14]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_5 (BIT(14)) -#define RMT_AFIFO_RST_5_M (RMT_AFIFO_RST_5_V << RMT_AFIFO_RST_5_S) -#define RMT_AFIFO_RST_5_V 0x00000001U -#define RMT_AFIFO_RST_5_S 14 -/** RMT_CONF_UPDATE_5 : WT; bitpos: [15]; default: 0; +#define RMT_AFIFO_RST_CH5 (BIT(14)) +#define RMT_AFIFO_RST_CH5_M (RMT_AFIFO_RST_CH5_V << RMT_AFIFO_RST_CH5_S) +#define RMT_AFIFO_RST_CH5_V 0x00000001U +#define RMT_AFIFO_RST_CH5_S 14 +/** RMT_CONF_UPDATE_CH5 : WT; bitpos: [15]; default: 0; * synchronization bit for CHANNEL5 */ -#define RMT_CONF_UPDATE_5 (BIT(15)) -#define RMT_CONF_UPDATE_5_M (RMT_CONF_UPDATE_5_V << RMT_CONF_UPDATE_5_S) -#define RMT_CONF_UPDATE_5_V 0x00000001U -#define RMT_CONF_UPDATE_5_S 15 +#define RMT_CONF_UPDATE_CH5 (BIT(15)) +#define RMT_CONF_UPDATE_CH5_M (RMT_CONF_UPDATE_CH5_V << RMT_CONF_UPDATE_CH5_S) +#define RMT_CONF_UPDATE_CH5_V 0x00000001U +#define RMT_CONF_UPDATE_CH5_S 15 /** RMT_CH6CONF0_REG register * Channel 6 configure register 0 */ #define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x40) -/** RMT_DIV_CNT_6 : R/W; bitpos: [7:0]; default: 2; +/** RMT_DIV_CNT_CH6 : R/W; bitpos: [7:0]; default: 2; * This register is used to configure the divider for clock of CHANNEL6. */ -#define RMT_DIV_CNT_6 0x000000FFU -#define RMT_DIV_CNT_6_M (RMT_DIV_CNT_6_V << RMT_DIV_CNT_6_S) -#define RMT_DIV_CNT_6_V 0x000000FFU -#define RMT_DIV_CNT_6_S 0 -/** RMT_IDLE_THRES_6 : R/W; bitpos: [22:8]; default: 32767; +#define RMT_DIV_CNT_CH6 0x000000FFU +#define RMT_DIV_CNT_CH6_M (RMT_DIV_CNT_CH6_V << RMT_DIV_CNT_CH6_S) +#define RMT_DIV_CNT_CH6_V 0x000000FFU +#define RMT_DIV_CNT_CH6_S 0 +/** RMT_IDLE_THRES_CH6 : R/W; bitpos: [22:8]; default: 32767; * When no edge is detected on the input signal and continuous clock cycles is longer * than this register value, received process is finished. */ -#define RMT_IDLE_THRES_6 0x00007FFFU -#define RMT_IDLE_THRES_6_M (RMT_IDLE_THRES_6_V << RMT_IDLE_THRES_6_S) -#define RMT_IDLE_THRES_6_V 0x00007FFFU -#define RMT_IDLE_THRES_6_S 8 -/** RMT_MEM_SIZE_6 : R/W; bitpos: [27:24]; default: 1; +#define RMT_IDLE_THRES_CH6 0x00007FFFU +#define RMT_IDLE_THRES_CH6_M (RMT_IDLE_THRES_CH6_V << RMT_IDLE_THRES_CH6_S) +#define RMT_IDLE_THRES_CH6_V 0x00007FFFU +#define RMT_IDLE_THRES_CH6_S 8 +/** RMT_MEM_SIZE_CH6 : R/W; bitpos: [27:24]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL6. */ -#define RMT_MEM_SIZE_6 0x0000000FU -#define RMT_MEM_SIZE_6_M (RMT_MEM_SIZE_6_V << RMT_MEM_SIZE_6_S) -#define RMT_MEM_SIZE_6_V 0x0000000FU -#define RMT_MEM_SIZE_6_S 24 -/** RMT_CARRIER_EN_6 : R/W; bitpos: [28]; default: 1; +#define RMT_MEM_SIZE_CH6 0x0000000FU +#define RMT_MEM_SIZE_CH6_M (RMT_MEM_SIZE_CH6_V << RMT_MEM_SIZE_CH6_S) +#define RMT_MEM_SIZE_CH6_V 0x0000000FU +#define RMT_MEM_SIZE_CH6_S 24 +/** RMT_CARRIER_EN_CH6 : R/W; bitpos: [28]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL6. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_6 (BIT(28)) -#define RMT_CARRIER_EN_6_M (RMT_CARRIER_EN_6_V << RMT_CARRIER_EN_6_S) -#define RMT_CARRIER_EN_6_V 0x00000001U -#define RMT_CARRIER_EN_6_S 28 -/** RMT_CARRIER_OUT_LV_6 : R/W; bitpos: [29]; default: 1; +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (RMT_CARRIER_EN_CH6_V << RMT_CARRIER_EN_CH6_S) +#define RMT_CARRIER_EN_CH6_V 0x00000001U +#define RMT_CARRIER_EN_CH6_S 28 +/** RMT_CARRIER_OUT_LV_CH6 : R/W; bitpos: [29]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL6. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_6 (BIT(29)) -#define RMT_CARRIER_OUT_LV_6_M (RMT_CARRIER_OUT_LV_6_V << RMT_CARRIER_OUT_LV_6_S) -#define RMT_CARRIER_OUT_LV_6_V 0x00000001U -#define RMT_CARRIER_OUT_LV_6_S 29 +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (RMT_CARRIER_OUT_LV_CH6_V << RMT_CARRIER_OUT_LV_CH6_S) +#define RMT_CARRIER_OUT_LV_CH6_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH6_S 29 /** RMT_CH6CONF1_REG register * Channel 6 configure register 1 */ #define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x44) -/** RMT_RX_EN_6 : R/W; bitpos: [0]; default: 0; +/** RMT_RX_EN_CH6 : R/W; bitpos: [0]; default: 0; * Set this bit to enable receiver to receive data on CHANNEL6. */ -#define RMT_RX_EN_6 (BIT(0)) -#define RMT_RX_EN_6_M (RMT_RX_EN_6_V << RMT_RX_EN_6_S) -#define RMT_RX_EN_6_V 0x00000001U -#define RMT_RX_EN_6_S 0 -/** RMT_MEM_WR_RST_6 : WT; bitpos: [1]; default: 0; +#define RMT_RX_EN_CH6 (BIT(0)) +#define RMT_RX_EN_CH6_M (RMT_RX_EN_CH6_V << RMT_RX_EN_CH6_S) +#define RMT_RX_EN_CH6_V 0x00000001U +#define RMT_RX_EN_CH6_S 0 +/** RMT_MEM_WR_RST_CH6 : WT; bitpos: [1]; default: 0; * Set this bit to reset write ram address for CHANNEL6 by accessing receiver. */ -#define RMT_MEM_WR_RST_6 (BIT(1)) -#define RMT_MEM_WR_RST_6_M (RMT_MEM_WR_RST_6_V << RMT_MEM_WR_RST_6_S) -#define RMT_MEM_WR_RST_6_V 0x00000001U -#define RMT_MEM_WR_RST_6_S 1 -/** RMT_APB_MEM_RST_6 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_WR_RST_CH6 (BIT(1)) +#define RMT_MEM_WR_RST_CH6_M (RMT_MEM_WR_RST_CH6_V << RMT_MEM_WR_RST_CH6_S) +#define RMT_MEM_WR_RST_CH6_V 0x00000001U +#define RMT_MEM_WR_RST_CH6_S 1 +/** RMT_APB_MEM_RST_CH6 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL6 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_6 (BIT(2)) -#define RMT_APB_MEM_RST_6_M (RMT_APB_MEM_RST_6_V << RMT_APB_MEM_RST_6_S) -#define RMT_APB_MEM_RST_6_V 0x00000001U -#define RMT_APB_MEM_RST_6_S 2 -/** RMT_MEM_OWNER_6 : R/W/SC; bitpos: [3]; default: 1; +#define RMT_APB_MEM_RST_CH6 (BIT(2)) +#define RMT_APB_MEM_RST_CH6_M (RMT_APB_MEM_RST_CH6_V << RMT_APB_MEM_RST_CH6_S) +#define RMT_APB_MEM_RST_CH6_V 0x00000001U +#define RMT_APB_MEM_RST_CH6_S 2 +/** RMT_MEM_OWNER_CH6 : R/W/SC; bitpos: [3]; default: 1; * This register marks the ownership of CHANNEL6's ram block. * * 1'h1: Receiver is using the ram. * * 1'h0: APB bus is using the ram. */ -#define RMT_MEM_OWNER_6 (BIT(3)) -#define RMT_MEM_OWNER_6_M (RMT_MEM_OWNER_6_V << RMT_MEM_OWNER_6_S) -#define RMT_MEM_OWNER_6_V 0x00000001U -#define RMT_MEM_OWNER_6_S 3 -/** RMT_RX_FILTER_EN_6 : R/W; bitpos: [4]; default: 0; +#define RMT_MEM_OWNER_CH6 (BIT(3)) +#define RMT_MEM_OWNER_CH6_M (RMT_MEM_OWNER_CH6_V << RMT_MEM_OWNER_CH6_S) +#define RMT_MEM_OWNER_CH6_V 0x00000001U +#define RMT_MEM_OWNER_CH6_S 3 +/** RMT_RX_FILTER_EN_CH6 : R/W; bitpos: [4]; default: 0; * This is the receive filter's enable bit for CHANNEL6. */ -#define RMT_RX_FILTER_EN_6 (BIT(4)) -#define RMT_RX_FILTER_EN_6_M (RMT_RX_FILTER_EN_6_V << RMT_RX_FILTER_EN_6_S) -#define RMT_RX_FILTER_EN_6_V 0x00000001U -#define RMT_RX_FILTER_EN_6_S 4 -/** RMT_RX_FILTER_THRES_6 : R/W; bitpos: [12:5]; default: 15; +#define RMT_RX_FILTER_EN_CH6 (BIT(4)) +#define RMT_RX_FILTER_EN_CH6_M (RMT_RX_FILTER_EN_CH6_V << RMT_RX_FILTER_EN_CH6_S) +#define RMT_RX_FILTER_EN_CH6_V 0x00000001U +#define RMT_RX_FILTER_EN_CH6_S 4 +/** RMT_RX_FILTER_THRES_CH6 : R/W; bitpos: [12:5]; default: 15; * Ignores the input pulse when its width is smaller than this register value in APB * clock periods (in receive mode). */ -#define RMT_RX_FILTER_THRES_6 0x000000FFU -#define RMT_RX_FILTER_THRES_6_M (RMT_RX_FILTER_THRES_6_V << RMT_RX_FILTER_THRES_6_S) -#define RMT_RX_FILTER_THRES_6_V 0x000000FFU -#define RMT_RX_FILTER_THRES_6_S 5 -/** RMT_MEM_RX_WRAP_EN_6 : R/W; bitpos: [13]; default: 0; +#define RMT_RX_FILTER_THRES_CH6 0x000000FFU +#define RMT_RX_FILTER_THRES_CH6_M (RMT_RX_FILTER_THRES_CH6_V << RMT_RX_FILTER_THRES_CH6_S) +#define RMT_RX_FILTER_THRES_CH6_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH6_S 5 +/** RMT_MEM_RX_WRAP_EN_CH6 : R/W; bitpos: [13]; default: 0; * This is the channel 6 enable bit for wraparound mode: it will resume receiving at * the start when the data to be received is more than its memory size. */ -#define RMT_MEM_RX_WRAP_EN_6 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_6_M (RMT_MEM_RX_WRAP_EN_6_V << RMT_MEM_RX_WRAP_EN_6_S) -#define RMT_MEM_RX_WRAP_EN_6_V 0x00000001U -#define RMT_MEM_RX_WRAP_EN_6_S 13 -/** RMT_AFIFO_RST_6 : WT; bitpos: [14]; default: 0; +#define RMT_MEM_RX_WRAP_EN_CH6 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH6_M (RMT_MEM_RX_WRAP_EN_CH6_V << RMT_MEM_RX_WRAP_EN_CH6_S) +#define RMT_MEM_RX_WRAP_EN_CH6_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH6_S 13 +/** RMT_AFIFO_RST_CH6 : WT; bitpos: [14]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_6 (BIT(14)) -#define RMT_AFIFO_RST_6_M (RMT_AFIFO_RST_6_V << RMT_AFIFO_RST_6_S) -#define RMT_AFIFO_RST_6_V 0x00000001U -#define RMT_AFIFO_RST_6_S 14 -/** RMT_CONF_UPDATE_6 : WT; bitpos: [15]; default: 0; +#define RMT_AFIFO_RST_CH6 (BIT(14)) +#define RMT_AFIFO_RST_CH6_M (RMT_AFIFO_RST_CH6_V << RMT_AFIFO_RST_CH6_S) +#define RMT_AFIFO_RST_CH6_V 0x00000001U +#define RMT_AFIFO_RST_CH6_S 14 +/** RMT_CONF_UPDATE_CH6 : WT; bitpos: [15]; default: 0; * synchronization bit for CHANNEL6 */ -#define RMT_CONF_UPDATE_6 (BIT(15)) -#define RMT_CONF_UPDATE_6_M (RMT_CONF_UPDATE_6_V << RMT_CONF_UPDATE_6_S) -#define RMT_CONF_UPDATE_6_V 0x00000001U -#define RMT_CONF_UPDATE_6_S 15 +#define RMT_CONF_UPDATE_CH6 (BIT(15)) +#define RMT_CONF_UPDATE_CH6_M (RMT_CONF_UPDATE_CH6_V << RMT_CONF_UPDATE_CH6_S) +#define RMT_CONF_UPDATE_CH6_V 0x00000001U +#define RMT_CONF_UPDATE_CH6_S 15 /** RMT_CH7CONF0_REG register * Channel 7 configure register 0 */ #define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x48) -/** RMT_DIV_CNT_7 : R/W; bitpos: [7:0]; default: 2; +/** RMT_DIV_CNT_CH7 : R/W; bitpos: [7:0]; default: 2; * This register is used to configure the divider for clock of CHANNEL7. */ -#define RMT_DIV_CNT_7 0x000000FFU -#define RMT_DIV_CNT_7_M (RMT_DIV_CNT_7_V << RMT_DIV_CNT_7_S) -#define RMT_DIV_CNT_7_V 0x000000FFU -#define RMT_DIV_CNT_7_S 0 -/** RMT_IDLE_THRES_7 : R/W; bitpos: [22:8]; default: 32767; +#define RMT_DIV_CNT_CH7 0x000000FFU +#define RMT_DIV_CNT_CH7_M (RMT_DIV_CNT_CH7_V << RMT_DIV_CNT_CH7_S) +#define RMT_DIV_CNT_CH7_V 0x000000FFU +#define RMT_DIV_CNT_CH7_S 0 +/** RMT_IDLE_THRES_CH7 : R/W; bitpos: [22:8]; default: 32767; * When no edge is detected on the input signal and continuous clock cycles is longer * than this register value, received process is finished. */ -#define RMT_IDLE_THRES_7 0x00007FFFU -#define RMT_IDLE_THRES_7_M (RMT_IDLE_THRES_7_V << RMT_IDLE_THRES_7_S) -#define RMT_IDLE_THRES_7_V 0x00007FFFU -#define RMT_IDLE_THRES_7_S 8 -/** RMT_MEM_SIZE_7 : R/W; bitpos: [27:24]; default: 1; +#define RMT_IDLE_THRES_CH7 0x00007FFFU +#define RMT_IDLE_THRES_CH7_M (RMT_IDLE_THRES_CH7_V << RMT_IDLE_THRES_CH7_S) +#define RMT_IDLE_THRES_CH7_V 0x00007FFFU +#define RMT_IDLE_THRES_CH7_S 8 +/** RMT_MEM_SIZE_CH7 : R/W; bitpos: [27:24]; default: 1; * This register is used to configure the maximum size of memory allocated to CHANNEL7. */ -#define RMT_MEM_SIZE_7 0x0000000FU -#define RMT_MEM_SIZE_7_M (RMT_MEM_SIZE_7_V << RMT_MEM_SIZE_7_S) -#define RMT_MEM_SIZE_7_V 0x0000000FU -#define RMT_MEM_SIZE_7_S 24 -/** RMT_CARRIER_EN_7 : R/W; bitpos: [28]; default: 1; +#define RMT_MEM_SIZE_CH7 0x0000000FU +#define RMT_MEM_SIZE_CH7_M (RMT_MEM_SIZE_CH7_V << RMT_MEM_SIZE_CH7_S) +#define RMT_MEM_SIZE_CH7_V 0x0000000FU +#define RMT_MEM_SIZE_CH7_S 24 +/** RMT_CARRIER_EN_CH7 : R/W; bitpos: [28]; default: 1; * This is the carrier modulation enable-control bit for CHANNEL7. 1: Add carrier * modulation in the output signal. 0: No carrier modulation in sig_out. */ -#define RMT_CARRIER_EN_7 (BIT(28)) -#define RMT_CARRIER_EN_7_M (RMT_CARRIER_EN_7_V << RMT_CARRIER_EN_7_S) -#define RMT_CARRIER_EN_7_V 0x00000001U -#define RMT_CARRIER_EN_7_S 28 -/** RMT_CARRIER_OUT_LV_7 : R/W; bitpos: [29]; default: 1; +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (RMT_CARRIER_EN_CH7_V << RMT_CARRIER_EN_CH7_S) +#define RMT_CARRIER_EN_CH7_V 0x00000001U +#define RMT_CARRIER_EN_CH7_S 28 +/** RMT_CARRIER_OUT_LV_CH7 : R/W; bitpos: [29]; default: 1; * This bit is used to configure the position of carrier wave for CHANNEL7. * * 1'h0: add carrier wave on low level. * * 1'h1: add carrier wave on high level. */ -#define RMT_CARRIER_OUT_LV_7 (BIT(29)) -#define RMT_CARRIER_OUT_LV_7_M (RMT_CARRIER_OUT_LV_7_V << RMT_CARRIER_OUT_LV_7_S) -#define RMT_CARRIER_OUT_LV_7_V 0x00000001U -#define RMT_CARRIER_OUT_LV_7_S 29 +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (RMT_CARRIER_OUT_LV_CH7_V << RMT_CARRIER_OUT_LV_CH7_S) +#define RMT_CARRIER_OUT_LV_CH7_V 0x00000001U +#define RMT_CARRIER_OUT_LV_CH7_S 29 /** RMT_CH7CONF1_REG register * Channel 7 configure register 1 */ #define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x4c) -/** RMT_RX_EN_7 : R/W; bitpos: [0]; default: 0; +/** RMT_RX_EN_CH7 : R/W; bitpos: [0]; default: 0; * Set this bit to enable receiver to receive data on CHANNEL7. */ -#define RMT_RX_EN_7 (BIT(0)) -#define RMT_RX_EN_7_M (RMT_RX_EN_7_V << RMT_RX_EN_7_S) -#define RMT_RX_EN_7_V 0x00000001U -#define RMT_RX_EN_7_S 0 -/** RMT_MEM_WR_RST_7 : WT; bitpos: [1]; default: 0; +#define RMT_RX_EN_CH7 (BIT(0)) +#define RMT_RX_EN_CH7_M (RMT_RX_EN_CH7_V << RMT_RX_EN_CH7_S) +#define RMT_RX_EN_CH7_V 0x00000001U +#define RMT_RX_EN_CH7_S 0 +/** RMT_MEM_WR_RST_CH7 : WT; bitpos: [1]; default: 0; * Set this bit to reset write ram address for CHANNEL7 by accessing receiver. */ -#define RMT_MEM_WR_RST_7 (BIT(1)) -#define RMT_MEM_WR_RST_7_M (RMT_MEM_WR_RST_7_V << RMT_MEM_WR_RST_7_S) -#define RMT_MEM_WR_RST_7_V 0x00000001U -#define RMT_MEM_WR_RST_7_S 1 -/** RMT_APB_MEM_RST_7 : WT; bitpos: [2]; default: 0; +#define RMT_MEM_WR_RST_CH7 (BIT(1)) +#define RMT_MEM_WR_RST_CH7_M (RMT_MEM_WR_RST_CH7_V << RMT_MEM_WR_RST_CH7_S) +#define RMT_MEM_WR_RST_CH7_V 0x00000001U +#define RMT_MEM_WR_RST_CH7_S 1 +/** RMT_APB_MEM_RST_CH7 : WT; bitpos: [2]; default: 0; * Set this bit to reset W/R ram address for CHANNEL7 by accessing apb fifo. */ -#define RMT_APB_MEM_RST_7 (BIT(2)) -#define RMT_APB_MEM_RST_7_M (RMT_APB_MEM_RST_7_V << RMT_APB_MEM_RST_7_S) -#define RMT_APB_MEM_RST_7_V 0x00000001U -#define RMT_APB_MEM_RST_7_S 2 -/** RMT_MEM_OWNER_7 : R/W/SC; bitpos: [3]; default: 1; +#define RMT_APB_MEM_RST_CH7 (BIT(2)) +#define RMT_APB_MEM_RST_CH7_M (RMT_APB_MEM_RST_CH7_V << RMT_APB_MEM_RST_CH7_S) +#define RMT_APB_MEM_RST_CH7_V 0x00000001U +#define RMT_APB_MEM_RST_CH7_S 2 +/** RMT_MEM_OWNER_CH7 : R/W/SC; bitpos: [3]; default: 1; * This register marks the ownership of CHANNEL7's ram block. * * 1'h1: Receiver is using the ram. * * 1'h0: APB bus is using the ram. */ -#define RMT_MEM_OWNER_7 (BIT(3)) -#define RMT_MEM_OWNER_7_M (RMT_MEM_OWNER_7_V << RMT_MEM_OWNER_7_S) -#define RMT_MEM_OWNER_7_V 0x00000001U -#define RMT_MEM_OWNER_7_S 3 -/** RMT_RX_FILTER_EN_7 : R/W; bitpos: [4]; default: 0; +#define RMT_MEM_OWNER_CH7 (BIT(3)) +#define RMT_MEM_OWNER_CH7_M (RMT_MEM_OWNER_CH7_V << RMT_MEM_OWNER_CH7_S) +#define RMT_MEM_OWNER_CH7_V 0x00000001U +#define RMT_MEM_OWNER_CH7_S 3 +/** RMT_RX_FILTER_EN_CH7 : R/W; bitpos: [4]; default: 0; * This is the receive filter's enable bit for CHANNEL7. */ -#define RMT_RX_FILTER_EN_7 (BIT(4)) -#define RMT_RX_FILTER_EN_7_M (RMT_RX_FILTER_EN_7_V << RMT_RX_FILTER_EN_7_S) -#define RMT_RX_FILTER_EN_7_V 0x00000001U -#define RMT_RX_FILTER_EN_7_S 4 -/** RMT_RX_FILTER_THRES_7 : R/W; bitpos: [12:5]; default: 15; +#define RMT_RX_FILTER_EN_CH7 (BIT(4)) +#define RMT_RX_FILTER_EN_CH7_M (RMT_RX_FILTER_EN_CH7_V << RMT_RX_FILTER_EN_CH7_S) +#define RMT_RX_FILTER_EN_CH7_V 0x00000001U +#define RMT_RX_FILTER_EN_CH7_S 4 +/** RMT_RX_FILTER_THRES_CH7 : R/W; bitpos: [12:5]; default: 15; * Ignores the input pulse when its width is smaller than this register value in APB * clock periods (in receive mode). */ -#define RMT_RX_FILTER_THRES_7 0x000000FFU -#define RMT_RX_FILTER_THRES_7_M (RMT_RX_FILTER_THRES_7_V << RMT_RX_FILTER_THRES_7_S) -#define RMT_RX_FILTER_THRES_7_V 0x000000FFU -#define RMT_RX_FILTER_THRES_7_S 5 -/** RMT_MEM_RX_WRAP_EN_7 : R/W; bitpos: [13]; default: 0; +#define RMT_RX_FILTER_THRES_CH7 0x000000FFU +#define RMT_RX_FILTER_THRES_CH7_M (RMT_RX_FILTER_THRES_CH7_V << RMT_RX_FILTER_THRES_CH7_S) +#define RMT_RX_FILTER_THRES_CH7_V 0x000000FFU +#define RMT_RX_FILTER_THRES_CH7_S 5 +/** RMT_MEM_RX_WRAP_EN_CH7 : R/W; bitpos: [13]; default: 0; * This is the channel 7 enable bit for wraparound mode: it will resume receiving at * the start when the data to be received is more than its memory size. */ -#define RMT_MEM_RX_WRAP_EN_7 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_7_M (RMT_MEM_RX_WRAP_EN_7_V << RMT_MEM_RX_WRAP_EN_7_S) -#define RMT_MEM_RX_WRAP_EN_7_V 0x00000001U -#define RMT_MEM_RX_WRAP_EN_7_S 13 -/** RMT_AFIFO_RST_7 : WT; bitpos: [14]; default: 0; +#define RMT_MEM_RX_WRAP_EN_CH7 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH7_M (RMT_MEM_RX_WRAP_EN_CH7_V << RMT_MEM_RX_WRAP_EN_CH7_S) +#define RMT_MEM_RX_WRAP_EN_CH7_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_CH7_S 13 +/** RMT_AFIFO_RST_CH7 : WT; bitpos: [14]; default: 0; * Reserved */ -#define RMT_AFIFO_RST_7 (BIT(14)) -#define RMT_AFIFO_RST_7_M (RMT_AFIFO_RST_7_V << RMT_AFIFO_RST_7_S) -#define RMT_AFIFO_RST_7_V 0x00000001U -#define RMT_AFIFO_RST_7_S 14 -/** RMT_CONF_UPDATE_7 : WT; bitpos: [15]; default: 0; +#define RMT_AFIFO_RST_CH7 (BIT(14)) +#define RMT_AFIFO_RST_CH7_M (RMT_AFIFO_RST_CH7_V << RMT_AFIFO_RST_CH7_S) +#define RMT_AFIFO_RST_CH7_V 0x00000001U +#define RMT_AFIFO_RST_CH7_S 14 +/** RMT_CONF_UPDATE_CH7 : WT; bitpos: [15]; default: 0; * synchronization bit for CHANNEL7 */ -#define RMT_CONF_UPDATE_7 (BIT(15)) -#define RMT_CONF_UPDATE_7_M (RMT_CONF_UPDATE_7_V << RMT_CONF_UPDATE_7_S) -#define RMT_CONF_UPDATE_7_V 0x00000001U -#define RMT_CONF_UPDATE_7_S 15 +#define RMT_CONF_UPDATE_CH7 (BIT(15)) +#define RMT_CONF_UPDATE_CH7_M (RMT_CONF_UPDATE_CH7_V << RMT_CONF_UPDATE_CH7_S) +#define RMT_CONF_UPDATE_CH7_V 0x00000001U +#define RMT_CONF_UPDATE_CH7_S 15 /** RMT_CH0STATUS_REG register * Channel 0 status register */ #define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x50) -/** RMT_MEM_RADDR_EX_0 : RO; bitpos: [9:0]; default: 0; +/** RMT_MEM_RADDR_EX_CH0 : RO; bitpos: [9:0]; default: 0; * This register records the memory address offset when transmitter of CHANNEL0 is * using the RAM. */ -#define RMT_MEM_RADDR_EX_0 0x000003FFU -#define RMT_MEM_RADDR_EX_0_M (RMT_MEM_RADDR_EX_0_V << RMT_MEM_RADDR_EX_0_S) -#define RMT_MEM_RADDR_EX_0_V 0x000003FFU -#define RMT_MEM_RADDR_EX_0_S 0 -/** RMT_APB_MEM_WADDR_0 : RO; bitpos: [20:11]; default: 0; +#define RMT_MEM_RADDR_EX_CH0 0x000003FFU +#define RMT_MEM_RADDR_EX_CH0_M (RMT_MEM_RADDR_EX_CH0_V << RMT_MEM_RADDR_EX_CH0_S) +#define RMT_MEM_RADDR_EX_CH0_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_APB_MEM_WADDR_CH0 : RO; bitpos: [20:11]; default: 0; * This register records the memory address offset when writes RAM over APB bus. */ -#define RMT_APB_MEM_WADDR_0 0x000003FFU -#define RMT_APB_MEM_WADDR_0_M (RMT_APB_MEM_WADDR_0_V << RMT_APB_MEM_WADDR_0_S) -#define RMT_APB_MEM_WADDR_0_V 0x000003FFU -#define RMT_APB_MEM_WADDR_0_S 11 -/** RMT_STATE_0 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_WADDR_CH0 0x000003FFU +#define RMT_APB_MEM_WADDR_CH0_M (RMT_APB_MEM_WADDR_CH0_V << RMT_APB_MEM_WADDR_CH0_S) +#define RMT_APB_MEM_WADDR_CH0_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH0_S 11 +/** RMT_STATE_CH0 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL0. */ -#define RMT_STATE_0 0x00000007U -#define RMT_STATE_0_M (RMT_STATE_0_V << RMT_STATE_0_S) -#define RMT_STATE_0_V 0x00000007U -#define RMT_STATE_0_S 22 -/** RMT_MEM_EMPTY_0 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH0 0x00000007U +#define RMT_STATE_CH0_M (RMT_STATE_CH0_V << RMT_STATE_CH0_S) +#define RMT_STATE_CH0_V 0x00000007U +#define RMT_STATE_CH0_S 22 +/** RMT_MEM_EMPTY_CH0 : RO; bitpos: [25]; default: 0; * This status bit will be set when the data to be set is more than memory size and * the wraparound mode is disabled. */ -#define RMT_MEM_EMPTY_0 (BIT(25)) -#define RMT_MEM_EMPTY_0_M (RMT_MEM_EMPTY_0_V << RMT_MEM_EMPTY_0_S) -#define RMT_MEM_EMPTY_0_V 0x00000001U -#define RMT_MEM_EMPTY_0_S 25 -/** RMT_APB_MEM_WR_ERR_0 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_EMPTY_CH0 (BIT(25)) +#define RMT_MEM_EMPTY_CH0_M (RMT_MEM_EMPTY_CH0_V << RMT_MEM_EMPTY_CH0_S) +#define RMT_MEM_EMPTY_CH0_V 0x00000001U +#define RMT_MEM_EMPTY_CH0_S 25 +/** RMT_APB_MEM_WR_ERR_CH0 : RO; bitpos: [26]; default: 0; * This status bit will be set if the offset address out of memory size when writes * via APB bus. */ -#define RMT_APB_MEM_WR_ERR_0 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_0_M (RMT_APB_MEM_WR_ERR_0_V << RMT_APB_MEM_WR_ERR_0_S) -#define RMT_APB_MEM_WR_ERR_0_V 0x00000001U -#define RMT_APB_MEM_WR_ERR_0_S 26 +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH0_M (RMT_APB_MEM_WR_ERR_CH0_V << RMT_APB_MEM_WR_ERR_CH0_S) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH0_S 26 /** RMT_CH1STATUS_REG register * Channel 1 status register */ #define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x54) -/** RMT_MEM_RADDR_EX_1 : RO; bitpos: [9:0]; default: 0; +/** RMT_MEM_RADDR_EX_CH1 : RO; bitpos: [9:0]; default: 0; * This register records the memory address offset when transmitter of CHANNEL1 is * using the RAM. */ -#define RMT_MEM_RADDR_EX_1 0x000003FFU -#define RMT_MEM_RADDR_EX_1_M (RMT_MEM_RADDR_EX_1_V << RMT_MEM_RADDR_EX_1_S) -#define RMT_MEM_RADDR_EX_1_V 0x000003FFU -#define RMT_MEM_RADDR_EX_1_S 0 -/** RMT_APB_MEM_WADDR_1 : RO; bitpos: [20:11]; default: 0; +#define RMT_MEM_RADDR_EX_CH1 0x000003FFU +#define RMT_MEM_RADDR_EX_CH1_M (RMT_MEM_RADDR_EX_CH1_V << RMT_MEM_RADDR_EX_CH1_S) +#define RMT_MEM_RADDR_EX_CH1_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_APB_MEM_WADDR_CH1 : RO; bitpos: [20:11]; default: 0; * This register records the memory address offset when writes RAM over APB bus. */ -#define RMT_APB_MEM_WADDR_1 0x000003FFU -#define RMT_APB_MEM_WADDR_1_M (RMT_APB_MEM_WADDR_1_V << RMT_APB_MEM_WADDR_1_S) -#define RMT_APB_MEM_WADDR_1_V 0x000003FFU -#define RMT_APB_MEM_WADDR_1_S 11 -/** RMT_STATE_1 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_WADDR_CH1 0x000003FFU +#define RMT_APB_MEM_WADDR_CH1_M (RMT_APB_MEM_WADDR_CH1_V << RMT_APB_MEM_WADDR_CH1_S) +#define RMT_APB_MEM_WADDR_CH1_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH1_S 11 +/** RMT_STATE_CH1 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL1. */ -#define RMT_STATE_1 0x00000007U -#define RMT_STATE_1_M (RMT_STATE_1_V << RMT_STATE_1_S) -#define RMT_STATE_1_V 0x00000007U -#define RMT_STATE_1_S 22 -/** RMT_MEM_EMPTY_1 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH1 0x00000007U +#define RMT_STATE_CH1_M (RMT_STATE_CH1_V << RMT_STATE_CH1_S) +#define RMT_STATE_CH1_V 0x00000007U +#define RMT_STATE_CH1_S 22 +/** RMT_MEM_EMPTY_CH1 : RO; bitpos: [25]; default: 0; * This status bit will be set when the data to be set is more than memory size and * the wraparound mode is disabled. */ -#define RMT_MEM_EMPTY_1 (BIT(25)) -#define RMT_MEM_EMPTY_1_M (RMT_MEM_EMPTY_1_V << RMT_MEM_EMPTY_1_S) -#define RMT_MEM_EMPTY_1_V 0x00000001U -#define RMT_MEM_EMPTY_1_S 25 -/** RMT_APB_MEM_WR_ERR_1 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_EMPTY_CH1 (BIT(25)) +#define RMT_MEM_EMPTY_CH1_M (RMT_MEM_EMPTY_CH1_V << RMT_MEM_EMPTY_CH1_S) +#define RMT_MEM_EMPTY_CH1_V 0x00000001U +#define RMT_MEM_EMPTY_CH1_S 25 +/** RMT_APB_MEM_WR_ERR_CH1 : RO; bitpos: [26]; default: 0; * This status bit will be set if the offset address out of memory size when writes * via APB bus. */ -#define RMT_APB_MEM_WR_ERR_1 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_1_M (RMT_APB_MEM_WR_ERR_1_V << RMT_APB_MEM_WR_ERR_1_S) -#define RMT_APB_MEM_WR_ERR_1_V 0x00000001U -#define RMT_APB_MEM_WR_ERR_1_S 26 +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH1_M (RMT_APB_MEM_WR_ERR_CH1_V << RMT_APB_MEM_WR_ERR_CH1_S) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH1_S 26 /** RMT_CH2STATUS_REG register * Channel 2 status register */ #define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x58) -/** RMT_MEM_RADDR_EX_2 : RO; bitpos: [9:0]; default: 0; +/** RMT_MEM_RADDR_EX_CH2 : RO; bitpos: [9:0]; default: 0; * This register records the memory address offset when transmitter of CHANNEL2 is * using the RAM. */ -#define RMT_MEM_RADDR_EX_2 0x000003FFU -#define RMT_MEM_RADDR_EX_2_M (RMT_MEM_RADDR_EX_2_V << RMT_MEM_RADDR_EX_2_S) -#define RMT_MEM_RADDR_EX_2_V 0x000003FFU -#define RMT_MEM_RADDR_EX_2_S 0 -/** RMT_APB_MEM_WADDR_2 : RO; bitpos: [20:11]; default: 0; +#define RMT_MEM_RADDR_EX_CH2 0x000003FFU +#define RMT_MEM_RADDR_EX_CH2_M (RMT_MEM_RADDR_EX_CH2_V << RMT_MEM_RADDR_EX_CH2_S) +#define RMT_MEM_RADDR_EX_CH2_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH2_S 0 +/** RMT_APB_MEM_WADDR_CH2 : RO; bitpos: [20:11]; default: 0; * This register records the memory address offset when writes RAM over APB bus. */ -#define RMT_APB_MEM_WADDR_2 0x000003FFU -#define RMT_APB_MEM_WADDR_2_M (RMT_APB_MEM_WADDR_2_V << RMT_APB_MEM_WADDR_2_S) -#define RMT_APB_MEM_WADDR_2_V 0x000003FFU -#define RMT_APB_MEM_WADDR_2_S 11 -/** RMT_STATE_2 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_WADDR_CH2 0x000003FFU +#define RMT_APB_MEM_WADDR_CH2_M (RMT_APB_MEM_WADDR_CH2_V << RMT_APB_MEM_WADDR_CH2_S) +#define RMT_APB_MEM_WADDR_CH2_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH2_S 11 +/** RMT_STATE_CH2 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL2. */ -#define RMT_STATE_2 0x00000007U -#define RMT_STATE_2_M (RMT_STATE_2_V << RMT_STATE_2_S) -#define RMT_STATE_2_V 0x00000007U -#define RMT_STATE_2_S 22 -/** RMT_MEM_EMPTY_2 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH2 0x00000007U +#define RMT_STATE_CH2_M (RMT_STATE_CH2_V << RMT_STATE_CH2_S) +#define RMT_STATE_CH2_V 0x00000007U +#define RMT_STATE_CH2_S 22 +/** RMT_MEM_EMPTY_CH2 : RO; bitpos: [25]; default: 0; * This status bit will be set when the data to be set is more than memory size and * the wraparound mode is disabled. */ -#define RMT_MEM_EMPTY_2 (BIT(25)) -#define RMT_MEM_EMPTY_2_M (RMT_MEM_EMPTY_2_V << RMT_MEM_EMPTY_2_S) -#define RMT_MEM_EMPTY_2_V 0x00000001U -#define RMT_MEM_EMPTY_2_S 25 -/** RMT_APB_MEM_WR_ERR_2 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_EMPTY_CH2 (BIT(25)) +#define RMT_MEM_EMPTY_CH2_M (RMT_MEM_EMPTY_CH2_V << RMT_MEM_EMPTY_CH2_S) +#define RMT_MEM_EMPTY_CH2_V 0x00000001U +#define RMT_MEM_EMPTY_CH2_S 25 +/** RMT_APB_MEM_WR_ERR_CH2 : RO; bitpos: [26]; default: 0; * This status bit will be set if the offset address out of memory size when writes * via APB bus. */ -#define RMT_APB_MEM_WR_ERR_2 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_2_M (RMT_APB_MEM_WR_ERR_2_V << RMT_APB_MEM_WR_ERR_2_S) -#define RMT_APB_MEM_WR_ERR_2_V 0x00000001U -#define RMT_APB_MEM_WR_ERR_2_S 26 +#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH2_M (RMT_APB_MEM_WR_ERR_CH2_V << RMT_APB_MEM_WR_ERR_CH2_S) +#define RMT_APB_MEM_WR_ERR_CH2_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH2_S 26 /** RMT_CH3STATUS_REG register * Channel 3 status register */ #define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x5c) -/** RMT_MEM_RADDR_EX_3 : RO; bitpos: [9:0]; default: 0; +/** RMT_MEM_RADDR_EX_CH3 : RO; bitpos: [9:0]; default: 0; * This register records the memory address offset when transmitter of CHANNEL3 is * using the RAM. */ -#define RMT_MEM_RADDR_EX_3 0x000003FFU -#define RMT_MEM_RADDR_EX_3_M (RMT_MEM_RADDR_EX_3_V << RMT_MEM_RADDR_EX_3_S) -#define RMT_MEM_RADDR_EX_3_V 0x000003FFU -#define RMT_MEM_RADDR_EX_3_S 0 -/** RMT_APB_MEM_WADDR_3 : RO; bitpos: [20:11]; default: 0; +#define RMT_MEM_RADDR_EX_CH3 0x000003FFU +#define RMT_MEM_RADDR_EX_CH3_M (RMT_MEM_RADDR_EX_CH3_V << RMT_MEM_RADDR_EX_CH3_S) +#define RMT_MEM_RADDR_EX_CH3_V 0x000003FFU +#define RMT_MEM_RADDR_EX_CH3_S 0 +/** RMT_APB_MEM_WADDR_CH3 : RO; bitpos: [20:11]; default: 0; * This register records the memory address offset when writes RAM over APB bus. */ -#define RMT_APB_MEM_WADDR_3 0x000003FFU -#define RMT_APB_MEM_WADDR_3_M (RMT_APB_MEM_WADDR_3_V << RMT_APB_MEM_WADDR_3_S) -#define RMT_APB_MEM_WADDR_3_V 0x000003FFU -#define RMT_APB_MEM_WADDR_3_S 11 -/** RMT_STATE_3 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_WADDR_CH3 0x000003FFU +#define RMT_APB_MEM_WADDR_CH3_M (RMT_APB_MEM_WADDR_CH3_V << RMT_APB_MEM_WADDR_CH3_S) +#define RMT_APB_MEM_WADDR_CH3_V 0x000003FFU +#define RMT_APB_MEM_WADDR_CH3_S 11 +/** RMT_STATE_CH3 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL3. */ -#define RMT_STATE_3 0x00000007U -#define RMT_STATE_3_M (RMT_STATE_3_V << RMT_STATE_3_S) -#define RMT_STATE_3_V 0x00000007U -#define RMT_STATE_3_S 22 -/** RMT_MEM_EMPTY_3 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH3 0x00000007U +#define RMT_STATE_CH3_M (RMT_STATE_CH3_V << RMT_STATE_CH3_S) +#define RMT_STATE_CH3_V 0x00000007U +#define RMT_STATE_CH3_S 22 +/** RMT_MEM_EMPTY_CH3 : RO; bitpos: [25]; default: 0; * This status bit will be set when the data to be set is more than memory size and * the wraparound mode is disabled. */ -#define RMT_MEM_EMPTY_3 (BIT(25)) -#define RMT_MEM_EMPTY_3_M (RMT_MEM_EMPTY_3_V << RMT_MEM_EMPTY_3_S) -#define RMT_MEM_EMPTY_3_V 0x00000001U -#define RMT_MEM_EMPTY_3_S 25 -/** RMT_APB_MEM_WR_ERR_3 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_EMPTY_CH3 (BIT(25)) +#define RMT_MEM_EMPTY_CH3_M (RMT_MEM_EMPTY_CH3_V << RMT_MEM_EMPTY_CH3_S) +#define RMT_MEM_EMPTY_CH3_V 0x00000001U +#define RMT_MEM_EMPTY_CH3_S 25 +/** RMT_APB_MEM_WR_ERR_CH3 : RO; bitpos: [26]; default: 0; * This status bit will be set if the offset address out of memory size when writes * via APB bus. */ -#define RMT_APB_MEM_WR_ERR_3 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_3_M (RMT_APB_MEM_WR_ERR_3_V << RMT_APB_MEM_WR_ERR_3_S) -#define RMT_APB_MEM_WR_ERR_3_V 0x00000001U -#define RMT_APB_MEM_WR_ERR_3_S 26 +#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH3_M (RMT_APB_MEM_WR_ERR_CH3_V << RMT_APB_MEM_WR_ERR_CH3_S) +#define RMT_APB_MEM_WR_ERR_CH3_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_CH3_S 26 /** RMT_CH4STATUS_REG register * Channel 4 status register */ #define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x60) -/** RMT_MEM_WADDR_EX_4 : RO; bitpos: [9:0]; default: 192; +/** RMT_MEM_WADDR_EX_CH4 : RO; bitpos: [9:0]; default: 192; * This register records the memory address offset when receiver of CHANNEL4 is using * the RAM. */ -#define RMT_MEM_WADDR_EX_4 0x000003FFU -#define RMT_MEM_WADDR_EX_4_M (RMT_MEM_WADDR_EX_4_V << RMT_MEM_WADDR_EX_4_S) -#define RMT_MEM_WADDR_EX_4_V 0x000003FFU -#define RMT_MEM_WADDR_EX_4_S 0 -/** RMT_APB_MEM_RADDR_4 : RO; bitpos: [20:11]; default: 192; +#define RMT_MEM_WADDR_EX_CH4 0x000003FFU +#define RMT_MEM_WADDR_EX_CH4_M (RMT_MEM_WADDR_EX_CH4_V << RMT_MEM_WADDR_EX_CH4_S) +#define RMT_MEM_WADDR_EX_CH4_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH4_S 0 +/** RMT_APB_MEM_RADDR_CH4 : RO; bitpos: [20:11]; default: 192; * This register records the memory address offset when reads RAM over APB bus. */ -#define RMT_APB_MEM_RADDR_4 0x000003FFU -#define RMT_APB_MEM_RADDR_4_M (RMT_APB_MEM_RADDR_4_V << RMT_APB_MEM_RADDR_4_S) -#define RMT_APB_MEM_RADDR_4_V 0x000003FFU -#define RMT_APB_MEM_RADDR_4_S 11 -/** RMT_STATE_4 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_RADDR_CH4 0x000003FFU +#define RMT_APB_MEM_RADDR_CH4_M (RMT_APB_MEM_RADDR_CH4_V << RMT_APB_MEM_RADDR_CH4_S) +#define RMT_APB_MEM_RADDR_CH4_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH4_S 11 +/** RMT_STATE_CH4 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL4. */ -#define RMT_STATE_4 0x00000007U -#define RMT_STATE_4_M (RMT_STATE_4_V << RMT_STATE_4_S) -#define RMT_STATE_4_V 0x00000007U -#define RMT_STATE_4_S 22 -/** RMT_MEM_OWNER_ERR_4 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH4 0x00000007U +#define RMT_STATE_CH4_M (RMT_STATE_CH4_V << RMT_STATE_CH4_S) +#define RMT_STATE_CH4_V 0x00000007U +#define RMT_STATE_CH4_S 22 +/** RMT_MEM_OWNER_ERR_CH4 : RO; bitpos: [25]; default: 0; * This status bit will be set when the ownership of memory block is wrong. */ -#define RMT_MEM_OWNER_ERR_4 (BIT(25)) -#define RMT_MEM_OWNER_ERR_4_M (RMT_MEM_OWNER_ERR_4_V << RMT_MEM_OWNER_ERR_4_S) -#define RMT_MEM_OWNER_ERR_4_V 0x00000001U -#define RMT_MEM_OWNER_ERR_4_S 25 -/** RMT_MEM_FULL_4 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_OWNER_ERR_CH4 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH4_M (RMT_MEM_OWNER_ERR_CH4_V << RMT_MEM_OWNER_ERR_CH4_S) +#define RMT_MEM_OWNER_ERR_CH4_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH4_S 25 +/** RMT_MEM_FULL_CH4 : RO; bitpos: [26]; default: 0; * This status bit will be set if the receiver receives more data than the memory size. */ -#define RMT_MEM_FULL_4 (BIT(26)) -#define RMT_MEM_FULL_4_M (RMT_MEM_FULL_4_V << RMT_MEM_FULL_4_S) -#define RMT_MEM_FULL_4_V 0x00000001U -#define RMT_MEM_FULL_4_S 26 -/** RMT_APB_MEM_RD_ERR_4 : RO; bitpos: [27]; default: 0; +#define RMT_MEM_FULL_CH4 (BIT(26)) +#define RMT_MEM_FULL_CH4_M (RMT_MEM_FULL_CH4_V << RMT_MEM_FULL_CH4_S) +#define RMT_MEM_FULL_CH4_V 0x00000001U +#define RMT_MEM_FULL_CH4_S 26 +/** RMT_APB_MEM_RD_ERR_CH4 : RO; bitpos: [27]; default: 0; * This status bit will be set if the offset address out of memory size when reads via * APB bus. */ -#define RMT_APB_MEM_RD_ERR_4 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_4_M (RMT_APB_MEM_RD_ERR_4_V << RMT_APB_MEM_RD_ERR_4_S) -#define RMT_APB_MEM_RD_ERR_4_V 0x00000001U -#define RMT_APB_MEM_RD_ERR_4_S 27 +#define RMT_APB_MEM_RD_ERR_CH4 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH4_M (RMT_APB_MEM_RD_ERR_CH4_V << RMT_APB_MEM_RD_ERR_CH4_S) +#define RMT_APB_MEM_RD_ERR_CH4_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH4_S 27 /** RMT_CH5STATUS_REG register * Channel 5 status register */ #define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x64) -/** RMT_MEM_WADDR_EX_5 : RO; bitpos: [9:0]; default: 192; +/** RMT_MEM_WADDR_EX_CH5 : RO; bitpos: [9:0]; default: 192; * This register records the memory address offset when receiver of CHANNEL5 is using * the RAM. */ -#define RMT_MEM_WADDR_EX_5 0x000003FFU -#define RMT_MEM_WADDR_EX_5_M (RMT_MEM_WADDR_EX_5_V << RMT_MEM_WADDR_EX_5_S) -#define RMT_MEM_WADDR_EX_5_V 0x000003FFU -#define RMT_MEM_WADDR_EX_5_S 0 -/** RMT_APB_MEM_RADDR_5 : RO; bitpos: [20:11]; default: 192; +#define RMT_MEM_WADDR_EX_CH5 0x000003FFU +#define RMT_MEM_WADDR_EX_CH5_M (RMT_MEM_WADDR_EX_CH5_V << RMT_MEM_WADDR_EX_CH5_S) +#define RMT_MEM_WADDR_EX_CH5_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH5_S 0 +/** RMT_APB_MEM_RADDR_CH5 : RO; bitpos: [20:11]; default: 192; * This register records the memory address offset when reads RAM over APB bus. */ -#define RMT_APB_MEM_RADDR_5 0x000003FFU -#define RMT_APB_MEM_RADDR_5_M (RMT_APB_MEM_RADDR_5_V << RMT_APB_MEM_RADDR_5_S) -#define RMT_APB_MEM_RADDR_5_V 0x000003FFU -#define RMT_APB_MEM_RADDR_5_S 11 -/** RMT_STATE_5 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_RADDR_CH5 0x000003FFU +#define RMT_APB_MEM_RADDR_CH5_M (RMT_APB_MEM_RADDR_CH5_V << RMT_APB_MEM_RADDR_CH5_S) +#define RMT_APB_MEM_RADDR_CH5_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH5_S 11 +/** RMT_STATE_CH5 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL5. */ -#define RMT_STATE_5 0x00000007U -#define RMT_STATE_5_M (RMT_STATE_5_V << RMT_STATE_5_S) -#define RMT_STATE_5_V 0x00000007U -#define RMT_STATE_5_S 22 -/** RMT_MEM_OWNER_ERR_5 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH5 0x00000007U +#define RMT_STATE_CH5_M (RMT_STATE_CH5_V << RMT_STATE_CH5_S) +#define RMT_STATE_CH5_V 0x00000007U +#define RMT_STATE_CH5_S 22 +/** RMT_MEM_OWNER_ERR_CH5 : RO; bitpos: [25]; default: 0; * This status bit will be set when the ownership of memory block is wrong. */ -#define RMT_MEM_OWNER_ERR_5 (BIT(25)) -#define RMT_MEM_OWNER_ERR_5_M (RMT_MEM_OWNER_ERR_5_V << RMT_MEM_OWNER_ERR_5_S) -#define RMT_MEM_OWNER_ERR_5_V 0x00000001U -#define RMT_MEM_OWNER_ERR_5_S 25 -/** RMT_MEM_FULL_5 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_OWNER_ERR_CH5 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH5_M (RMT_MEM_OWNER_ERR_CH5_V << RMT_MEM_OWNER_ERR_CH5_S) +#define RMT_MEM_OWNER_ERR_CH5_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH5_S 25 +/** RMT_MEM_FULL_CH5 : RO; bitpos: [26]; default: 0; * This status bit will be set if the receiver receives more data than the memory size. */ -#define RMT_MEM_FULL_5 (BIT(26)) -#define RMT_MEM_FULL_5_M (RMT_MEM_FULL_5_V << RMT_MEM_FULL_5_S) -#define RMT_MEM_FULL_5_V 0x00000001U -#define RMT_MEM_FULL_5_S 26 -/** RMT_APB_MEM_RD_ERR_5 : RO; bitpos: [27]; default: 0; +#define RMT_MEM_FULL_CH5 (BIT(26)) +#define RMT_MEM_FULL_CH5_M (RMT_MEM_FULL_CH5_V << RMT_MEM_FULL_CH5_S) +#define RMT_MEM_FULL_CH5_V 0x00000001U +#define RMT_MEM_FULL_CH5_S 26 +/** RMT_APB_MEM_RD_ERR_CH5 : RO; bitpos: [27]; default: 0; * This status bit will be set if the offset address out of memory size when reads via * APB bus. */ -#define RMT_APB_MEM_RD_ERR_5 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_5_M (RMT_APB_MEM_RD_ERR_5_V << RMT_APB_MEM_RD_ERR_5_S) -#define RMT_APB_MEM_RD_ERR_5_V 0x00000001U -#define RMT_APB_MEM_RD_ERR_5_S 27 +#define RMT_APB_MEM_RD_ERR_CH5 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH5_M (RMT_APB_MEM_RD_ERR_CH5_V << RMT_APB_MEM_RD_ERR_CH5_S) +#define RMT_APB_MEM_RD_ERR_CH5_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH5_S 27 /** RMT_CH6STATUS_REG register * Channel 6 status register */ #define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x68) -/** RMT_MEM_WADDR_EX_6 : RO; bitpos: [9:0]; default: 192; +/** RMT_MEM_WADDR_EX_CH6 : RO; bitpos: [9:0]; default: 192; * This register records the memory address offset when receiver of CHANNEL6 is using * the RAM. */ -#define RMT_MEM_WADDR_EX_6 0x000003FFU -#define RMT_MEM_WADDR_EX_6_M (RMT_MEM_WADDR_EX_6_V << RMT_MEM_WADDR_EX_6_S) -#define RMT_MEM_WADDR_EX_6_V 0x000003FFU -#define RMT_MEM_WADDR_EX_6_S 0 -/** RMT_APB_MEM_RADDR_6 : RO; bitpos: [20:11]; default: 192; +#define RMT_MEM_WADDR_EX_CH6 0x000003FFU +#define RMT_MEM_WADDR_EX_CH6_M (RMT_MEM_WADDR_EX_CH6_V << RMT_MEM_WADDR_EX_CH6_S) +#define RMT_MEM_WADDR_EX_CH6_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH6_S 0 +/** RMT_APB_MEM_RADDR_CH6 : RO; bitpos: [20:11]; default: 192; * This register records the memory address offset when reads RAM over APB bus. */ -#define RMT_APB_MEM_RADDR_6 0x000003FFU -#define RMT_APB_MEM_RADDR_6_M (RMT_APB_MEM_RADDR_6_V << RMT_APB_MEM_RADDR_6_S) -#define RMT_APB_MEM_RADDR_6_V 0x000003FFU -#define RMT_APB_MEM_RADDR_6_S 11 -/** RMT_STATE_6 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_RADDR_CH6 0x000003FFU +#define RMT_APB_MEM_RADDR_CH6_M (RMT_APB_MEM_RADDR_CH6_V << RMT_APB_MEM_RADDR_CH6_S) +#define RMT_APB_MEM_RADDR_CH6_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH6_S 11 +/** RMT_STATE_CH6 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL6. */ -#define RMT_STATE_6 0x00000007U -#define RMT_STATE_6_M (RMT_STATE_6_V << RMT_STATE_6_S) -#define RMT_STATE_6_V 0x00000007U -#define RMT_STATE_6_S 22 -/** RMT_MEM_OWNER_ERR_6 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH6 0x00000007U +#define RMT_STATE_CH6_M (RMT_STATE_CH6_V << RMT_STATE_CH6_S) +#define RMT_STATE_CH6_V 0x00000007U +#define RMT_STATE_CH6_S 22 +/** RMT_MEM_OWNER_ERR_CH6 : RO; bitpos: [25]; default: 0; * This status bit will be set when the ownership of memory block is wrong. */ -#define RMT_MEM_OWNER_ERR_6 (BIT(25)) -#define RMT_MEM_OWNER_ERR_6_M (RMT_MEM_OWNER_ERR_6_V << RMT_MEM_OWNER_ERR_6_S) -#define RMT_MEM_OWNER_ERR_6_V 0x00000001U -#define RMT_MEM_OWNER_ERR_6_S 25 -/** RMT_MEM_FULL_6 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_OWNER_ERR_CH6 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH6_M (RMT_MEM_OWNER_ERR_CH6_V << RMT_MEM_OWNER_ERR_CH6_S) +#define RMT_MEM_OWNER_ERR_CH6_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH6_S 25 +/** RMT_MEM_FULL_CH6 : RO; bitpos: [26]; default: 0; * This status bit will be set if the receiver receives more data than the memory size. */ -#define RMT_MEM_FULL_6 (BIT(26)) -#define RMT_MEM_FULL_6_M (RMT_MEM_FULL_6_V << RMT_MEM_FULL_6_S) -#define RMT_MEM_FULL_6_V 0x00000001U -#define RMT_MEM_FULL_6_S 26 -/** RMT_APB_MEM_RD_ERR_6 : RO; bitpos: [27]; default: 0; +#define RMT_MEM_FULL_CH6 (BIT(26)) +#define RMT_MEM_FULL_CH6_M (RMT_MEM_FULL_CH6_V << RMT_MEM_FULL_CH6_S) +#define RMT_MEM_FULL_CH6_V 0x00000001U +#define RMT_MEM_FULL_CH6_S 26 +/** RMT_APB_MEM_RD_ERR_CH6 : RO; bitpos: [27]; default: 0; * This status bit will be set if the offset address out of memory size when reads via * APB bus. */ -#define RMT_APB_MEM_RD_ERR_6 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_6_M (RMT_APB_MEM_RD_ERR_6_V << RMT_APB_MEM_RD_ERR_6_S) -#define RMT_APB_MEM_RD_ERR_6_V 0x00000001U -#define RMT_APB_MEM_RD_ERR_6_S 27 +#define RMT_APB_MEM_RD_ERR_CH6 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH6_M (RMT_APB_MEM_RD_ERR_CH6_V << RMT_APB_MEM_RD_ERR_CH6_S) +#define RMT_APB_MEM_RD_ERR_CH6_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH6_S 27 /** RMT_CH7STATUS_REG register * Channel 7 status register */ #define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x6c) -/** RMT_MEM_WADDR_EX_7 : RO; bitpos: [9:0]; default: 192; +/** RMT_MEM_WADDR_EX_CH7 : RO; bitpos: [9:0]; default: 192; * This register records the memory address offset when receiver of CHANNEL7 is using * the RAM. */ -#define RMT_MEM_WADDR_EX_7 0x000003FFU -#define RMT_MEM_WADDR_EX_7_M (RMT_MEM_WADDR_EX_7_V << RMT_MEM_WADDR_EX_7_S) -#define RMT_MEM_WADDR_EX_7_V 0x000003FFU -#define RMT_MEM_WADDR_EX_7_S 0 -/** RMT_APB_MEM_RADDR_7 : RO; bitpos: [20:11]; default: 192; +#define RMT_MEM_WADDR_EX_CH7 0x000003FFU +#define RMT_MEM_WADDR_EX_CH7_M (RMT_MEM_WADDR_EX_CH7_V << RMT_MEM_WADDR_EX_CH7_S) +#define RMT_MEM_WADDR_EX_CH7_V 0x000003FFU +#define RMT_MEM_WADDR_EX_CH7_S 0 +/** RMT_APB_MEM_RADDR_CH7 : RO; bitpos: [20:11]; default: 192; * This register records the memory address offset when reads RAM over APB bus. */ -#define RMT_APB_MEM_RADDR_7 0x000003FFU -#define RMT_APB_MEM_RADDR_7_M (RMT_APB_MEM_RADDR_7_V << RMT_APB_MEM_RADDR_7_S) -#define RMT_APB_MEM_RADDR_7_V 0x000003FFU -#define RMT_APB_MEM_RADDR_7_S 11 -/** RMT_STATE_7 : RO; bitpos: [24:22]; default: 0; +#define RMT_APB_MEM_RADDR_CH7 0x000003FFU +#define RMT_APB_MEM_RADDR_CH7_M (RMT_APB_MEM_RADDR_CH7_V << RMT_APB_MEM_RADDR_CH7_S) +#define RMT_APB_MEM_RADDR_CH7_V 0x000003FFU +#define RMT_APB_MEM_RADDR_CH7_S 11 +/** RMT_STATE_CH7 : RO; bitpos: [24:22]; default: 0; * This register records the FSM status of CHANNEL7. */ -#define RMT_STATE_7 0x00000007U -#define RMT_STATE_7_M (RMT_STATE_7_V << RMT_STATE_7_S) -#define RMT_STATE_7_V 0x00000007U -#define RMT_STATE_7_S 22 -/** RMT_MEM_OWNER_ERR_7 : RO; bitpos: [25]; default: 0; +#define RMT_STATE_CH7 0x00000007U +#define RMT_STATE_CH7_M (RMT_STATE_CH7_V << RMT_STATE_CH7_S) +#define RMT_STATE_CH7_V 0x00000007U +#define RMT_STATE_CH7_S 22 +/** RMT_MEM_OWNER_ERR_CH7 : RO; bitpos: [25]; default: 0; * This status bit will be set when the ownership of memory block is wrong. */ -#define RMT_MEM_OWNER_ERR_7 (BIT(25)) -#define RMT_MEM_OWNER_ERR_7_M (RMT_MEM_OWNER_ERR_7_V << RMT_MEM_OWNER_ERR_7_S) -#define RMT_MEM_OWNER_ERR_7_V 0x00000001U -#define RMT_MEM_OWNER_ERR_7_S 25 -/** RMT_MEM_FULL_7 : RO; bitpos: [26]; default: 0; +#define RMT_MEM_OWNER_ERR_CH7 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH7_M (RMT_MEM_OWNER_ERR_CH7_V << RMT_MEM_OWNER_ERR_CH7_S) +#define RMT_MEM_OWNER_ERR_CH7_V 0x00000001U +#define RMT_MEM_OWNER_ERR_CH7_S 25 +/** RMT_MEM_FULL_CH7 : RO; bitpos: [26]; default: 0; * This status bit will be set if the receiver receives more data than the memory size. */ -#define RMT_MEM_FULL_7 (BIT(26)) -#define RMT_MEM_FULL_7_M (RMT_MEM_FULL_7_V << RMT_MEM_FULL_7_S) -#define RMT_MEM_FULL_7_V 0x00000001U -#define RMT_MEM_FULL_7_S 26 -/** RMT_APB_MEM_RD_ERR_7 : RO; bitpos: [27]; default: 0; +#define RMT_MEM_FULL_CH7 (BIT(26)) +#define RMT_MEM_FULL_CH7_M (RMT_MEM_FULL_CH7_V << RMT_MEM_FULL_CH7_S) +#define RMT_MEM_FULL_CH7_V 0x00000001U +#define RMT_MEM_FULL_CH7_S 26 +/** RMT_APB_MEM_RD_ERR_CH7 : RO; bitpos: [27]; default: 0; * This status bit will be set if the offset address out of memory size when reads via * APB bus. */ -#define RMT_APB_MEM_RD_ERR_7 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_7_M (RMT_APB_MEM_RD_ERR_7_V << RMT_APB_MEM_RD_ERR_7_S) -#define RMT_APB_MEM_RD_ERR_7_V 0x00000001U -#define RMT_APB_MEM_RD_ERR_7_S 27 +#define RMT_APB_MEM_RD_ERR_CH7 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH7_M (RMT_APB_MEM_RD_ERR_CH7_V << RMT_APB_MEM_RD_ERR_CH7_S) +#define RMT_APB_MEM_RD_ERR_CH7_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_CH7_S 27 /** RMT_INT_RAW_REG register * Raw interrupt status @@ -2656,49 +2656,49 @@ extern "C" { * Channel 4 Rx event configuration register */ #define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0xb0) -/** RMT_CH4_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; +/** RMT_RX_LIM_CH4 : R/W; bitpos: [8:0]; default: 128; * This register is used to configure the maximum entries that CHANNEL4 can receive. */ -#define RMT_CH4_RX_LIM_REG 0x000001FFU -#define RMT_CH4_RX_LIM_REG_M (RMT_CH4_RX_LIM_REG_V << RMT_CH4_RX_LIM_REG_S) -#define RMT_CH4_RX_LIM_REG_V 0x000001FFU -#define RMT_CH4_RX_LIM_REG_S 0 +#define RMT_RX_LIM_CH4 0x000001FFU +#define RMT_RX_LIM_CH4_M (RMT_RX_LIM_CH4_V << RMT_RX_LIM_CH4_S) +#define RMT_RX_LIM_CH4_V 0x000001FFU +#define RMT_RX_LIM_CH4_S 0 /** RMT_CH5_RX_LIM_REG register * Channel 5 Rx event configuration register */ #define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0xb4) -/** RMT_CH5_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; +/** RMT_RX_LIM_CH5 : R/W; bitpos: [8:0]; default: 128; * This register is used to configure the maximum entries that CHANNEL5 can receive. */ -#define RMT_CH5_RX_LIM_REG 0x000001FFU -#define RMT_CH5_RX_LIM_REG_M (RMT_CH5_RX_LIM_REG_V << RMT_CH5_RX_LIM_REG_S) -#define RMT_CH5_RX_LIM_REG_V 0x000001FFU -#define RMT_CH5_RX_LIM_REG_S 0 +#define RMT_RX_LIM_CH5 0x000001FFU +#define RMT_RX_LIM_CH5_M (RMT_RX_LIM_CH5_V << RMT_RX_LIM_CH5_S) +#define RMT_RX_LIM_CH5_V 0x000001FFU +#define RMT_RX_LIM_CH5_S 0 /** RMT_CH6_RX_LIM_REG register * Channel 6 Rx event configuration register */ #define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0xb8) -/** RMT_CH6_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; +/** RMT_RX_LIM_CH6 : R/W; bitpos: [8:0]; default: 128; * This register is used to configure the maximum entries that CHANNEL6 can receive. */ -#define RMT_CH6_RX_LIM_REG 0x000001FFU -#define RMT_CH6_RX_LIM_REG_M (RMT_CH6_RX_LIM_REG_V << RMT_CH6_RX_LIM_REG_S) -#define RMT_CH6_RX_LIM_REG_V 0x000001FFU -#define RMT_CH6_RX_LIM_REG_S 0 +#define RMT_RX_LIM_CH6 0x000001FFU +#define RMT_RX_LIM_CH6_M (RMT_RX_LIM_CH6_V << RMT_RX_LIM_CH6_S) +#define RMT_RX_LIM_CH6_V 0x000001FFU +#define RMT_RX_LIM_CH6_S 0 /** RMT_CH7_RX_LIM_REG register * Channel 7 Rx event configuration register */ #define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0xbc) -/** RMT_CH7_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; +/** RMT_RX_LIM_CH7 : R/W; bitpos: [8:0]; default: 128; * This register is used to configure the maximum entries that CHANNEL7 can receive. */ -#define RMT_CH7_RX_LIM_REG 0x000001FFU -#define RMT_CH7_RX_LIM_REG_M (RMT_CH7_RX_LIM_REG_V << RMT_CH7_RX_LIM_REG_S) -#define RMT_CH7_RX_LIM_REG_V 0x000001FFU -#define RMT_CH7_RX_LIM_REG_S 0 +#define RMT_RX_LIM_CH7 0x000001FFU +#define RMT_RX_LIM_CH7_M (RMT_RX_LIM_CH7_V << RMT_RX_LIM_CH7_S) +#define RMT_RX_LIM_CH7_V 0x000001FFU +#define RMT_RX_LIM_CH7_S 0 /** RMT_SYS_CONF_REG register * RMT apb configuration register