From 1b903111b6d7506d434d2dd36b0ea5fc66fe32bc Mon Sep 17 00:00:00 2001 From: suda-morris <362953310@qq.com> Date: Mon, 29 Jul 2019 11:35:00 +0800 Subject: [PATCH] efuse: update the scheme of getting chip revision --- components/efuse/esp32/esp_efuse_table.c | 11 ++++++- components/efuse/esp32/esp_efuse_table.csv | 15 +++++----- .../efuse/esp32/include/esp_efuse_table.h | 3 +- components/efuse/src/esp_efuse_fields.c | 28 +++++++++++++++-- components/esp32/Kconfig | 28 +++++++++++++++++ components/esp32/cpu_start.c | 12 +++++++- components/esp32/dport_access.c | 8 ++--- components/esp32/include/esp32/dport_access.h | 2 +- components/esp32/system_api.c | 30 +++++++------------ components/esptool_py/esptool | 2 +- .../soc/esp32/include/soc/dport_access.h | 8 ++--- components/soc/esp32/include/soc/soc.h | 2 +- 12 files changed, 106 insertions(+), 43 deletions(-) diff --git a/components/efuse/esp32/esp_efuse_table.c b/components/efuse/esp32/esp_efuse_table.c index 36b54b50ba..e0d4e2d104 100644 --- a/components/efuse/esp32/esp_efuse_table.c +++ b/components/efuse/esp32/esp_efuse_table.c @@ -17,7 +17,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 544d434da010ce22f7db1b14d38e1d66 +// md5_digest_table 2e23344575b3d07f01ecb695294e9770 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -151,6 +151,10 @@ static const esp_efuse_desc_t CHIP_VER_REV1[] = { {EFUSE_BLK0, 111, 1}, // EFUSE_RD_CHIP_VER_REV1, }; +static const esp_efuse_desc_t CHIP_VER_REV2[] = { + {EFUSE_BLK0, 180, 1}, // EFUSE_RD_CHIP_VER_REV2, +}; + static const esp_efuse_desc_t XPD_SDIO_REG[] = { {EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG, }; @@ -336,6 +340,11 @@ const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = { + &CHIP_VER_REV2[0], // EFUSE_RD_CHIP_VER_REV2 + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = { &XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG NULL diff --git a/components/efuse/esp32/esp_efuse_table.csv b/components/efuse/esp32/esp_efuse_table.csv index 23b28ec47d..1445ac8ae6 100644 --- a/components/efuse/esp32/esp_efuse_table.csv +++ b/components/efuse/esp32/esp_efuse_table.csv @@ -6,7 +6,7 @@ ########################################################################## # *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. # !!!!!!!!!!! # -# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table" +# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table" # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # @@ -36,11 +36,11 @@ ABS_DONE_0, EFUSE_BLK0, 196, 1, Secure boot is enabled for ENCRYPT_FLASH_KEY, EFUSE_BLK1, 0, MAX_BLK_LEN, Flash encrypt. Key. (length = "None" - 256. "3/4" - 192. "REPEAT" - 128) ENCRYPT_CONFIG, EFUSE_BLK0, 188, 4, Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M -DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT. -DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT. -DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE. -DISABLE_JTAG, EFUSE_BLK0, 198, 1, Flash encrypt. Disable JTAG. EFUSE_RD_DISABLE_JTAG. -CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, Flash encrypt. Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE. +DISABLE_DL_ENCRYPT, EFUSE_BLK0, 199, 1, Flash encrypt. Disable UART bootloader encryption. EFUSE_DISABLE_DL_ENCRYPT. +DISABLE_DL_DECRYPT, EFUSE_BLK0, 200, 1, Flash encrypt. Disable UART bootloader decryption. EFUSE_DISABLE_DL_DECRYPT. +DISABLE_DL_CACHE, EFUSE_BLK0, 201, 1, Flash encrypt. Disable UART bootloader MMU cache. EFUSE_DISABLE_DL_CACHE. +DISABLE_JTAG, EFUSE_BLK0, 198, 1, Flash encrypt. Disable JTAG. EFUSE_RD_DISABLE_JTAG. +CONSOLE_DEBUG_DISABLE, EFUSE_BLK0, 194, 1, Flash encrypt. Disable ROM BASIC interpreter fallback. EFUSE_RD_CONSOLE_DEBUG_DISABLE. FLASH_CRYPT_CNT, EFUSE_BLK0, 20, 7, Flash encrypt. Flash encryption is enabled if this field has an odd number of bits set. EFUSE_FLASH_CRYPT_CNT. # Write protection # @@ -53,7 +53,7 @@ WR_DIS_BLK3, EFUSE_BLK0, 9, 1, Write protection for EFUSE_B # Read protection # ################### RD_DIS_BLK1, EFUSE_BLK0, 16, 1, Flash encrypt. efuse_key_read_protected. EFUSE_RD_DIS_BLK1 -RD_DIS_BLK2, EFUSE_BLK0, 17, 1, Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2 +RD_DIS_BLK2, EFUSE_BLK0, 17, 1, Security boot. efuse_key_read_protected. EFUSE_RD_DIS_BLK2 RD_DIS_BLK3, EFUSE_BLK0, 18, 1, Read protection for EFUSE_BLK3. EFUSE_RD_DIS_BLK3 # Chip info # @@ -64,6 +64,7 @@ CHIP_VER_PKG, EFUSE_BLK0, 105, 3, EFUSE_RD_CHIP_VER_PKG CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1 +CHIP_VER_REV2, EFUSE_BLK0, 180, 1, EFUSE_RD_CHIP_VER_REV2 XPD_SDIO_REG, EFUSE_BLK0, 142, 1, EFUSE_RD_XPD_SDIO_REG SDIO_TIEH, EFUSE_BLK0, 143, 1, EFUSE_RD_SDIO_TIEH SDIO_FORCE, EFUSE_BLK0, 144, 1, EFUSE_RD_SDIO_FORCE diff --git a/components/efuse/esp32/include/esp_efuse_table.h b/components/efuse/esp32/include/esp_efuse_table.h index 807fb08882..a0137c012f 100644 --- a/components/efuse/esp32/include/esp_efuse_table.h +++ b/components/efuse/esp32/include/esp_efuse_table.h @@ -17,7 +17,7 @@ extern "C" { #endif -// md5_digest_table 544d434da010ce22f7db1b14d38e1d66 +// md5_digest_table 2e23344575b3d07f01ecb695294e9770 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -52,6 +52,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_PKG[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[]; extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[]; extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[]; extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[]; extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[]; diff --git a/components/efuse/src/esp_efuse_fields.c b/components/efuse/src/esp_efuse_fields.c index 5d440f383b..39a38f2744 100644 --- a/components/efuse/src/esp_efuse_fields.c +++ b/components/efuse/src/esp_efuse_fields.c @@ -23,6 +23,7 @@ #include "esp_log.h" #include "soc/efuse_periph.h" #include "bootloader_random.h" +#include "soc/apb_ctrl_reg.h" const static char *TAG = "efuse"; @@ -31,8 +32,29 @@ const static char *TAG = "efuse"; // Returns chip version from efuse uint8_t esp_efuse_get_chip_ver(void) { - uint8_t chip_ver; - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &chip_ver, 1); + uint8_t eco_bit0, eco_bit1, eco_bit2; + esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, &eco_bit0, 1); + esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, &eco_bit1, 1); + eco_bit2 = (REG_READ(APB_CTRL_DATE_REG) & 80000000) >> 31; + uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; + uint8_t chip_ver = 0; + switch (combine_value) { + case 0: + chip_ver = 0; + break; + case 1: + chip_ver = 1; + break; + case 3: + chip_ver = 2; + break; + case 7: + chip_ver = 3; + break; + default: + chip_ver = 0; + break; + } return chip_ver; } @@ -111,7 +133,7 @@ void esp_efuse_write_random_key(uint32_t blk_wdata0_reg) ESP_LOGV(TAG, "Writing random values to address 0x%08x", blk_wdata0_reg); for (int i = 0; i < 8; i++) { ESP_LOGV(TAG, "EFUSE_BLKx_WDATA%d_REG = 0x%08x", i, buf[i]); - REG_WRITE(blk_wdata0_reg + 4*i, buf[i]); + REG_WRITE(blk_wdata0_reg + 4 * i, buf[i]); } bzero(buf, sizeof(buf)); bzero(raw, sizeof(raw)); diff --git a/components/esp32/Kconfig b/components/esp32/Kconfig index 847560fe05..d0e9b5da0f 100644 --- a/components/esp32/Kconfig +++ b/components/esp32/Kconfig @@ -1,5 +1,33 @@ menu "ESP32-specific" + choice ESP32_REV_MIN + prompt "Minimum Supported ESP32 Revision" + default ESP32_REV_MIN_0 + help + Minimum revision that ESP-IDF would support. + ESP-IDF performs different strategy on different esp32 revision. + + config ESP32_REV_MIN_0 + bool "Rev 0" + config ESP32_REV_MIN_1 + bool "Rev 1" + config ESP32_REV_MIN_2 + bool "Rev 2" + config ESP32_REV_MIN_3 + bool "Rev 3" + endchoice + + config ESP32_REV_MIN + int + default 0 if ESP32_REV_MIN_0 + default 1 if ESP32_REV_MIN_1 + default 2 if ESP32_REV_MIN_2 + default 3 if ESP32_REV_MIN_3 + + config ESP32_DPORT_WORKAROUND + bool + default "y" if !FREERTOS_UNICORE && ESP32_REV_MIN < 2 + choice ESP32_DEFAULT_CPU_FREQ_MHZ prompt "CPU frequency" default ESP32_DEFAULT_CPU_FREQ_160 diff --git a/components/esp32/cpu_start.c b/components/esp32/cpu_start.c index f93e4cdf00..5a811d0373 100644 --- a/components/esp32/cpu_start.c +++ b/components/esp32/cpu_start.c @@ -204,7 +204,7 @@ void IRAM_ATTR call_start_cpu0() abort(); } ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_start_cpu1); - + esp_flash_enc_mode_t mode; mode = esp_get_flash_encryption_mode(); if (mode == ESP_FLASH_ENC_MODE_DEVELOPMENT) { @@ -408,6 +408,16 @@ void start_cpu0_default(void) esp_flash_app_init(); esp_err_t flash_ret = esp_flash_init_default_chip(); assert(flash_ret == ESP_OK); + + uint8_t revision = esp_efuse_get_chip_ver(); + ESP_LOGI(TAG, "Chip Revision: %d", revision); + if (revision > CONFIG_ESP32_REV_MIN) { + ESP_LOGW(TAG, "Chip revision is higher than the one configured in menuconfig. Suggest to upgrade it."); + } else if(revision != CONFIG_ESP32_REV_MIN) { + ESP_LOGE(TAG, "ESP-IDF can't support this chip revision. Modify minimum supported revision in menuconfig"); + abort(); + } + #ifdef CONFIG_PM_ENABLE esp_pm_impl_init(); #ifdef CONFIG_PM_DFS_INIT_AUTO diff --git a/components/esp32/dport_access.c b/components/esp32/dport_access.c index 2c83583350..f2fea2d359 100644 --- a/components/esp32/dport_access.c +++ b/components/esp32/dport_access.c @@ -16,7 +16,7 @@ * DPORT access is used for do protection when dual core access DPORT internal register and APB register via DPORT simultaneously * This function will be initialize after FreeRTOS startup. * When cpu0 want to access DPORT register, it should notify cpu1 enter in high-priority interrupt for be mute. When cpu1 already in high-priority interrupt, - * cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt. + * cpu0 can access DPORT register. Currently, cpu1 will wait for cpu0 finish access and exit high-priority interrupt. */ #include @@ -116,7 +116,7 @@ void IRAM_ATTR esp_dport_access_stall_other_cpu_end(void) { #ifndef CONFIG_FREERTOS_UNICORE int cpu_id = xPortGetCoreID(); - + if (dport_core_state[0] == DPORT_CORE_STATE_IDLE || dport_core_state[1] == DPORT_CORE_STATE_IDLE) { return; @@ -249,7 +249,7 @@ void IRAM_ATTR esp_dport_access_read_buffer(uint32_t *buff_out, uint32_t address */ uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg) { -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) return _DPORT_REG_READ(reg); #else uint32_t apb; @@ -295,7 +295,7 @@ uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg) */ uint32_t IRAM_ATTR esp_dport_access_sequence_reg_read(uint32_t reg) { -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) return _DPORT_REG_READ(reg); #else uint32_t apb; diff --git a/components/esp32/include/esp32/dport_access.h b/components/esp32/include/esp32/dport_access.h index f91c563e6b..8ea60c4cdb 100644 --- a/components/esp32/include/esp32/dport_access.h +++ b/components/esp32/include/esp32/dport_access.h @@ -33,7 +33,7 @@ uint32_t esp_dport_access_sequence_reg_read(uint32_t reg); //only call in case of panic(). void esp_dport_access_int_abort(void); -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) #define DPORT_STALL_OTHER_CPU_START() #define DPORT_STALL_OTHER_CPU_END() #define DPORT_INTERRUPT_DISABLE() diff --git a/components/esp32/system_api.c b/components/esp32/system_api.c index bd81a82db7..b7f6898b03 100644 --- a/components/esp32/system_api.c +++ b/components/esp32/system_api.c @@ -204,7 +204,7 @@ esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type) ESP_LOGW(TAG, "incorrect mac type"); break; } - + return ESP_OK; } @@ -307,10 +307,10 @@ void IRAM_ATTR esp_restart_noos() WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); // Reset wifi/bluetooth/ethernet/sdio (bb/mac) - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | - DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | + DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); @@ -366,35 +366,27 @@ const char* esp_get_idf_version(void) return IDF_VER; } -static void get_chip_info_esp32(esp_chip_info_t* out_info) +void esp_chip_info(esp_chip_info_t* out_info) { - uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG); + uint32_t efuse_rd3 = REG_READ(EFUSE_BLK0_RDATA3_REG); memset(out_info, 0, sizeof(*out_info)); - + out_info->model = CHIP_ESP32; - if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) { - out_info->revision = 1; - } - if ((reg & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) { + out_info->revision = esp_efuse_get_chip_ver(); + + if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_APP_CPU_M) == 0) { out_info->cores = 2; } else { out_info->cores = 1; } out_info->features = CHIP_FEATURE_WIFI_BGN; - if ((reg & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) { + if ((efuse_rd3 & EFUSE_RD_CHIP_VER_DIS_BT_M) == 0) { out_info->features |= CHIP_FEATURE_BT | CHIP_FEATURE_BLE; } - int package = (reg & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S; + int package = (efuse_rd3 & EFUSE_RD_CHIP_VER_PKG_M) >> EFUSE_RD_CHIP_VER_PKG_S; if (package == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || package == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) { out_info->features |= CHIP_FEATURE_EMB_FLASH; } } - -void esp_chip_info(esp_chip_info_t* out_info) -{ - // Only ESP32 is supported now, in the future call one of the - // chip-specific functions based on sdkconfig choice - return get_chip_info_esp32(out_info); -} diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index b4c418a5d9..1a7dbf787e 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit b4c418a5d90c94863b44c8661b9332cf229b08b7 +Subproject commit 1a7dbf787e7e504acdeaea074d15a5ccaf87e9e8 diff --git a/components/soc/esp32/include/soc/dport_access.h b/components/soc/esp32/include/soc/dport_access.h index 544560fdfb..fe7e70ebc0 100644 --- a/components/soc/esp32/include/soc/dport_access.h +++ b/components/soc/esp32/include/soc/dport_access.h @@ -48,7 +48,7 @@ extern "C" { // After completing read operations, use DPORT_STALL_OTHER_CPU_END(). // This method uses stall other CPU while reading DPORT registers. // Useful for compatibility, as well as for large consecutive readings. -// This method is slower, but must be used if ROM functions or +// This method is slower, but must be used if ROM functions or // other code is called which accesses DPORT without any other workaround. // *) The pre-readable APB register before reading the DPORT register // helps synchronize the operation of the two CPUs, @@ -73,7 +73,7 @@ extern "C" { */ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg) { -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) return _DPORT_REG_READ(reg); #else return esp_dport_access_reg_read(reg); @@ -106,7 +106,7 @@ static inline uint32_t IRAM_ATTR DPORT_REG_READ(uint32_t reg) */ static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg) { -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) return _DPORT_REG_READ(reg); #else return esp_dport_access_sequence_reg_read(reg); @@ -166,7 +166,7 @@ static inline uint32_t IRAM_ATTR DPORT_SEQUENCE_REG_READ(uint32_t reg) */ static inline uint32_t IRAM_ATTR DPORT_READ_PERI_REG(uint32_t reg) { -#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM) +#if defined(BOOTLOADER_BUILD) || !defined(CONFIG_ESP32_DPORT_WORKAROUND) || !defined(ESP_PLATFORM) return _DPORT_REG_READ(reg); #else return esp_dport_access_reg_read(reg); diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 5901abca23..419cf49b7f 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -108,7 +108,7 @@ #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) -#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM ) +#if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM ) #define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); #else #define ASSERT_IF_DPORT_REG(_r, OP)