kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/lan8720_ci_speed' into 'master'
Added ioctl option to read/write PHY registers + addressed LAN8720 errata Closes IDFCI-1845 See merge request espressif/esp-idf!26796pull/12666/head
commit
1844a6680c
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -121,6 +121,15 @@ typedef struct {
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esp_err_t (*write_phy_reg)(esp_eth_handle_t eth_handle, uint32_t phy_addr, uint32_t phy_reg, uint32_t reg_value);
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} esp_eth_config_t;
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/**
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* @brief Data structure to Read/Write PHY register via ioctl API
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*
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*/
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typedef struct {
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uint32_t reg_addr; /*!< PHY register address */
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uint32_t *reg_value_p; /*!< Pointer to a memory where the register value is read/written */
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} esp_eth_phy_reg_rw_data_t;
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/**
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* @brief Command list for ioctl API
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*
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@ -139,6 +148,8 @@ typedef enum {
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ETH_CMD_G_DUPLEX_MODE, /*!< Get Duplex mode */
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ETH_CMD_S_DUPLEX_MODE, /*!< Set Duplex mode */
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ETH_CMD_S_PHY_LOOPBACK, /*!< Set PHY loopback */
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ETH_CMD_READ_PHY_REG, /*!< Read PHY register */
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ETH_CMD_WRITE_PHY_REG, /*!< Write PHY register */
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ETH_CMD_CUSTOM_MAC_CMDS = 0x0FFF, // Offset for start of MAC custom commands
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ETH_CMD_CUSTOM_PHY_CMDS = 0x1FFF, // Offset for start of PHY custom commands
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@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -466,7 +466,23 @@ esp_err_t esp_eth_ioctl(esp_eth_handle_t hdl, esp_eth_io_cmd_t cmd, void *data)
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case ETH_CMD_S_PHY_LOOPBACK:
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ESP_GOTO_ON_FALSE(data, ESP_ERR_INVALID_ARG, err, TAG, "can't set loopback to null");
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ESP_GOTO_ON_ERROR(phy->loopback(phy, *(bool *)data), err, TAG, "configuration of phy loopback mode failed");
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break;
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case ETH_CMD_READ_PHY_REG:
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uint32_t phy_addr;
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ESP_GOTO_ON_FALSE(data, ESP_ERR_INVALID_ARG, err, TAG, "invalid register read/write info");
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esp_eth_phy_reg_rw_data_t *phy_r_data = (esp_eth_phy_reg_rw_data_t *)data;
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ESP_GOTO_ON_FALSE(phy_r_data->reg_value_p, ESP_ERR_INVALID_ARG, err, TAG, "can't read registers to null");
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ESP_GOTO_ON_ERROR(phy->get_addr(phy, &phy_addr), err, TAG, "get phy address failed");
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ESP_GOTO_ON_ERROR(eth_driver->mediator.phy_reg_read(ð_driver->mediator,
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phy_addr, phy_r_data->reg_addr, phy_r_data->reg_value_p), err, TAG, "failed to read PHY register");
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break;
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case ETH_CMD_WRITE_PHY_REG:
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ESP_GOTO_ON_FALSE(data, ESP_ERR_INVALID_ARG, err, TAG, "invalid register read/write info");
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esp_eth_phy_reg_rw_data_t *phy_w_data = (esp_eth_phy_reg_rw_data_t *)data;
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ESP_GOTO_ON_FALSE(phy_w_data->reg_value_p, ESP_ERR_INVALID_ARG, err, TAG, "can't write registers from null");
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ESP_GOTO_ON_ERROR(phy->get_addr(phy, &phy_addr), err, TAG, "get phy address failed");
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ESP_GOTO_ON_ERROR(eth_driver->mediator.phy_reg_write(ð_driver->mediator,
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phy_addr, phy_w_data->reg_addr, *(phy_w_data->reg_value_p)), err, TAG, "failed to write PHY register");
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break;
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default:
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if (phy->custom_ioctl != NULL && cmd >= ETH_CMD_CUSTOM_PHY_CMDS) {
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@ -6,6 +6,8 @@
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#include <string.h>
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#include <stdlib.h>
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#include <sys/cdefs.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "esp_log.h"
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#include "esp_check.h"
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#include "esp_eth_phy_802_3.h"
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@ -317,6 +319,19 @@ err:
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return ret;
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}
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static esp_err_t lan87xx_set_speed(esp_eth_phy_t *phy, eth_speed_t speed)
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{
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esp_err_t ret = ESP_OK;
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phy_802_3_t *phy_802_3 = esp_eth_phy_into_phy_802_3(phy);
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/* It was observed that a delay needs to be introduced after setting speed and prior driver's start.
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Otherwise, the very first read of PHY registers is not valid data (0xFFFF's). */
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ESP_GOTO_ON_ERROR(esp_eth_phy_802_3_set_speed(phy_802_3, speed), err, TAG, "set speed failed");
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vTaskDelay(pdMS_TO_TICKS(10));
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err:
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return ret;
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}
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static esp_err_t lan87xx_init(esp_eth_phy_t *phy)
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{
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esp_err_t ret = ESP_OK;
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@ -359,6 +374,7 @@ esp_eth_phy_t *esp_eth_phy_new_lan87xx(const eth_phy_config_t *config)
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lan87xx->phy_802_3.parent.get_link = lan87xx_get_link;
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lan87xx->phy_802_3.parent.autonego_ctrl = lan87xx_autonego_ctrl;
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lan87xx->phy_802_3.parent.loopback = lan87xx_loopback;
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lan87xx->phy_802_3.parent.set_speed = lan87xx_set_speed;
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return &lan87xx->phy_802_3.parent;
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err:
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@ -30,10 +30,10 @@ menu "esp_eth TEST_APPS Configuration"
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config TARGET_ETH_PHY_DEVICE_IP101
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bool "IP101"
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config TARGET_ETH_PHY_DEVICE_LAN87XX
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config TARGET_ETH_PHY_DEVICE_LAN8720
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bool "LAN8720"
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config TARGET_ETH_PHY_DEVICE_KSZ80XX
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bool "KSZ80xx"
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config TARGET_ETH_PHY_DEVICE_KSZ8041
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bool "KSZ8041"
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config TARGET_ETH_PHY_DEVICE_RTL8201
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bool "RTL8201"
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config TARGET_ETH_PHY_DEVICE_DP83848
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@ -164,6 +164,23 @@ TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]")
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// set new speed
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TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_S_SPEED, &speed));
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// *** LAN8720 deviation ***
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// Rationale: When the device is in manual 100BASE-TX or 10BASE-T modes with Auto-MDIX enabled, the PHY does not link to a
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// link partner that is configured for auto-negotiation. See LAN8720 errata for more details.
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#ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
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esp_eth_phy_reg_rw_data_t reg;
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uint32_t reg_val;
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reg.reg_addr = 27;
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reg.reg_value_p = ®_val;
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TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®));
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reg_val |= 0x8000;
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TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, ®));
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uint32_t reg_val_act;
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reg.reg_value_p = ®_val_act;
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TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®));
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TEST_ASSERT_EQUAL(reg_val, reg_val_act);
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#endif
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// start the driver and wait for connection establish
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esp_eth_start(eth_handle);
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bits = xEventGroupWaitBits(eth_event_group, ETH_CONNECT_BIT, true, true, pdMS_TO_TICKS(ETH_CONNECT_TIMEOUT_MS));
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@ -242,6 +259,19 @@ TEST_CASE("ethernet io speed/duplex/autonegotiation", "[ethernet]")
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esp_eth_stop(eth_handle);
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auto_nego_en = true;
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esp_eth_ioctl(eth_handle, ETH_CMD_S_AUTONEGO, &auto_nego_en);
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// *** LAN8720 deviation ***
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// Rationale: See above
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#ifdef CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
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reg.reg_value_p = ®_val;
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TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®));
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reg_val &= ~0x8000;
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TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_WRITE_PHY_REG, ®));
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reg.reg_value_p = ®_val_act;
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TEST_ESP_OK(esp_eth_ioctl(eth_handle, ETH_CMD_READ_PHY_REG, ®));
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TEST_ASSERT_EQUAL(reg_val, reg_val_act);
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#endif
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esp_eth_start(eth_handle);
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bits = xEventGroupWaitBits(eth_event_group, ETH_CONNECT_BIT, true, true, pdMS_TO_TICKS(ETH_CONNECT_TIMEOUT_MS));
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TEST_ASSERT((bits & ETH_CONNECT_BIT) == ETH_CONNECT_BIT);
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@ -328,7 +358,7 @@ TEST_CASE("ethernet io loopback", "[ethernet]")
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ESP_LOGI(TAG, "Test with %s Mbps %s duplex.", expected_speed == ETH_SPEED_10M ? "10" : "100", expected_duplex == ETH_DUPLEX_HALF ? "half" : "full");
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// *** KSZ80XX, KSZ8851SNL and DM9051 deviation ***
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// Rationale: do not support loopback at 10 Mbps
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#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_KSZ80XX) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DM9051)
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#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_KSZ8041) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DM9051)
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if ((expected_speed == ETH_SPEED_10M)) {
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, esp_eth_ioctl(eth_handle, ETH_CMD_S_SPEED, &expected_speed));
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continue;
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@ -378,7 +408,7 @@ TEST_CASE("ethernet io loopback", "[ethernet]")
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// *** RTL8201, DP83848 and LAN87xx deviation ***
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// Rationale: do not support autonegotiation with loopback enabled.
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#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_RTL8201) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DP83848) || \
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defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX)
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defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720)
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, esp_eth_ioctl(eth_handle, ETH_CMD_S_AUTONEGO, &auto_nego_en));
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goto cleanup;
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#endif
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@ -397,7 +427,7 @@ TEST_CASE("ethernet io loopback", "[ethernet]")
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TEST_ASSERT((bits & ETH_STOP_BIT) == ETH_STOP_BIT);
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// *** W5500, LAN87xx, RTL8201 and DP83848 deviation ***
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// Rationale: in those cases 'goto cleanup' is used to skip part of the test code. Incasing in #if block is done to prevent unused label error
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#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_W5500) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX) || \
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#if defined(CONFIG_TARGET_ETH_PHY_DEVICE_W5500) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720) || \
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defined(CONFIG_TARGET_ETH_PHY_DEVICE_RTL8201) || defined(CONFIG_TARGET_ETH_PHY_DEVICE_DP83848)
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cleanup:
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#endif
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@ -96,9 +96,9 @@ esp_eth_phy_t *phy_init(eth_phy_config_t *phy_config)
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phy_config->phy_addr = ESP_ETH_PHY_ADDR_AUTO;
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#if CONFIG_TARGET_ETH_PHY_DEVICE_IP101
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phy = esp_eth_phy_new_ip101(phy_config);
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#elif CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX
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#elif CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720
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phy = esp_eth_phy_new_lan87xx(phy_config);
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#elif CONFIG_TARGET_ETH_PHY_DEVICE_KSZ80XX
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#elif CONFIG_TARGET_ETH_PHY_DEVICE_KSZ8041
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phy = esp_eth_phy_new_ksz80xx(phy_config);
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#elif CONFIG_TARGET_ETH_PHY_DEVICE_RTL8201
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phy = esp_eth_phy_new_rtl8201(phy_config);
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@ -6,4 +6,4 @@ CONFIG_ETH_USE_ESP32_EMAC=y
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CONFIG_ESP_TASK_WDT=n
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CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
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CONFIG_TARGET_ETH_PHY_DEVICE_KSZ80XX=y
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CONFIG_TARGET_ETH_PHY_DEVICE_KSZ8041=y
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@ -6,6 +6,6 @@ CONFIG_ETH_USE_ESP32_EMAC=y
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CONFIG_ESP_TASK_WDT_EN=n
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CONFIG_TARGET_USE_INTERNAL_ETHERNET=y
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CONFIG_TARGET_ETH_PHY_DEVICE_LAN87XX=y
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CONFIG_TARGET_ETH_PHY_DEVICE_LAN8720=y
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CONFIG_ETH_RMII_CLK_OUTPUT=y
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CONFIG_ETH_RMII_CLK_OUT_GPIO=17
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