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Merge branch 'refactor/add_alias_name_for_ets_common_api' into 'master' 

esp_rom: extract common ets apis into esp_rom_sys.h

See merge request espressif/esp-idf!9701
pull/5688/head
Ivan Grokhotkov 2020-07-28 15:04:55 +08:00
rodzic a6c1834327 2917651478
commit 16c73edc67
140 zmienionych plików z 490 dodań i 410 usunięć
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5
components/app_trace/app_trace.c
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@ -166,6 +166,7 @@
#include "soc/timer_periph.h"
#include "freertos/FreeRTOS.h"
#include "esp_app_trace.h"
#include "esp_rom_sys.h"
#if CONFIG_APPTRACE_ENABLE
#define ESP_APPTRACE_MAX_VPRINTF_ARGS 256
@ -180,13 +181,13 @@ const static char *TAG = "esp_apptrace";
#define ESP_APPTRACE_LOG( format, ... ) \
do { \
esp_apptrace_log_lock(); \
ets_printf(format, ##__VA_ARGS__); \
esp_rom_printf(format, ##__VA_ARGS__); \
esp_apptrace_log_unlock(); \
} while(0)
#else
#define ESP_APPTRACE_LOG( format, ... ) \
do { \
ets_printf(format, ##__VA_ARGS__); \
esp_rom_printf(format, ##__VA_ARGS__); \
} while(0)
#endif

10
components/app_trace/sys_view/Sample/Config/SEGGER_SYSVIEW_Config_FreeRTOS.c
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@ -61,25 +61,17 @@ File : SEGGER_SYSVIEW_Config_FreeRTOS.c
Purpose : Sample setup configuration of SystemView with FreeRTOS.
Revision: $Rev: 3734 $
*/
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "SEGGER_SYSVIEW.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/clk.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/clk.h"
#endif
#include "esp_app_trace.h"
#include "esp_app_trace_util.h"
#include "esp_intr_alloc.h"
#include "soc/soc.h"
#include "soc/interrupts.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/clk.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/clk.h"
#endif

7
components/app_trace/sys_view/esp32/SEGGER_RTT_esp32.c
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@ -18,14 +18,9 @@
#include "SEGGER_SYSVIEW.h"
#include "SEGGER_SYSVIEW_Conf.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#include "esp_app_trace.h"
#include "esp_log.h"
const static char *TAG = "segger_rtt";
#define SYSVIEW_EVENTS_BUF_SZ 255U

13
components/app_trace/test/test_trace.c
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@ -5,6 +5,7 @@
#include <stdarg.h>
#include "unity.h"
#include "driver/timer.h"
#include "esp_rom_sys.h"
#include "soc/cpu.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
@ -31,7 +32,7 @@ const static char *TAG = "esp_apptrace_test";
else \
ret = xSemaphoreTake(s_print_lock, portMAX_DELAY); \
if (ret == pdTRUE) { \
ets_printf(format, ##__VA_ARGS__); \
esp_rom_printf(format, ##__VA_ARGS__); \
if (xPortInIsrContext()) \
xSemaphoreGiveFromISR(s_print_lock, NULL); \
else \
@ -41,7 +42,7 @@ const static char *TAG = "esp_apptrace_test";
#else
#define ESP_APPTRACE_TEST_LOG( format, ... ) \
do { \
ets_printf(format, ##__VA_ARGS__); \
esp_rom_printf(format, ##__VA_ARGS__); \
} while(0)
#endif
@ -138,7 +139,7 @@ static void esp_apptrace_test_timer_isr(void *arg)
if (res != ESP_OK) {
} else {
if (0) {
ets_printf("tim-%d-%d: Written chunk%d %d bytes, %x\n",
esp_rom_printf("tim-%d-%d: Written chunk%d %d bytes, %x\n",
tim_arg->group, tim_arg->id, tim_arg->data.wr_cnt, tim_arg->data.buf_sz, tim_arg->data.wr_cnt & tim_arg->data.mask);
}
tim_arg->data.wr_err = 0;
@ -161,9 +162,9 @@ static void esp_apptrace_test_timer_isr_crash(void *arg)
memset(tim_arg->data.buf + 2 * sizeof(uint32_t), tim_arg->data.wr_cnt & tim_arg->data.mask, tim_arg->data.buf_sz - 2 * sizeof(uint32_t));
int res = ESP_APPTRACE_TEST_WRITE_FROM_ISR(tim_arg->data.buf, tim_arg->data.buf_sz);
if (res != ESP_OK) {
ets_printf("tim-%d-%d: Failed to write trace %d %x!\n", tim_arg->group, tim_arg->id, res, tim_arg->data.wr_cnt & tim_arg->data.mask);
esp_rom_printf("tim-%d-%d: Failed to write trace %d %x!\n", tim_arg->group, tim_arg->id, res, tim_arg->data.wr_cnt & tim_arg->data.mask);
} else {
ets_printf("tim-%d-%d: Written chunk%d %d bytes, %x\n",
esp_rom_printf("tim-%d-%d: Written chunk%d %d bytes, %x\n",
tim_arg->group, tim_arg->id, tim_arg->data.wr_cnt, tim_arg->data.buf_sz, tim_arg->data.wr_cnt & tim_arg->data.mask);
tim_arg->data.wr_cnt++;
}
@ -404,7 +405,7 @@ static void esp_apptrace_test(esp_apptrace_test_cfg_t *test_cfg)
#if ESP_APPTRACE_TEST_USE_PRINT_LOCK == 1
s_print_lock = xSemaphoreCreateBinary();
if (!s_print_lock) {
ets_printf("%s: Failed to create print lock!", TAG);
esp_rom_printf("%s: Failed to create print lock!", TAG);
return;
}
xSemaphoreGive(s_print_lock);

4
components/bootloader_support/src/bootloader_common.c
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@ -21,10 +21,10 @@
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/ets_sys.h"
#endif
#include "esp_rom_crc.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "esp_flash_partitions.h"
#include "bootloader_flash.h"
#include "bootloader_common.h"
@ -259,7 +259,7 @@ void bootloader_common_vddsdio_configure(void)
cfg.drefl = 3;
cfg.force = 1;
rtc_vddsdio_set_config(cfg);
ets_delay_us(10); // wait for regulator to become stable
esp_rom_delay_us(10); // wait for regulator to become stable
}
#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
}

17
components/bootloader_support/src/bootloader_console.c
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@ -21,21 +21,19 @@
#include "soc/gpio_sig_map.h"
#include "soc/rtc.h"
#include "hal/clk_gate_ll.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_common.h"
#endif
#include "esp_rom_gpio.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#ifdef CONFIG_ESP_CONSOLE_UART_NONE
void bootloader_console_init(void)
{
ets_install_putc1(NULL);
ets_install_putc2(NULL);
esp_rom_install_channel_putc(1, NULL);
esp_rom_install_channel_putc(2, NULL);
}
#endif // CONFIG_ESP_CONSOLE_UART_NONE
@ -44,7 +42,7 @@ void bootloader_console_init(void)
{
const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
ets_install_uart_printf();
esp_rom_install_channel_putc(1, esp_rom_uart_putc);
// Wait for UART FIFO to be empty.
esp_rom_uart_tx_wait_idle(0);
@ -53,8 +51,7 @@ void bootloader_console_init(void)
// Some constants to make the following code less upper-case
const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
// Switch to the new UART (this just changes UART number used for
// ets_printf in ROM code).
// Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
esp_rom_uart_set_as_console(uart_num);
// If console is attached to UART1 or if non-default pins are used,
// need to reconfigure pins using GPIO matrix
@ -96,6 +93,6 @@ void bootloader_console_init(void)
esp_rom_uart_usb_acm_init(s_usb_cdc_buf, sizeof(s_usb_cdc_buf));
esp_rom_uart_set_as_console(ESP_ROM_UART_USB);
ets_install_putc1(bootloader_console_write_char_usb);
esp_rom_install_channel_putc(1, bootloader_console_write_char_usb);
}
#endif //CONFIG_ESP_CONSOLE_USB_CDC

14
components/bootloader_support/src/bootloader_console_loader.c
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@ -13,7 +13,7 @@
// limitations under the License.
/**
* This file is contains console-related functions which should be located in iram_loader_seg,
* This file contains console-related functions which should be located in iram_loader_seg,
* to be available in the "loader" phase, when iram_seg may be overwritten.
*/
#include <stdint.h>
@ -21,10 +21,8 @@
#include "sdkconfig.h"
#include "bootloader_console.h"
#include "esp_rom_uart.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/usb/chip_usb_dw_wrapper.h"
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/cdc_acm.h"
@ -32,7 +30,7 @@
#endif
#ifdef CONFIG_ESP_CONSOLE_USB_CDC
/* The following functions replace ets_write_char_uart, esp_rom_uart_tx_one_char,
/* The following functions replace esp_rom_uart_putc, esp_rom_uart_tx_one_char,
* and uart_tx_one_char_uart ROM functions. The main difference is that
* uart_tx_one_char_uart calls cdc_acm_fifo_fill for each byte passed to it,
* which results in very slow console output. The version here uses a TX buffer.
@ -79,10 +77,10 @@ void bootloader_console_deinit(void)
bootloader_console_flush_usb();
usb_dc_prepare_persist();
chip_usb_set_persist_flags(USBDC_PERSIST_ENA);
ets_delay_us(100);
esp_rom_delay_us(100);
for (int i = 0; i < 10; i++) {
usb_dc_check_poll_for_interrupts();
}
ets_install_putc1(NULL);
esp_rom_install_channel_putc(1, NULL);
#endif
}

5
components/bootloader_support/src/bootloader_utility.c
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@ -19,15 +19,14 @@
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/secure_boot.h"
@ -766,7 +765,7 @@ void bootloader_reset(void)
{
#ifdef BOOTLOADER_BUILD
bootloader_atexit();
ets_delay_us(1000); /* Allow last byte to leave FIFO */
esp_rom_delay_us(1000); /* Allow last byte to leave FIFO */
REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
while (1) { } /* This line will never be reached, used to keep gcc happy */
#else

4
components/bootloader_support/src/esp32/bootloader_esp32.c
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@ -35,9 +35,9 @@
#include "soc/spi_periph.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/ets_sys.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
@ -354,7 +354,7 @@ static void bootloader_check_wdt_reset(void)
void abort(void)
{
#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
ets_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3);
esp_rom_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3);
#endif
if (esp_cpu_in_ocd_debug_mode()) {
__asm__("break 0,0");

3
components/bootloader_support/src/esp32/bootloader_sha.c
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@ -45,7 +45,6 @@ void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data,
size_t word_len = data_len / 4;
uint32_t *sha_text_reg = (uint32_t *)(SHA_TEXT_BASE);
//ets_printf("word_len %d so far %d\n", word_len, words_hashed);
while (word_len > 0) {
size_t block_count = words_hashed % BLOCK_WORDS;
size_t copy_words = (BLOCK_WORDS - block_count);
@ -56,7 +55,6 @@ void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data,
while (REG_READ(SHA_256_BUSY_REG) != 0) { }
// Copy to memory block
//ets_printf("block_count %d copy_words %d\n", block_count, copy_words);
for (int i = 0; i < copy_words; i++) {
sha_text_reg[block_count + i] = __builtin_bswap32(w[i]);
}
@ -70,7 +68,6 @@ void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data,
// If we loaded a full block, run the SHA engine
if (block_count == BLOCK_WORDS) {
//ets_printf("running engine @ count %d\n", words_hashed);
if (words_hashed == BLOCK_WORDS) {
REG_WRITE(SHA_256_START_REG, 1);
} else {

1
components/bootloader_support/src/esp32/secure_boot.c
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@ -19,7 +19,6 @@
#include "esp_log.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/ets_sys.h"
#include "esp_rom_crc.h"
#include "soc/efuse_periph.h"

4
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
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@ -28,8 +28,8 @@
#include "bootloader_mem.h"
#include "bootloader_console.h"
#include "esp_rom_sys.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
@ -279,7 +279,7 @@ static void bootloader_check_wdt_reset(void)
void abort(void)
{
#if !CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT
ets_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3);
esp_rom_printf("abort() was called at PC 0x%08x\r\n", (intptr_t)__builtin_return_address(0) - 3);
#endif
if (esp_cpu_in_ocd_debug_mode()) {
__asm__("break 0,0");

4
components/bt/controller/bt.c
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@ -46,6 +46,8 @@
#include "esp_ipc.h"
#endif
#include "esp_rom_sys.h"
#if CONFIG_BT_ENABLED
/* Macro definition
@ -1433,7 +1435,7 @@ esp_err_t esp_bt_controller_disable(void)
btdm_wakeup_request(false);
}
while (!btdm_power_state_active()) {
ets_delay_us(1000);
esp_rom_delay_us(1000);
}
}

3
components/bt/esp_ble_mesh/mesh_common/include/mesh_trace.h
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@ -11,6 +11,7 @@
#include "esp_log.h"
#include "mesh_util.h"
#include "esp_rom_sys.h"
#ifdef __cplusplus
extern "C" {
@ -65,7 +66,7 @@ extern "C" {
#define BLE_MESH_PRINT_D(tag, format, ...) {esp_log_write(ESP_LOG_DEBUG, tag, LOG_FORMAT(D, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
#define BLE_MESH_PRINT_V(tag, format, ...) {esp_log_write(ESP_LOG_VERBOSE, tag, LOG_FORMAT(V, format), esp_log_timestamp(), tag, ##__VA_ARGS__); }
#define printk ets_printf
#define printk esp_rom_printf
#define _STRINGIFY(x) #x
#define STRINGIFY(s) _STRINGIFY(s)

6
components/driver/esp32/adc.c
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@ -12,9 +12,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include <stdlib.h>
#include <ctype.h>
#include "sdkconfig.h"
#include "esp_types.h"
#include "esp_log.h"
#include "sys/lock.h"
#include "soc/rtc.h"
@ -28,9 +29,6 @@
#include "driver/rtc_cntl.h"
#include "driver/gpio.h"
#include "driver/adc.h"
#include "sdkconfig.h"
#include "esp32/rom/ets_sys.h"
#ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds

6
components/driver/esp32/touch_sensor.c
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@ -12,9 +12,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include <stdlib.h>
#include <ctype.h>
#include "sdkconfig.h"
#include "esp_types.h"
#include "esp_log.h"
#include "sys/lock.h"
#include "soc/rtc.h"
@ -28,9 +29,6 @@
#include "driver/touch_pad.h"
#include "driver/rtc_cntl.h"
#include "driver/gpio.h"
#include "sdkconfig.h"
#include "esp32/rom/ets_sys.h"
#ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds

5
components/driver/esp32s2/adc.c
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@ -12,9 +12,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include <stdlib.h>
#include <ctype.h>
#include "sdkconfig.h"
#include "esp_types.h"
#include "esp_log.h"
#include "sys/lock.h"
#include "freertos/FreeRTOS.h"
@ -27,9 +28,7 @@
#include "driver/rtc_cntl.h"
#include "driver/gpio.h"
#include "driver/adc.h"
#include "sdkconfig.h"
#include "esp32s2/rom/ets_sys.h"
#include "hal/adc_types.h"
#include "hal/adc_hal.h"

3
components/driver/esp32s2/rtc_tempsensor.c
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@ -12,9 +12,9 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include <stdlib.h>
#include <ctype.h>
#include "esp_types.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "esp_log.h"
@ -24,7 +24,6 @@
#include "soc/sens_reg.h"
#include "soc/sens_struct.h"
#include "driver/temp_sensor.h"
#include "esp32s2/rom/ets_sys.h"
static const char *TAG = "tsens";

1
components/driver/esp32s2/touch_sensor.c
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@ -28,7 +28,6 @@
#include "driver/gpio.h"
#include "sdkconfig.h"
#include "esp32s2/rom/ets_sys.h"
#include "hal/touch_sensor_types.h"
#include "hal/touch_sensor_hal.h"

9
components/driver/i2c.c
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@ -31,6 +31,7 @@
#include "driver/i2c.h"
#include "driver/periph_ctrl.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *I2C_TAG = "i2c";
#define I2C_CHECK(a, str, ret) if(!(a)) { \
@ -529,16 +530,16 @@ static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
// a STOP condition.
gpio_set_level(scl_io, 0);
gpio_set_level(sda_io, 1);
ets_delay_us(scl_half_period);
esp_rom_delay_us(scl_half_period);
while (!gpio_get_level(sda_io) && (i++ < I2C_CLR_BUS_SCL_NUM)) {
gpio_set_level(scl_io, 1);
ets_delay_us(scl_half_period);
esp_rom_delay_us(scl_half_period);
gpio_set_level(scl_io, 0);
ets_delay_us(scl_half_period);
esp_rom_delay_us(scl_half_period);
}
gpio_set_level(sda_io, 0); // setup for STOP
gpio_set_level(scl_io, 1);
ets_delay_us(scl_half_period);
esp_rom_delay_us(scl_half_period);
gpio_set_level(sda_io, 1); // STOP, SDA low -> high while SCL is HIGH
i2c_set_pin(i2c_num, sda_io, scl_io, 1, 1, I2C_MODE_MASTER);
#else

3
components/driver/ledc.c
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@ -23,6 +23,7 @@
#include "hal/ledc_hal.h"
#include "driver/ledc.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char* LEDC_TAG = "ledc";
@ -97,7 +98,7 @@ static bool ledc_slow_clk_calibrate(void)
//Enable CLK8M for LEDC
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M);
//Waiting for CLK8M to turn on
ets_delay_us(DELAY_CLK8M_CLK_SWITCH);
esp_rom_delay_us(DELAY_CLK8M_CLK_SWITCH);
uint32_t cal_val = rtc_clk_cal(RTC_CAL_8MD256, SLOW_CLK_CYC_CALIBRATE);
if(cal_val == 0) {
ESP_LOGE(LEDC_TAG, "CLK8M_CLK calibration failed");

9
components/driver/rtc_module.c
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@ -12,9 +12,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include <stdlib.h>
#include <ctype.h>
#include "sdkconfig.h"
#include "esp_types.h"
#include "esp_log.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
@ -28,12 +29,6 @@
#include "esp_intr_alloc.h"
#include "sys/lock.h"
#include "driver/rtc_cntl.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds

3
components/driver/sdmmc_host.c
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@ -20,6 +20,7 @@
#include "soc/gpio_periph.h"
#include "soc/gpio_caps.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
#include "driver/gpio.h"
#include "driver/sdmmc_host.h"
#include "driver/periph_ctrl.h"
@ -96,7 +97,7 @@ static void sdmmc_host_set_clk_div(int div)
SDMMC.clock.phase_din = 4; // 180 degree phase on the input clock
SDMMC.clock.phase_core = 0;
// Wait for the clock to propagate
ets_delay_us(10);
esp_rom_delay_us(10);
}
static void sdmmc_host_input_clk_disable(void)

27
components/driver/spi_slave.c
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@ -35,6 +35,7 @@
#include "driver/gpio.h"
#include "esp_heap_caps.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *SPI_TAG = "spi_slave";
#define SPI_CHECK(a, str, ret_val) \
@ -302,24 +303,24 @@ esp_err_t SPI_SLAVE_ATTR spi_slave_transmit(spi_host_device_t host, spi_slave_tr
#ifdef DEBUG_SLAVE
static void dumpregs(spi_dev_t *hw)
{
ets_printf("***REG DUMP ***\n");
ets_printf("mosi_dlen : %08X\n", hw->mosi_dlen.val);
ets_printf("miso_dlen : %08X\n", hw->miso_dlen.val);
ets_printf("slv_wrbuf_dlen : %08X\n", hw->slv_wrbuf_dlen.val);
ets_printf("slv_rdbuf_dlen : %08X\n", hw->slv_rdbuf_dlen.val);
ets_printf("slave : %08X\n", hw->slave.val);
ets_printf("slv_rdata_bit : %x\n", hw->slv_rd_bit.slv_rdata_bit);
ets_printf("dma_rx_status : %08X\n", hw->dma_rx_status);
ets_printf("dma_tx_status : %08X\n", hw->dma_tx_status);
esp_rom_printf("***REG DUMP ***\n");
esp_rom_printf("mosi_dlen : %08X\n", hw->mosi_dlen.val);
esp_rom_printf("miso_dlen : %08X\n", hw->miso_dlen.val);
esp_rom_printf("slv_wrbuf_dlen : %08X\n", hw->slv_wrbuf_dlen.val);
esp_rom_printf("slv_rdbuf_dlen : %08X\n", hw->slv_rdbuf_dlen.val);
esp_rom_printf("slave : %08X\n", hw->slave.val);
esp_rom_printf("slv_rdata_bit : %x\n", hw->slv_rd_bit.slv_rdata_bit);
esp_rom_printf("dma_rx_status : %08X\n", hw->dma_rx_status);
esp_rom_printf("dma_tx_status : %08X\n", hw->dma_tx_status);
}
static void dumpll(lldesc_t *ll)
{
ets_printf("****LL DUMP****\n");
ets_printf("Size %d\n", ll->size);
ets_printf("Len: %d\n", ll->length);
ets_printf("Owner: %s\n", ll->owner ? "dma" : "cpu");
esp_rom_printf("****LL DUMP****\n");
esp_rom_printf("Size %d\n", ll->size);
esp_rom_printf("Len: %d\n", ll->length);
esp_rom_printf("Owner: %s\n", ll->owner ? "dma" : "cpu");
}
#endif

3
components/driver/test/adc_dma_test/test_esp32.c
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@ -27,6 +27,7 @@
#include "esp_log.h"
#include "nvs_flash.h"
#include "test_utils.h"
#include "esp_rom_sys.h"
#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2) // This testcase for ESP32
@ -118,7 +119,7 @@ TEST_CASE("ADC DMA read", "[adc dma]")
example_disp_buf((uint8_t *) i2s_read_buff, 64);
//save original data from I2S(ADC) into flash.
flash_wr_size += i2s_read_len;
ets_printf("Sound recording %u%%\n", flash_wr_size * 100 / FLASH_RECORD_SIZE);
esp_rom_printf("Sound recording %u%%\n", flash_wr_size * 100 / FLASH_RECORD_SIZE);
}
TEST_ESP_OK( i2s_adc_disable(EXAMPLE_I2S_NUM) );
if (i2s_read_buff) {

19
components/driver/test/adc_dma_test/test_esp32s2.c
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@ -35,6 +35,7 @@
#include "soc/spi_reg.h"
#include "soc/adc_periph.h"
#include "test/test_common_adc.h"
#include "esp_rom_sys.h"
#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2
@ -219,7 +220,7 @@ static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
int unit_old = 1;
int ch_cnt = 0;
for (int cnt = 0; cnt < 2; cnt++) {
ets_printf("\n[%s] link_buf[%d]: \n", __func__, cnt % 2);
esp_rom_printf("\n[%s] link_buf[%d]: \n", __func__, cnt % 2);
for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
uint16_t temp = (h << 8 | l);
@ -228,9 +229,9 @@ static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
if (adc > ADC_UNIT_2) { //ADC_ENCODE_11BIT
#if DEBUG_PRINT_ENABLE
if (i % 16 == 0) {
ets_printf("\n");
esp_rom_printf("\n");
}
ets_printf("[%d_%d_%04x] ", data->type2.unit, data->type2.channel, data->type2.data);
esp_rom_printf("[%d_%d_%04x] ", data->type2.unit, data->type2.channel, data->type2.data);
#endif
#if DEBUG_CHECK_ENABLE
if (ideal_level >= 0) {
@ -256,9 +257,9 @@ static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
} else { //ADC_ENCODE_12BIT
#if DEBUG_PRINT_ENABLE
if (i % 16 == 0) {
ets_printf("\n");
esp_rom_printf("\n");
}
ets_printf("[%d_%04x] ", data->type1.channel, data->type1.data);
esp_rom_printf("[%d_%04x] ", data->type1.channel, data->type1.data);
#endif
#if DEBUG_CHECK_ENABLE
if (ideal_level >= 0) {
@ -279,7 +280,7 @@ static esp_err_t adc_dma_data_check(adc_unit_t adc, int ideal_level)
link_buf[cnt % 2][i] = 0;
link_buf[cnt % 2][i + 1] = 0;
}
ets_printf("\n");
esp_rom_printf("\n");
}
return ESP_OK;
}
@ -580,9 +581,9 @@ static void scope_output(int adc_num, int channel, int data)
#if SCOPE_OUTPUT_UART
static int icnt = 0;
if (icnt++ % 8 == 0) {
ets_printf("\n");
esp_rom_printf("\n");
}
ets_printf("[%d_%d_%04x] ", adc_num, channel, data);
esp_rom_printf("[%d_%d_%04x] ", adc_num, channel, data);
return;
#endif
#if SCOPE_DEBUG_TYPE == 0
@ -632,7 +633,7 @@ TEST_CASE("test_adc_digi_slope_debug", "[adc_dma][ignore]")
dma_linker_restart();
adc_digi_reset();
for (int cnt = 0; cnt < 2; cnt++) {
ets_printf("cnt%d\n", cnt);
esp_rom_printf("cnt%d\n", cnt);
for (int i = 0; i < SAR_DMA_DATA_SIZE((adc > 2) ? 2 : 1, SAR_SIMPLE_NUM); i += 2) {
uint8_t h = link_buf[cnt % 2][i + 1], l = link_buf[cnt % 2][i];
uint16_t temp = (h << 8 | l);

13
components/driver/test/test_gpio.c
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@ -14,6 +14,7 @@
#include "freertos/queue.h"
#include "sdkconfig.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated.
@ -65,7 +66,7 @@ static gpio_config_t init_io(gpio_num_t num)
static void gpio_isr_edge_handler(void* arg)
{
uint32_t gpio_num = (uint32_t) arg;
ets_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
esp_rom_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
edge_intr_times++;
}
@ -74,7 +75,7 @@ static void gpio_isr_level_handler(void* arg)
{
uint32_t gpio_num = (uint32_t) arg;
disable_intr_times++;
ets_printf("GPIO[%d] intr, val: %d, disable_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), disable_intr_times);
esp_rom_printf("GPIO[%d] intr, val: %d, disable_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), disable_intr_times);
gpio_intr_disable(gpio_num);
}
@ -83,14 +84,14 @@ static void gpio_isr_level_handler2(void* arg)
{
uint32_t gpio_num = (uint32_t) arg;
level_intr_times++;
ets_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
esp_rom_printf("GPIO[%d] intr, val: %d\n", gpio_num, gpio_get_level(gpio_num));
if(gpio_get_level(gpio_num)) {
gpio_set_level(TEST_GPIO_EXT_OUT_IO, 0);
}else{
gpio_set_level(TEST_GPIO_EXT_OUT_IO, 1);
}
ets_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", TEST_GPIO_EXT_OUT_IO, gpio_get_level(TEST_GPIO_EXT_OUT_IO), level_intr_times);
ets_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times);
esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", TEST_GPIO_EXT_OUT_IO, gpio_get_level(TEST_GPIO_EXT_OUT_IO), level_intr_times);
esp_rom_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times);
}
#endif
@ -705,7 +706,7 @@ typedef struct {
static void gpio_isr_handler(void* arg)
{
gpio_isr_param_t *param = (gpio_isr_param_t *)arg;
ets_printf("GPIO[%d] intr, val: %d\n", param->gpio_num, gpio_get_level(param->gpio_num));
esp_rom_printf("GPIO[%d] intr, val: %d\n", param->gpio_num, gpio_get_level(param->gpio_num));
param->isr_cnt++;
}

5
components/driver/test/test_spi_sio.c
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@ -8,11 +8,6 @@
#include <malloc.h>
#include <string.h>
#include "sdkconfig.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"

5
components/driver/test/test_timer.c
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@ -7,6 +7,7 @@
#include "nvs_flash.h"
#include "driver/timer.h"
#include "soc/rtc.h"
#include "esp_rom_sys.h"
#define TIMER_DIVIDER 16
#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) /*!< used to calculate counter value */
@ -51,13 +52,13 @@ static bool test_timer_group_isr_cb(void *arg)
alarm_flag = true;
if (timer_group_get_auto_reload_in_isr(timer_group, timer_idx)) { // For autoreload mode, the counter value has been cleared
timer_group_clr_intr_status_in_isr(timer_group, timer_idx);
ets_printf("This is TG%d timer[%d] reload-timer alarm!\n", timer_group, timer_idx);
esp_rom_printf("This is TG%d timer[%d] reload-timer alarm!\n", timer_group, timer_idx);
timer_get_counter_value(timer_group, timer_idx, &timer_val);
timer_get_counter_time_sec(timer_group, timer_idx, &time);
evt.type = TIMER_AUTORELOAD_EN;
} else {
timer_group_clr_intr_status_in_isr(timer_group, timer_idx);
ets_printf("This is TG%d timer[%d] count-up-timer alarm!\n", timer_group, timer_idx);
esp_rom_printf("This is TG%d timer[%d] count-up-timer alarm!\n", timer_group, timer_idx);
timer_get_counter_value(timer_group, timer_idx, &timer_val);
timer_get_counter_time_sec(timer_group, timer_idx, &time);
timer_get_alarm_value(timer_group, timer_idx, &alarm_value);

3
components/driver/test/touch_sensor_test/test_esp32.c
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@ -32,6 +32,7 @@
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_io_reg.h"
#include "soc/rtc_io_struct.h"
#include "esp_rom_sys.h"
#if !DISABLED_FOR_TARGETS(ESP8266, ESP32S2) // This testcase for ESP32
@ -298,7 +299,7 @@ static bool s_pad_activated[TOUCH_PAD_MAX];
static void test_touch_intr_cb(void *arg)
{
uint32_t pad_intr = touch_pad_get_status();
ets_printf("T%x ", pad_intr);
esp_rom_printf("T%x ", pad_intr);
//clear interrupt
touch_pad_clear_status();
for (int i = 0; i < TEST_TOUCH_CHANNEL; i++) {

12
components/driver/test/touch_sensor_test/test_esp32s2.c
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@ -36,6 +36,7 @@
#include "soc/rtc_io_struct.h"
#include "soc/apb_ctrl_reg.h"
#include "driver/rtc_io.h"
#include "esp_rom_sys.h"
#if !DISABLED_FOR_TARGETS(ESP8266, ESP32) // This testcase for ESP32S2
@ -623,7 +624,7 @@ static esp_err_t test_touch_check_ch_touched_with_proximity(uint32_t test_ch_num
if (BIT(i) & ch_mask) {
if (evt.pad_num == i) {
if (count == evt.slp_proxi_cnt) {
ets_printf("priximity base(%d) cnt(%d)\n", evt.slp_proxi_base, evt.slp_proxi_cnt);
esp_rom_printf("priximity base(%d) cnt(%d)\n", evt.slp_proxi_base, evt.slp_proxi_cnt);
}
}
}
@ -665,7 +666,7 @@ static esp_err_t test_touch_check_ch_released_with_proximity(uint32_t test_ch_nu
if (BIT(i) & ch_mask) {
if (evt.pad_num == i) {
if (count == evt.slp_proxi_cnt) {
ets_printf("priximity base(%d) cnt(%d)\n", evt.slp_proxi_base, evt.slp_proxi_cnt);
esp_rom_printf("priximity base(%d) cnt(%d)\n", evt.slp_proxi_base, evt.slp_proxi_cnt);
}
}
}
@ -742,7 +743,7 @@ static esp_err_t test_touch_check_ch_intr_timeout(touch_pad_t pad_num)
touch_pad_timeout_resume();
break;
} else {
ets_printf("-timeout %x T[%d] status %d, evt_msk %x -\n",
esp_rom_printf("-timeout %x T[%d] status %d, evt_msk %x -\n",
s_touch_timeout_mask, evt.pad_num, evt.pad_status, evt.intr_mask);
touch_pad_timeout_resume();
}
@ -768,7 +769,7 @@ static void test_touch_intr_cb(void *arg)
evt.pad_num = touch_pad_get_current_meas_channel();
if (!evt.intr_mask) {
ets_printf(".");
esp_rom_printf(".");
return;
}
if (evt.intr_mask & TOUCH_PAD_INTR_MASK_SCAN_DONE) {
@ -779,11 +780,10 @@ static void test_touch_intr_cb(void *arg)
touch_pad_sleep_channel_read_proximity_cnt(slp_config.touch_num, &cnt);
evt.slp_proxi_cnt = cnt;
evt.slp_proxi_base = touch_value;
// ets_printf("[intr] base(%d) cnt(%d)\n", touch_value, cnt);
}
if (evt.intr_mask & TOUCH_PAD_INTR_MASK_TIMEOUT) {
s_touch_timeout_mask |= (BIT(evt.pad_num));
ets_printf("-%dtout-", SENS.sar_touch_status0.touch_scan_curr);
esp_rom_printf("-%dtout-", SENS.sar_touch_status0.touch_scan_curr);
}
xQueueSendFromISR(que_touch, &evt, &task_awoken);

9
components/driver/touch_sensor_common.c
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@ -12,9 +12,10 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#include <esp_types.h>
#include <stdlib.h>
#include <ctype.h>
#include "sdkconfig.h"
#include "esp_types.h"
#include "esp_log.h"
#include "sys/lock.h"
#include "freertos/FreeRTOS.h"
@ -26,13 +27,7 @@
#include "driver/touch_pad.h"
#include "driver/rtc_cntl.h"
#include "driver/gpio.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#include "hal/touch_sensor_types.h"
#include "hal/touch_sensor_hal.h"

2
components/esp32/cache_err_int.c
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@ -32,7 +32,7 @@
#include "hal/cpu_hal.h"
#include "esp32/dport_access.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/ets_sys.h" // for intr_matrix_set
#include "sdkconfig.h"

2
components/esp32/clk.c
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@ -44,7 +44,7 @@ int IRAM_ATTR esp_clk_xtal_freq(void)
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
{
/* Update scale factors used by ets_delay_us */
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us_pro = ticks_per_us;
#ifndef CONFIG_FREERTOS_UNICORE
g_ticks_per_us_app = ticks_per_us;

2
components/esp32/crosscore_int.c
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@ -19,8 +19,6 @@
#include "esp_intr_alloc.h"
#include "esp_debug_helpers.h"
#include "esp32/rom/ets_sys.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/gpio_periph.h"

1
components/esp32/dport_access.c
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@ -26,7 +26,6 @@
#include "esp_attr.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "esp32/rom/ets_sys.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"

7
components/esp32/sleep_modes.c
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@ -22,6 +22,7 @@
#include "esp32/clk.h"
#include "esp_newlib.h"
#include "esp_spi_flash.h"
#include "esp_rom_sys.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
#include "esp_rom_uart.h"
@ -132,11 +133,11 @@ void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void) {
_DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR));
#if CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0
// ROM code has not started yet, so we need to set delay factor
// used by ets_delay_us first.
// used by esp_rom_delay_us first.
ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000);
// This delay is configured in menuconfig, it can be used to give
// the flash chip some time to become ready.
ets_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY);
esp_rom_delay_us(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY);
#endif
}
@ -280,7 +281,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
// If SPI flash was powered down, wait for it to become ready
if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
// Wait for the flash chip to start up
ets_delay_us(flash_enable_time_us);
esp_rom_delay_us(flash_enable_time_us);
}
return err;
}

6
components/esp32/test/test_backtrace.c
Wyświetl plik

@ -9,6 +9,8 @@
#include "freertos/task.h"
#include "freertos/xtensa_api.h"
#include "esp_intr_alloc.h"
#include "esp_rom_sys.h"
#include "esp_rom_uart.h"
#define SW_ISR_LEVEL_1 7
#define SW_ISR_LEVEL_3 29
@ -72,12 +74,12 @@ TEST_CASE("Test backtrace from interrupt watchdog timeout", "[reset_reason][rese
static void write_char_crash(char c)
{
ets_write_char_uart(c);
esp_rom_uart_putc(c);
*(char*) 0x00000001 = 0;
}
TEST_CASE("Test backtrace with a ROM function", "[reset_reason][reset=StoreProhibited,SW_CPU_RESET]")
{
ets_install_putc1(&write_char_crash);
ets_printf("foo");
esp_rom_printf("foo");
}

4
components/esp32/test/test_delay.c
Wyświetl plik

@ -3,7 +3,7 @@
#include <time.h>
#include <sys/time.h>
#include "unity.h"
#include "esp32/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -23,7 +23,7 @@ static void test_delay_task(void* p)
uint64_t start = ref_clock_get();
switch (arg->method) {
case 0:
ets_delay_us(arg->delay_us);
esp_rom_delay_us(arg->delay_us);
break;
case 1:
vTaskDelay(arg->delay_us / portTICK_PERIOD_MS / 1000);

3
components/esp32/test/test_fastbus.c
Wyświetl plik

@ -1,8 +1,7 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "esp_types.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"

7
components/esp32/test/test_intr_alloc.c
Wyświetl plik

@ -4,7 +4,7 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -69,7 +69,6 @@ static void timer_isr(void *arg)
timer_group_clr_intr_status_in_isr(TIMER_GROUP_1, TIMER_1);
timer_group_enable_alarm_in_isr(TIMER_GROUP_1, TIMER_1);
}
// ets_printf("int %d\n", timer_idx);
}
@ -237,7 +236,7 @@ typedef struct {
void IRAM_ATTR int_handler1(void* arg)
{
intr_alloc_test_ctx_t* ctx=(intr_alloc_test_ctx_t*)arg;
ets_printf("handler 1 called.\n");
esp_rom_printf("handler 1 called.\n");
if ( ctx->flag1 ) {
ctx->flag3 = true;
} else {
@ -249,7 +248,7 @@ void IRAM_ATTR int_handler1(void* arg)
void IRAM_ATTR int_handler2(void* arg)
{
intr_alloc_test_ctx_t* ctx = (intr_alloc_test_ctx_t*)arg;
ets_printf("handler 2 called.\n");
esp_rom_printf("handler 2 called.\n");
if ( ctx->flag2 ) {
ctx->flag4 = true;
} else {

3
components/esp32/test/test_pm.c
Wyświetl plik

@ -14,6 +14,7 @@
#include "driver/rtc_io.h"
#include "esp32/ulp.h"
#include "soc/rtc_periph.h"
#include "esp_rom_sys.h"
#define MHZ 1000000
@ -271,7 +272,7 @@ TEST_CASE("esp_timer produces correct delays with light sleep", "[pm]")
p_args->intervals[p_args->cur_interval++] = ms_diff;
// Deliberately make timer handler run longer.
// We check that this doesn't affect the result.
ets_delay_us(10*1000);
esp_rom_delay_us(10*1000);
if (p_args->cur_interval == NUM_INTERVALS) {
printf("done\n");
TEST_ESP_OK(esp_timer_stop(p_args->timer));

3
components/esp32/test/test_sleep.c
Wyświetl plik

@ -18,6 +18,7 @@
#include "esp_newlib.h"
#include "test_utils.h"
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#define ESP_EXT0_WAKEUP_LEVEL_LOW 0
@ -101,7 +102,7 @@ TEST_CASE("light sleep stress test with periodic esp_timer", "[deepsleep]")
{
void timer_func(void* arg)
{
ets_delay_us(50);
esp_rom_delay_us(50);
}
SemaphoreHandle_t done = xSemaphoreCreateCounting(2, 0);

2
components/esp32/test/test_spiram_cache_flush.c
Wyświetl plik

@ -4,7 +4,6 @@ This code tests the interaction between PSRAM and SPI flash routines.
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -15,7 +14,6 @@ This code tests the interaction between PSRAM and SPI flash routines.
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "esp32/rom/ets_sys.h"
#include "esp_heap_caps.h"
#include "esp_spi_flash.h"
#include "esp_partition.h"

6
components/esp32/test/test_tsens.c
Wyświetl plik

@ -1,6 +1,6 @@
#include <stdio.h>
#include "unity.h"
#include "esp32/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "soc/rtc_periph.h"
#include "soc/sens_periph.h"
@ -12,9 +12,9 @@ TEST_CASE("can control TSENS using registers", "[rtc][ignore]")
CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
ets_delay_us(100);
esp_rom_delay_us(100);
SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
ets_delay_us(5);
esp_rom_delay_us(5);
int res = GET_PERI_REG_BITS2(SENS_SAR_SLAVE_ADDR3_REG, SENS_TSENS_OUT, SENS_TSENS_OUT_S);
printf("res=%d\n", res);
}

2
components/esp32s2/cache_err_int.c
Wyświetl plik

@ -35,7 +35,7 @@
#include "hal/cpu_hal.h"
#include "esp32s2/dport_access.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/ets_sys.h" // for intr_matrix_set
#include "sdkconfig.h"

2
components/esp32s2/clk.c
Wyświetl plik

@ -41,6 +41,6 @@ int IRAM_ATTR esp_clk_xtal_freq(void)
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
{
/* Update scale factors used by ets_delay_us */
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us_pro = ticks_per_us;
}

2
components/esp32s2/crosscore_int.c
Wyświetl plik

@ -19,8 +19,6 @@
#include "esp_intr_alloc.h"
#include "esp_debug_helpers.h"
#include "esp32s2/rom/ets_sys.h"
#include "soc/cpu.h"
#include "soc/dport_reg.h"
#include "soc/io_mux_reg.h"

3
components/esp32s2/esp_hmac.c
Wyświetl plik

@ -13,7 +13,6 @@
// limitations under the License.
#include "esp32s2/rom/hmac.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp_hmac.h"
#include "esp_crypto_lock.h"
@ -38,7 +37,7 @@ esp_err_t esp_hmac_calculate(hmac_key_id_t key_id,
esp_crypto_dma_lock_release();
if (hmac_ret != ETS_OK) {
if (hmac_ret != 0) {
return ESP_FAIL;
} else {
return ESP_OK;

4
components/esp32s2/sleep_modes.c
Wyświetl plik

@ -24,8 +24,8 @@
#include "esp_spi_flash.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "soc/cpu.h"
#include "soc/rtc.h"
#include "soc/spi_periph.h"
@ -286,7 +286,7 @@ static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
// If SPI flash was powered down, wait for it to become ready
if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
// Wait for the flash chip to start up
ets_delay_us(flash_enable_time_us);
esp_rom_delay_us(flash_enable_time_us);
}
return err;
}

1
components/esp32s2/spiram_psram.c
Wyświetl plik

@ -24,7 +24,6 @@
#include "esp_types.h"
#include "esp_log.h"
#include "spiram_psram.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/opi_flash.h"
#include "esp32s2/rom/cache.h"

4
components/esp32s2/test/test_delay.c
Wyświetl plik

@ -2,7 +2,7 @@
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include "esp32s2/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -23,7 +23,7 @@ static void test_delay_task(void *p)
uint64_t start = ref_clock_get();
switch (arg->method) {
case 0:
ets_delay_us(arg->delay_us);
esp_rom_delay_us(arg->delay_us);
break;
case 1:
vTaskDelay(arg->delay_us / portTICK_PERIOD_MS / 1000);

6
components/esp32s2/test/test_intr_alloc.c
Wyświetl plik

@ -5,7 +5,7 @@
#include <stdio.h>
#include "unity.h"
#include "esp_types.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp_rom_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@ -234,7 +234,7 @@ typedef struct {
void IRAM_ATTR int_handler1(void *arg)
{
intr_alloc_test_ctx_t *ctx = (intr_alloc_test_ctx_t *)arg;
ets_printf("handler 1 called.\n");
esp_rom_printf("handler 1 called.\n");
if (ctx->flag1) {
ctx->flag3 = true;
} else {
@ -246,7 +246,7 @@ void IRAM_ATTR int_handler1(void *arg)
void IRAM_ATTR int_handler2(void *arg)
{
intr_alloc_test_ctx_t *ctx = (intr_alloc_test_ctx_t *)arg;
ets_printf("handler 2 called.\n");
esp_rom_printf("handler 2 called.\n");
if (ctx->flag2) {
ctx->flag4 = true;
} else {

6
components/esp_common/Kconfig
Wyświetl plik

@ -105,7 +105,7 @@ menu "Common ESP-related"
is reconfigured after the bootloader exits and the app starts.
Due to an ESP32 ROM bug, UART2 is not supported for console output
via ets_printf.
via esp_rom_printf.
config ESP_CONSOLE_UART_CUSTOM_NUM_0
bool "UART0"
@ -179,11 +179,11 @@ menu "Common ESP-related"
is often receiving data over USB CDC.
config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
bool "Enable ets_printf / ESP_EARLY_LOG via USB CDC"
bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC"
depends on ESP_CONSOLE_USB_CDC
default n
help
If enabled, ets_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC.
Disabling this option saves about 1kB or RAM.
config ESP_INT_WDT

7
components/esp_common/include/esp_fault.h
Wyświetl plik

@ -13,6 +13,7 @@
// limitations under the License.
#include "sdkconfig.h"
#include "soc/rtc_cntl_reg.h"
#include "esp_rom_sys.h"
#pragma once
@ -81,9 +82,9 @@ extern "C" {
#warning "Enabling ESP_FAULT_ASSERT_DEBUG makes ESP_FAULT_ASSERT() less effective"
#define _ESP_FAULT_RESET() do { \
ets_printf("ESP_FAULT_ASSERT %s:%d\n", __FILE__, __LINE__); \
asm volatile("ill;"); \
#define _ESP_FAULT_RESET() do { \
esp_rom_printf("ESP_FAULT_ASSERT %s:%d\n", __FILE__, __LINE__); \
asm volatile("ill;"); \
} while(0)
#endif // ESP_FAULT_ASSERT_DEBUG

5
components/esp_common/src/brownout.c
Wyświetl plik

@ -25,6 +25,7 @@
#include "esp_private/system_internal.h"
#include "driver/rtc_cntl.h"
#include "freertos/FreeRTOS.h"
#include "esp_rom_sys.h"
#if defined(CONFIG_ESP32_BROWNOUT_DET_LVL)
#define BROWNOUT_DET_LVL CONFIG_ESP32_BROWNOUT_DET_LVL
@ -49,11 +50,11 @@ static void rtc_brownout_isr_handler(void *arg)
*/
brownout_hal_intr_clear();
/* Stall the other CPU to make sure the code running there doesn't use UART
* at the same time as the following ets_printf.
* at the same time as the following esp_rom_printf.
*/
esp_cpu_stall(!xPortGetCoreID());
esp_reset_reason_set_hint(ESP_RST_BROWNOUT);
ets_printf("\r\nBrownout detector was triggered\r\n\r\n");
esp_rom_printf("\r\nBrownout detector was triggered\r\n\r\n");
esp_restart_noos();
}

14
components/esp_common/src/esp_err.c
Wyświetl plik

@ -17,21 +17,17 @@
#include "esp_err.h"
#include "esp_spi_flash.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
#include "esp_rom_sys.h"
static void esp_error_check_failed_print(const char *msg, esp_err_t rc, const char *file, int line, const char *function, const char *expression)
{
ets_printf("%s failed: esp_err_t 0x%x", msg, rc);
esp_rom_printf("%s failed: esp_err_t 0x%x", msg, rc);
#ifdef CONFIG_ESP_ERR_TO_NAME_LOOKUP
ets_printf(" (%s)", esp_err_to_name(rc));
esp_rom_printf(" (%s)", esp_err_to_name(rc));
#endif //CONFIG_ESP_ERR_TO_NAME_LOOKUP
ets_printf(" at 0x%08x\n", (intptr_t)__builtin_return_address(0) - 3);
esp_rom_printf(" at 0x%08x\n", (intptr_t)__builtin_return_address(0) - 3);
if (spi_flash_cache_enabled()) { // strings may be in flash cache
ets_printf("file: \"%s\" line %d\nfunc: %s\nexpression: %s\n", file, line, function, expression);
esp_rom_printf("file: \"%s\" line %d\nfunc: %s\nexpression: %s\n", file, line, function, expression);
}
}

3
components/esp_common/src/stack_check.c
Wyświetl plik

@ -14,6 +14,7 @@
#include "sdkconfig.h"
#include "esp_system.h"
#include "esp_rom_sys.h"
#if CONFIG_COMPILER_STACK_CHECK
@ -32,7 +33,7 @@ __esp_stack_guard_setup (void)
void __stack_chk_fail (void)
{
ets_printf("\r\nStack smashing protect failure!\r\n\r\n");
esp_rom_printf("\r\nStack smashing protect failure!\r\n\r\n");
abort();
}

7
components/esp_eth/src/esp_eth_mac_dm9051.c
Wyświetl plik

@ -29,6 +29,7 @@
#include "dm9051.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "emac_dm9051";
#define MAC_CHECK(a, str, goto_tag, ret_value, ...) \
@ -450,7 +451,7 @@ static esp_err_t emac_dm9051_write_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr
/* polling the busy flag */
uint32_t to = 0;
do {
ets_delay_us(100);
esp_rom_delay_us(100);
MAC_CHECK(dm9051_register_read(emac, DM9051_EPCR, &epcr) == ESP_OK, "read EPCR failed", err, ESP_FAIL);
to += 100;
} while ((epcr & EPCR_ERRE) && to < DM9051_PHY_OPERATION_TIMEOUT_US);
@ -476,7 +477,7 @@ static esp_err_t emac_dm9051_read_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr,
/* polling the busy flag */
uint32_t to = 0;
do {
ets_delay_us(100);
esp_rom_delay_us(100);
MAC_CHECK(dm9051_register_read(emac, DM9051_EPCR, &epcr) == ESP_OK, "read EPCR failed", err, ESP_FAIL);
to += 100;
} while ((epcr & EPCR_ERRE) && to < DM9051_PHY_OPERATION_TIMEOUT_US);
@ -641,7 +642,7 @@ static esp_err_t emac_dm9051_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t
/* reset rx fifo pointer */
MAC_CHECK(dm9051_register_write(emac, DM9051_MPTRCR, MPTRCR_RST_RX) == ESP_OK,
"write MPTRCR failed", err, ESP_FAIL);
ets_delay_us(10);
esp_rom_delay_us(10);
MAC_CHECK(mac->start(mac) == ESP_OK, "start dm9051 failed", err, ESP_FAIL);
MAC_CHECK(false, "reset rx fifo pointer", err, ESP_FAIL);
} else if (rxbyte) {

5
components/esp_eth/src/esp_eth_mac_esp32.c
Wyświetl plik

@ -31,6 +31,7 @@
#include "soc/soc.h"
#include "sdkconfig.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "emac_esp32";
#define MAC_CHECK(a, str, goto_tag, ret_value, ...) \
@ -87,7 +88,7 @@ static esp_err_t emac_esp32_write_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr,
uint32_t to = 0;
bool busy = true;
do {
ets_delay_us(100);
esp_rom_delay_us(100);
busy = emac_hal_is_mii_busy(&emac->hal);
to += 100;
} while (busy && to < PHY_OPERATION_TIMEOUT_US);
@ -108,7 +109,7 @@ static esp_err_t emac_esp32_read_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr,
uint32_t to = 0;
bool busy = true;
do {
ets_delay_us(100);
esp_rom_delay_us(100);
busy = emac_hal_is_mii_busy(&emac->hal);
to += 100;
} while (busy && to < PHY_OPERATION_TIMEOUT_US);

3
components/esp_eth/src/esp_eth_phy_dm9051.c
Wyświetl plik

@ -21,6 +21,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "dm9051";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -193,7 +194,7 @@ static esp_err_t dm9051_reset_hw(esp_eth_phy_t *phy)
esp_rom_gpio_pad_select_gpio(dm9051->reset_gpio_num);
gpio_set_direction(dm9051->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(dm9051->reset_gpio_num, 0);
ets_delay_us(100); // insert min input assert time
esp_rom_delay_us(100); // insert min input assert time
gpio_set_level(dm9051->reset_gpio_num, 1);
}
return ESP_OK;

3
components/esp_eth/src/esp_eth_phy_dp83848.c
Wyświetl plik

@ -21,6 +21,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "dp83848";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -182,7 +183,7 @@ static esp_err_t dp83848_reset_hw(esp_eth_phy_t *phy)
esp_rom_gpio_pad_select_gpio(dp83848->reset_gpio_num);
gpio_set_direction(dp83848->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(dp83848->reset_gpio_num, 0);
ets_delay_us(100); // insert min input assert time
esp_rom_delay_us(100); // insert min input assert time
gpio_set_level(dp83848->reset_gpio_num, 1);
}
return ESP_OK;

3
components/esp_eth/src/esp_eth_phy_ip101.c
Wyświetl plik

@ -21,6 +21,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "ip101";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -222,7 +223,7 @@ static esp_err_t ip101_reset_hw(esp_eth_phy_t *phy)
esp_rom_gpio_pad_select_gpio(ip101->reset_gpio_num);
gpio_set_direction(ip101->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(ip101->reset_gpio_num, 0);
ets_delay_us(100); // insert min input assert time
esp_rom_delay_us(100); // insert min input assert time
gpio_set_level(ip101->reset_gpio_num, 1);
}
return ESP_OK;

3
components/esp_eth/src/esp_eth_phy_ksz8041.c
Wyświetl plik

@ -21,6 +21,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "ksz8041";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -170,7 +171,7 @@ static esp_err_t ksz8041_reset_hw(esp_eth_phy_t *phy)
esp_rom_gpio_pad_select_gpio(ksz8041->reset_gpio_num);
gpio_set_direction(ksz8041->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(ksz8041->reset_gpio_num, 0);
ets_delay_us(100); // insert min input assert time
esp_rom_delay_us(100); // insert min input assert time
gpio_set_level(ksz8041->reset_gpio_num, 1);
}
return ESP_OK;

3
components/esp_eth/src/esp_eth_phy_lan8720.c
Wyświetl plik

@ -21,6 +21,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "lan8720";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -267,7 +268,7 @@ static esp_err_t lan8720_reset_hw(esp_eth_phy_t *phy)
esp_rom_gpio_pad_select_gpio(lan8720->reset_gpio_num);
gpio_set_direction(lan8720->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(lan8720->reset_gpio_num, 0);
ets_delay_us(100); // insert min input assert time
esp_rom_delay_us(100); // insert min input assert time
gpio_set_level(lan8720->reset_gpio_num, 1);
}
return ESP_OK;

3
components/esp_eth/src/esp_eth_phy_rtl8201.c
Wyświetl plik

@ -22,6 +22,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"
static const char *TAG = "rtl8201";
#define PHY_CHECK(a, str, goto_tag, ...) \
@ -176,7 +177,7 @@ static esp_err_t rtl8201_reset_hw(esp_eth_phy_t *phy)
esp_rom_gpio_pad_select_gpio(rtl8201->reset_gpio_num);
gpio_set_direction(rtl8201->reset_gpio_num, GPIO_MODE_OUTPUT);
gpio_set_level(rtl8201->reset_gpio_num, 0);
ets_delay_us(100); // insert min input assert time
esp_rom_delay_us(100); // insert min input assert time
gpio_set_level(rtl8201->reset_gpio_num, 1);
}
return ESP_OK;

11
components/esp_ipc/test/test_ipc.c
Wyświetl plik

@ -8,6 +8,7 @@
#include "esp_ipc.h"
#endif
#include "esp_log.h"
#include "esp_rom_sys.h"
#if !CONFIG_FREERTOS_UNICORE
static void test_func_ipc_cb(void *arg)
@ -30,7 +31,7 @@ static volatile bool exit_flag;
static void task1(void *sema)
{
ESP_LOGI("task1", "start");
ets_delay_us(3000000);
esp_rom_delay_us(3000000);
vTaskDelay(1);
while (exit_flag == false) {
@ -43,10 +44,10 @@ static UBaseType_t func_ipc_priority;
static void test_func_ipc(void *sema)
{
ets_delay_us(1000000 + xPortGetCoreID() * 100);
esp_rom_delay_us(1000000 + xPortGetCoreID() * 100);
func_ipc_priority = uxTaskPriorityGet(NULL);
xSemaphoreGive(*(xSemaphoreHandle *)sema);
ets_printf("test_func_ipc: [%d, %d]\n", func_ipc_priority, xPortGetCoreID());
esp_rom_printf("test_func_ipc: [%d, %d]\n", func_ipc_priority, xPortGetCoreID());
}
TEST_CASE("Test ipc_task works with the priority of the caller's task", "[ipc]")
@ -77,9 +78,9 @@ TEST_CASE("Test ipc_task works with the priority of the caller's task", "[ipc]")
static void test_func2_ipc(void *arg)
{
int callers_priority = *(int *)arg;
ets_delay_us(1000000 + xPortGetCoreID() * 100);
esp_rom_delay_us(1000000 + xPortGetCoreID() * 100);
UBaseType_t priority = uxTaskPriorityGet(NULL);
ets_printf("test_func2_ipc: [callers_priority = %d, priority = %d, cpu = %d]\n", callers_priority, priority, xPortGetCoreID());
esp_rom_printf("test_func2_ipc: [callers_priority = %d, priority = %d, cpu = %d]\n", callers_priority, priority, xPortGetCoreID());
}
static void task(void *sema)

7
components/esp_ringbuf/test/test_ringbuf.c
Wyświetl plik

@ -10,6 +10,7 @@
#include "esp_spi_flash.h"
#include "unity.h"
#include "test_utils.h"
#include "esp_rom_sys.h"
//Definitions used in multiple test cases
#define TIMEOUT_TICKS 10
@ -572,7 +573,7 @@ static void rec_task(void *args)
static void setup(void)
{
ets_printf("Size of test data: %d\n", CONT_DATA_LEN);
esp_rom_printf("Size of test data: %d\n", CONT_DATA_LEN);
tx_done = xSemaphoreCreateBinary(); //Semaphore to indicate send is done for a particular iteration
rx_done = xSemaphoreCreateBinary(); //Semaphore to indicate receive is done for a particular iteration
tasks_done = xSemaphoreCreateBinary(); //Semaphore used to to indicate send and receive tasks completed running
@ -602,7 +603,7 @@ TEST_CASE("Test ring buffer SMP", "[esp_ringbuf]")
//Test every permutation of core affinity
for (int send_core = 0; send_core < portNUM_PROCESSORS; send_core++) {
for (int rec_core = 0; rec_core < portNUM_PROCESSORS; rec_core ++) {
ets_printf("Type: %d, PM: %d, SC: %d, RC: %d\n", buf_type, prior_mod, send_core, rec_core);
esp_rom_printf("Type: %d, PM: %d, SC: %d, RC: %d\n", buf_type, prior_mod, send_core, rec_core);
xTaskCreatePinnedToCore(send_task, "send tsk", 2048, (void *)&task_args, 10 + prior_mod, NULL, send_core);
xTaskCreatePinnedToCore(rec_task, "rec tsk", 2048, (void *)&task_args, 10, NULL, rec_core);
xSemaphoreTake(tasks_done, portMAX_DELAY);
@ -646,7 +647,7 @@ TEST_CASE("Test static ring buffer SMP", "[esp_ringbuf]")
//Test every permutation of core affinity
for (int send_core = 0; send_core < portNUM_PROCESSORS; send_core++) {
for (int rec_core = 0; rec_core < portNUM_PROCESSORS; rec_core ++) {
ets_printf("Type: %d, PM: %d, SC: %d, RC: %d\n", buf_type, prior_mod, send_core, rec_core);
esp_rom_printf("Type: %d, PM: %d, SC: %d, RC: %d\n", buf_type, prior_mod, send_core, rec_core);
xTaskCreatePinnedToCore(send_task, "send tsk", 2048, (void *)&task_args, 10 + prior_mod, NULL, send_core);
xTaskCreatePinnedToCore(rec_task, "rec tsk", 2048, (void *)&task_args, 10, NULL, rec_core);
xSemaphoreTake(tasks_done, portMAX_DELAY);

2
components/esp_rom/CMakeLists.txt
Wyświetl plik

@ -1,6 +1,6 @@
idf_build_get_property(target IDF_TARGET)
idf_component_register(SRCS "patches/esp_rom_crc.c" "patches/esp_rom_uart.c"
idf_component_register(SRCS "patches/esp_rom_crc.c" "patches/esp_rom_sys.c" "patches/esp_rom_uart.c"
INCLUDE_DIRS include
PRIV_INCLUDE_DIRS "${target}"
PRIV_REQUIRES soc)

4
components/esp_rom/esp32/ld/esp32.rom.api.ld
Wyświetl plik

@ -26,9 +26,13 @@ PROVIDE ( esp_rom_uart_tx_wait_idle = uart_tx_wait_idle );
PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */
/* so here we directly assign the symbols with the ROM API address */
PROVIDE ( esp_rom_md5_init = 0x4005da7c );
PROVIDE ( esp_rom_md5_update = 0x4005da9c );
PROVIDE ( esp_rom_md5_final = 0x4005db1c );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );

4
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
Wyświetl plik

@ -25,9 +25,13 @@ PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */
/* so here we directly assign the symbols with the ROM API address */
PROVIDE ( esp_rom_md5_init = 0x4000526c );
PROVIDE ( esp_rom_md5_update = 0x4000528c );
PROVIDE ( esp_rom_md5_final = 0x4000530c );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );

4
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
Wyświetl plik

@ -28,9 +28,13 @@ PROVIDE ( esp_rom_uart_rx_one_char = uart_rx_one_char );
PROVIDE ( esp_rom_uart_rx_string = UartRxString );
PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
PROVIDE ( esp_rom_uart_usb_acm_init = Uart_Init_USB );
PROVIDE ( esp_rom_uart_putc = ets_write_char_uart );
/* wpa_supplicant re-implements the MD5 functions: MD5Init, MD5Update, MD5Final */
/* so here we directly assign the symbols with the ROM API address */
PROVIDE ( esp_rom_md5_init = 0x400376a0 );
PROVIDE ( esp_rom_md5_update = 0x400376c0 );
PROVIDE ( esp_rom_md5_final = 0x40037740 );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );

8
components/esp_rom/include/esp32s2/rom/cache.h
Wyświetl plik

@ -50,10 +50,10 @@ typedef enum {
typedef enum {
CACHE_MEMORY_INVALID = 0,
CACHE_MEMORY_ICACHE_LOW = BIT(0),
CACHE_MEMORY_ICACHE_HIGH = BIT(1),
CACHE_MEMORY_DCACHE_LOW = BIT(2),
CACHE_MEMORY_DCACHE_HIGH = BIT(3),
CACHE_MEMORY_ICACHE_LOW = 1<<0,
CACHE_MEMORY_ICACHE_HIGH = 1<<1,
CACHE_MEMORY_DCACHE_LOW = 1<<2,
CACHE_MEMORY_DCACHE_HIGH = 1<<3,
} cache_layout_t;
#define CACHE_SIZE_8KB CACHE_SIZE_HALF

1
components/esp_rom/include/esp_rom_gpio.h
Wyświetl plik

@ -20,7 +20,6 @@ extern "C" {
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
/**
* @brief Configure IO Pad as General Purpose IO,

51
components/esp_rom/include/esp_rom_sys.h 100644
Wyświetl plik

@ -0,0 +1,51 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @brief Print formated string to console device
* @note float and long long data are not supported!
*
* @param fmt Format string
* @param ... Additional arguments, depending on the format string
* @return int: Total number of characters written on success; A negative number on failure.
*/
int esp_rom_printf(const char *fmt, ...);
/**
* @brief Pauses execution for us microseconds
*
* @param us Number of microseconds to pause
*/
void esp_rom_delay_us(uint32_t us);
/**
* @brief esp_rom_printf can print message to different channels simultaneously.
* This function can help install the low level putc function for esp_rom_printf.
*
* @param channel Channel number (startting from 1)
* @param putc Function pointer to the putc implementation. Set NULL can disconnect esp_rom_printf with putc.
*/
void esp_rom_install_channel_putc(int channel, void (*putc)(char c));
#ifdef __cplusplus
}
#endif

8
components/esp_rom/include/esp_rom_uart.h
Wyświetl plik

@ -61,6 +61,14 @@ void esp_rom_uart_flush_tx(uint8_t uart_no);
*/
int esp_rom_uart_tx_one_char(uint8_t c);
/**
* @brief Transmit one character to the console channel.
* @note This function is a wrapper over esp_rom_uart_tx_one_char, it can help handle line ending issue by replacing '\n' with '\r\n'.
*
* @param c Character to send
*/
void esp_rom_uart_putc(char c);
/**
* @brief Get one character from the console channel.
*

32
components/esp_rom/patches/esp_rom_sys.c 100644
Wyświetl plik

@ -0,0 +1,32 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <stdint.h>
#include "esp_attr.h"
IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
{
extern void ets_install_putc1(void (*p)(char c));
extern void ets_install_putc2(void (*p)(char c));
switch (channel) {
case 1:
ets_install_putc1(putc);
break;
case 2:
ets_install_putc2(putc);
break;
default:
break;
}
}

9
components/esp_system/port/cpu_start.c
Wyświetl plik

@ -26,6 +26,7 @@
#include "esp_clk_internal.h"
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
@ -33,12 +34,10 @@
#include "esp32/rom/cache.h"
#include "esp32/rom/rtc.h"
#include "esp32/spiram.h"
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/brownout.h"
#include "esp32s2/cache_err_int.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/rtc.h"
#include "esp32s2/spiram.h"
#include "soc/periph_defs.h"
@ -139,7 +138,7 @@ void IRAM_ATTR call_start_cpu1(void)
s_cpu_inited[1] = true;
while (!s_resume_cores) {
ets_delay_us(100);
esp_rom_delay_us(100);
}
SYS_STARTUP_FN();
@ -175,7 +174,7 @@ static void start_other_core(void)
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
cpus_up &= s_cpu_up[i];
}
ets_delay_us(100);
esp_rom_delay_us(100);
}
}
}
@ -408,7 +407,7 @@ void IRAM_ATTR call_start_cpu0(void)
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
cpus_inited &= s_cpu_inited[i];
}
ets_delay_us(100);
esp_rom_delay_us(100);
}
#endif

1
components/esp_system/port/esp32s2/clk.c
Wyświetl plik

@ -22,7 +22,6 @@
#include "esp_log.h"
#include "esp32s2/clk.h"
#include "esp_clk_internal.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/rtc.h"
#include "esp_rom_uart.h"
#include "soc/system_reg.h"

11
components/esp_system/port/esp32s2/usb_console.c
Wyświetl plik

@ -30,6 +30,7 @@
#include "soc/spinlock.h"
#include "hal/soc_hal.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp32s2/rom/usb/usb_dc.h"
#include "esp32s2/rom/usb/cdc_acm.h"
#include "esp32s2/rom/usb/usb_dfu.h"
@ -69,7 +70,7 @@ void esp_usb_console_write_char(char c);
#endif // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Optional write lock routines; used only if ets_printf output via CDC is enabled */
/* Optional write lock routines; used only if esp_rom_printf output via CDC is enabled */
static inline void write_lock_acquire(void);
static inline void write_lock_release(void);
@ -103,7 +104,7 @@ int esp_usb_console_osglue_wait_proc(int delay_us)
{
if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING ||
!xPortCanYield()) {
ets_delay_us(delay_us);
esp_rom_delay_us(delay_us);
return delay_us;
}
if (delay_us == 0) {
@ -257,7 +258,7 @@ esp_err_t esp_usb_console_init(void)
esp_intr_enable(s_usb_int_handle);
#ifdef CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Install ets_printf handler */
/* Install esp_rom_printf handler */
ets_install_putc1(&esp_usb_console_write_char);
#endif // CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
@ -387,8 +388,8 @@ bool esp_usb_console_write_available(void)
#ifdef CONFIG_ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF
/* Used as an output function by ets_printf.
* The LF->CRLF replacement logic replicates the one in ets_write_char_uart.
/* Used as an output function by esp_rom_printf.
* The LF->CRLF replacement logic replicates the one in esp_rom_uart_putc.
* Not static to allow placement into IRAM by ldgen.
*/
void esp_usb_console_write_char(char c)

3
components/esp_system/port/panic_handler.c
Wyświetl plik

@ -35,6 +35,7 @@
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/cache_err_int.h"
#include "esp32/dport_access.h"
@ -494,7 +495,7 @@ static void panic_handler(XtExcFrame *frame, bool pseudo_excause)
}
}
ets_delay_us(1);
esp_rom_delay_us(1);
SOC_HAL_STALL_OTHER_CORES();
#endif

9
components/esp_system/startup.c
Wyświetl plik

@ -55,14 +55,13 @@
#include "esp_private/usb_console.h"
#include "esp_vfs_cdcacm.h"
#include "esp_rom_sys.h"
// [refactor-todo] make this file completely target-independent
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/spiram.h"
#include "esp32/brownout.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/spiram.h"
#include "esp32s2/brownout.h"
#endif
@ -156,7 +155,7 @@ static void IRAM_ATTR do_system_init_fn(void)
static void IRAM_ATTR start_app_other_cores_default(void)
{
while (1) {
ets_delay_us(UINT32_MAX);
esp_rom_delay_us(UINT32_MAX);
}
}
@ -165,7 +164,7 @@ static void IRAM_ATTR start_cpu_other_cores_default(void)
do_system_init_fn();
while (!s_system_full_inited) {
ets_delay_us(100);
esp_rom_delay_us(100);
}
start_app_other_cores();
@ -295,7 +294,7 @@ static void IRAM_ATTR do_secondary_init(void)
for (int i = 0; i < SOC_CPU_CORES_NUM; i++) {
system_inited &= s_system_inited[i];
}
ets_delay_us(100);
esp_rom_delay_us(100);
}
#endif
}

2
components/esp_timer/src/ets_timer_legacy.c
Wyświetl plik

@ -32,7 +32,7 @@
#include "sdkconfig.h"
#include "esp_timer.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/ets_sys.h" // for ETSTimer type
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif

7
components/esp_timer/test/test_esp_timer.c
Wyświetl plik

@ -14,6 +14,7 @@
#include "freertos/semphr.h"
#include "test_utils.h"
#include "esp_freertos_hooks.h"
#include "esp_rom_sys.h"
#ifdef CONFIG_ESP_TIMER_PROFILING
#define WITH_PROFILING 1
@ -207,7 +208,7 @@ TEST_CASE("periodic esp_timer produces correct delays", "[esp_timer]")
p_args->intervals[p_args->cur_interval++] = ms_diff;
// Deliberately make timer handler run longer.
// We check that this doesn't affect the result.
ets_delay_us(10*1000);
esp_rom_delay_us(10*1000);
if (p_args->cur_interval == NUM_INTERVALS) {
printf("done\n");
TEST_ESP_OK(esp_timer_stop(p_args->timer));
@ -734,7 +735,7 @@ static void dport_task(void *pvParameters)
{
while (task_stop == false) {
DPORT_STALL_OTHER_CPU_START();
ets_delay_us(3);
esp_rom_delay_us(3);
DPORT_STALL_OTHER_CPU_END();
}
vTaskDelete(NULL);
@ -836,7 +837,7 @@ TEST_CASE("Test case when esp_timer_impl_set_alarm needs set timer < now_time",
#endif
esp_timer_impl_advance(50331648); // 0xefffffff/80 = 50331647
ets_delay_us(2);
esp_rom_delay_us(2);
portDISABLE_INTERRUPTS();
esp_timer_impl_set_alarm(50331647);

4
components/esp_timer/test/test_ets_timer.c
Wyświetl plik

@ -8,7 +8,7 @@
#include "freertos/semphr.h"
#include "esp_spi_flash.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/ets_sys.h" // for ETSTimer type
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
@ -69,7 +69,7 @@ TEST_CASE("periodic ets_timer produces correct delays", "[ets_timer]")
p_args->intervals[p_args->cur_interval++] = ms_diff;
// Deliberately make timer handler run longer.
// We check that this doesn't affect the result.
ets_delay_us(10*1000);
esp_rom_delay_us(10*1000);
if (p_args->cur_interval == NUM_INTERVALS) {
printf("done\n");
ets_timer_disarm(p_args->timer);

2
components/esp_wifi/src/phy_init.c
Wyświetl plik

@ -37,10 +37,8 @@
#include "esp_rom_crc.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/rtc.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/rtc.h"
#endif

3
components/espcoredump/include_core_dump/esp_core_dump_priv.h
Wyświetl plik

@ -21,13 +21,14 @@ extern "C" {
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "esp_rom_sys.h"
#include "sdkconfig.h"
#if CONFIG_ESP32_COREDUMP_CHECKSUM_SHA256
// TODO: move this to portable part of the code
#include "mbedtls/sha256.h"
#endif
#define ESP_COREDUMP_LOG( level, format, ... ) if (LOG_LOCAL_LEVEL >= level) { ets_printf(DRAM_STR(format), esp_log_early_timestamp(), (const char *)TAG, ##__VA_ARGS__); }
#define ESP_COREDUMP_LOG( level, format, ... ) if (LOG_LOCAL_LEVEL >= level) { esp_rom_printf(DRAM_STR(format), esp_log_early_timestamp(), (const char *)TAG, ##__VA_ARGS__); }
#define ESP_COREDUMP_LOGE( format, ... ) ESP_COREDUMP_LOG(ESP_LOG_ERROR, LOG_FORMAT(E, format), ##__VA_ARGS__)
#define ESP_COREDUMP_LOGW( format, ... ) ESP_COREDUMP_LOG(ESP_LOG_WARN, LOG_FORMAT(W, format), ##__VA_ARGS__)
#define ESP_COREDUMP_LOGI( format, ... ) ESP_COREDUMP_LOG(ESP_LOG_INFO, LOG_FORMAT(I, format), ##__VA_ARGS__)

7
components/espcoredump/src/core_dump_port.c
Wyświetl plik

@ -18,6 +18,7 @@
#include "freertos/task.h"
#include "freertos/xtensa_context.h" // for exception register stack structure
#include "esp_core_dump_priv.h"
#include "esp_rom_sys.h"
const static DRAM_ATTR char TAG[] __attribute__((unused)) = "esp_core_dump_port";
@ -192,11 +193,11 @@ exit:
void esp_core_dump_print_sha256(const char* msg, const uint8_t* sha_output)
{
ets_printf(DRAM_STR("%s='"), msg);
esp_rom_printf(DRAM_STR("%s='"), msg);
for (int i = 0; i < COREDUMP_SHA256_LEN; i++) {
ets_printf(DRAM_STR("%02x"), sha_output[i]);
esp_rom_printf(DRAM_STR("%02x"), sha_output[i]);
}
ets_printf(DRAM_STR("'\r\n"));
esp_rom_printf(DRAM_STR("'\r\n"));
}
#endif

9
components/espcoredump/src/core_dump_uart.c
Wyświetl plik

@ -16,6 +16,7 @@
#include "soc/gpio_periph.h"
#include "driver/gpio.h"
#include "esp_core_dump_priv.h"
#include "esp_rom_sys.h"
// TODO: move chip dependent part to portable code
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h"
@ -57,7 +58,7 @@ static esp_err_t esp_core_dump_uart_write_start(void *priv)
esp_err_t err = ESP_OK;
core_dump_write_data_t *wr_data = (core_dump_write_data_t *)priv;
esp_core_dump_checksum_init(wr_data);
ets_printf(DRAM_STR("================= CORE DUMP START =================\r\n"));
esp_rom_printf(DRAM_STR("================= CORE DUMP START =================\r\n"));
return err;
}
@ -80,9 +81,9 @@ static esp_err_t esp_core_dump_uart_write_end(void *priv)
size_t cs_len = esp_core_dump_checksum_finish(wr_data, &cs_addr);
wr_data->off += cs_len;
esp_core_dump_b64_encode((const uint8_t *)cs_addr, cs_len, (uint8_t*)&buf[0]);
ets_printf(DRAM_STR("%s\r\n"), buf);
esp_rom_printf(DRAM_STR("%s\r\n"), buf);
}
ets_printf(DRAM_STR("================= CORE DUMP END =================\r\n"));
esp_rom_printf(DRAM_STR("================= CORE DUMP END =================\r\n"));
#if CONFIG_ESP32_COREDUMP_CHECKSUM_SHA256
if (cs_addr) {
esp_core_dump_print_sha256(DRAM_STR("Coredump SHA256"), (uint8_t*)(cs_addr));
@ -107,7 +108,7 @@ static esp_err_t esp_core_dump_uart_write_data(void *priv, void * data, uint32_t
memcpy(tmp, addr, len);
esp_core_dump_b64_encode((const uint8_t *)tmp, len, (uint8_t *)buf);
addr += len;
ets_printf(DRAM_STR("%s\r\n"), buf);
esp_rom_printf(DRAM_STR("%s\r\n"), buf);
}
if (wr_data) {

5
components/fatfs/test/test_fatfs_common.c
Wyświetl plik

@ -31,6 +31,7 @@
#include "freertos/task.h"
#include "ff.h"
#include "test_fatfs_common.h"
#include "esp_rom_sys.h"
const char* fatfs_test_hello_str = "Hello, World!\n";
const char* fatfs_test_hello_str_utf = "世界，你好！\n";
@ -698,7 +699,7 @@ static void read_write_task(void* param)
if (args->write) {
int cnt = fwrite(&val, sizeof(val), 1, f);
if (cnt != 1) {
ets_printf("E(w): i=%d, cnt=%d val=%d\n\n", i, cnt, val);
esp_rom_printf("E(w): i=%d, cnt=%d val=%d\n\n", i, cnt, val);
args->result = ESP_FAIL;
goto close;
}
@ -706,7 +707,7 @@ static void read_write_task(void* param)
uint32_t rval;
int cnt = fread(&rval, sizeof(rval), 1, f);
if (cnt != 1 || rval != val) {
ets_printf("E(r): i=%d, cnt=%d rval=%d val=%d\n\n", i, cnt, rval, val);
esp_rom_printf("E(r): i=%d, cnt=%d rval=%d val=%d\n\n", i, cnt, rval, val);
args->result = ESP_FAIL;
goto close;
}

3
components/fatfs/test/test_fatfs_rawflash.c
Wyświetl plik

@ -29,6 +29,7 @@
#include "test_fatfs_common.h"
#include "esp_partition.h"
#include "ff.h"
#include "esp_rom_sys.h"
static void test_setup(size_t max_files)
@ -267,7 +268,7 @@ static void read_task(void* param)
uint32_t rval;
int cnt = fread(&rval, sizeof(rval), 1, f);
if (cnt != 1 || rval != args->val) {
ets_printf("E(r): i=%d, cnt=%d rval=%d val=%d\n\n", i, cnt, rval, args->val);
esp_rom_printf("E(r): i=%d, cnt=%d rval=%d val=%d\n\n", i, cnt, rval, args->val);
args->result = ESP_FAIL;
goto close;
}

3
components/freertos/test/test_freertos_isinisrcontext.c
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@ -13,13 +13,14 @@
#include "unity.h"
#include "esp_intr_alloc.h"
#include "xtensa/hal.h"
#include "esp_rom_sys.h"
static volatile int in_int_context, int_handled;
static void testint(void *arg) {
xthal_set_ccompare(1, xthal_get_ccount()+8000000000);
ets_printf("INT!\n");
esp_rom_printf("INT!\n");
if (xPortInIsrContext()) in_int_context++;
int_handled++;
}

6
components/freertos/test/test_freertos_task_delete.c
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@ -21,6 +21,8 @@
#include "unity.h"
#include "test_utils.h"
#include "esp_rom_sys.h"
#define NO_OF_TSKS 3
#define DELAY_TICKS 2
/* Caps of all memory which is allocated from when a task is created */
@ -42,7 +44,7 @@ static void tsk_extern_del(void *param)
static void tsk_self_del_us_delay(void *param)
{
uint32_t delay = (uint32_t)param;
ets_delay_us(delay);
esp_rom_delay_us(delay);
vTaskDelete(NULL);
}
@ -78,7 +80,7 @@ TEST_CASE("FreeRTOS Delete Tasks", "[freertos]")
for(int i = 0; i < DELAY_US_ITERATIONS; i+= 10){
vTaskDelay(1); //Sync to next tick interrupt
xTaskCreatePinnedToCore(tsk_self_del_us_delay, "delay", 1024, (void *)i, UNITY_FREERTOS_PRIORITY - 1, NULL, tskNO_AFFINITY);
ets_delay_us(10); //Busy wait to ensure no affinity task runs on opposite core
esp_rom_delay_us(10); //Busy wait to ensure no affinity task runs on opposite core
}
}

16
components/freertos/test/test_suspend_scheduler.c
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@ -13,6 +13,8 @@
#include "driver/timer.h"
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2
#define int_clr_timers int_clr
#define update update.update
@ -102,7 +104,7 @@ TEST_CASE("Scheduler disabled can handle a pending context switch on resume", "[
unsigned no_sched_task = count_config.counter;
// scheduler off on this CPU...
ets_delay_us(20 * 1000);
esp_rom_delay_us(20 * 1000);
//TEST_ASSERT_NOT_EQUAL(no_sched_isr, isr_count);
TEST_ASSERT_EQUAL(count_config.counter, no_sched_task);
@ -171,12 +173,12 @@ TEST_CASE("Scheduler disabled can wake multiple tasks on resume", "[freertos]")
}
}
ets_delay_us(200); /* Let the other CPU do some things */
esp_rom_delay_us(200); /* Let the other CPU do some things */
for (int p = 0; p < portNUM_PROCESSORS; p++) {
for (int t = 0; t < TASKS_PER_PROC; t++) {
int expected = (p == UNITY_FREERTOS_CPU) ? 0 : 1; // Has run if it was on the other CPU
ets_printf("Checking CPU %d task %d (expected %d actual %d)\n", p, t, expected, counters[p][t].counter);
esp_rom_printf("Checking CPU %d task %d (expected %d actual %d)\n", p, t, expected, counters[p][t].counter);
TEST_ASSERT_EQUAL(expected, counters[p][t].counter);
}
}
@ -187,7 +189,7 @@ TEST_CASE("Scheduler disabled can wake multiple tasks on resume", "[freertos]")
/* Now the tasks on both CPUs should have been woken once and counted once. */
for (int p = 0; p < portNUM_PROCESSORS; p++) {
for (int t = 0; t < TASKS_PER_PROC; t++) {
ets_printf("Checking CPU %d task %d (expected 1 actual %d)\n", p, t, counters[p][t].counter);
esp_rom_printf("Checking CPU %d task %d (expected 1 actual %d)\n", p, t, counters[p][t].counter);
TEST_ASSERT_EQUAL(1, counters[p][t].counter);
}
}
@ -208,7 +210,7 @@ static void suspend_scheduler_5ms_task_fn(void *ignore)
vTaskSuspendAll();
sched_suspended = true;
for (int i = 0; i <5; i++) {
ets_delay_us(1000);
esp_rom_delay_us(1000);
}
xTaskResumeAll();
sched_suspended = false;
@ -240,7 +242,7 @@ TEST_CASE("Scheduler disabled on CPU B, tasks on A can wake", "[freertos]")
while(!sched_suspended) { }
xSemaphoreGive(wake_sem);
ets_delay_us(1000);
esp_rom_delay_us(1000);
// Bit of a race here if the other CPU resumes its scheduler, but 5ms is a long time... */
TEST_ASSERT(sched_suspended);
TEST_ASSERT_EQUAL(0, count_config.counter); // the other task hasn't woken yet, because scheduler is off
@ -249,7 +251,7 @@ TEST_CASE("Scheduler disabled on CPU B, tasks on A can wake", "[freertos]")
/* wait for the rest of the 5ms... */
while(sched_suspended) { }
ets_delay_us(100);
esp_rom_delay_us(100);
TEST_ASSERT_EQUAL(1, count_config.counter); // when scheduler resumes, counter task should immediately count
vTaskDelete(counter_task);

7
components/freertos/test/test_task_suspend_resume.c
Wyświetl plik

@ -19,6 +19,7 @@
#endif
#include "esp_freertos_hooks.h"
#include "esp_rom_sys.h"
#ifdef CONFIG_IDF_TARGET_ESP32S2
#define int_clr_timers int_clr
@ -195,7 +196,7 @@ static void IRAM_ATTR suspend_scheduler_while_block_set(void* arg)
vTaskSuspendAll();
while (block) { };
ets_delay_us(1);
esp_rom_delay_us(1);
xTaskResumeAll();
}
@ -236,12 +237,12 @@ static void waiting_task(void *pvParameters)
static void control_task(void *pvParameters)
{
int cpu_id = xPortGetCoreID();
ets_delay_us(2000); // let to start the waiting_task first
esp_rom_delay_us(2000); // let to start the waiting_task first
printf("Start control_task cpu=%d\n", cpu_id);
int64_t start_time = esp_timer_get_time();
suspend_scheduler_on_both_cpus();
ets_delay_us(waiting_ms * 1000 + delta_ms * 1000);
esp_rom_delay_us(waiting_ms * 1000 + delta_ms * 1000);
resume_scheduler_on_both_cpus();
duration_ctrl_task_ms = (esp_timer_get_time() - start_time) / 1000;

19
components/freertos/xtensa/include/freertos/FreeRTOSConfig.h
Wyświetl plik

@ -120,8 +120,9 @@ int xt_clock_freq(void) __attribute__((deprecated));
/* configASSERT behaviour */
#ifndef __ASSEMBLER__
#include <stdlib.h> /* for abort() */
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
@ -129,20 +130,20 @@ int xt_clock_freq(void) __attribute__((deprecated));
#if defined(CONFIG_FREERTOS_ASSERT_DISABLE)
#define configASSERT(a) /* assertions disabled */
#elif defined(CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE)
#define configASSERT(a) if (unlikely(!(a))) { \
ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
__FUNCTION__); \
#define configASSERT(a) if (unlikely(!(a))) { \
esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
__FUNCTION__); \
}
#else /* CONFIG_FREERTOS_ASSERT_FAIL_ABORT */
#define configASSERT(a) if (unlikely(!(a))) { \
ets_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
__FUNCTION__); \
abort(); \
#define configASSERT(a) if (unlikely(!(a))) { \
esp_rom_printf("%s:%d (%s)- assert failed!\n", __FILE__, __LINE__, \
__FUNCTION__); \
abort(); \
}
#endif
#if CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION
#define UNTESTED_FUNCTION() { ets_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
#define UNTESTED_FUNCTION() { esp_rom_printf("Untested FreeRTOS function %s\r\n", __FUNCTION__); configASSERT(false); } while(0)
#else
#define UNTESTED_FUNCTION()
#endif

22
components/freertos/xtensa/include/freertos/portmacro.h
Wyświetl plik

@ -84,7 +84,7 @@ extern "C" {
#include "esp_timer.h" /* required for FreeRTOS run time stats */
#include "soc/spinlock.h"
#include <esp_heap_caps.h>
#include "esp_rom_sys.h"
#include "sdkconfig.h"
#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
@ -225,22 +225,22 @@ static inline void __attribute__((always_inline)) vPortEnterCriticalCompliance(p
{
if(!xPortInIsrContext()) {
vPortEnterCritical(mux);
} else {
ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__,
__FUNCTION__);
abort();
}
} else {
esp_rom_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n",
__FILE__, __LINE__, __FUNCTION__);
abort();
}
}
static inline void __attribute__((always_inline)) vPortExitCriticalCompliance(portMUX_TYPE *mux)
{
if(!xPortInIsrContext()) {
vPortExitCritical(mux);
} else {
ets_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n", __FILE__, __LINE__,
__FUNCTION__);
abort();
}
} else {
esp_rom_printf("%s:%d (%s)- port*_CRITICAL called from ISR context!\n",
__FILE__, __LINE__, __FUNCTION__);
abort();
}
}
#ifdef CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE

3
components/freertos/xtensa/xtensa_intr.c
Wyświetl plik

@ -34,6 +34,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "freertos/xtensa_api.h"
#include "freertos/portable.h"
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#if XCHAL_HAVE_EXCEPTIONS
@ -99,7 +100,7 @@ extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS*portNUM_P
*/
void xt_unhandled_interrupt(void * arg)
{
ets_printf("Unhandled interrupt %d on cpu %d!\n", (int)arg, xPortGetCoreID());
esp_rom_printf("Unhandled interrupt %d on cpu %d!\n", (int)arg, xPortGetCoreID());
}

9
components/heap/multi_heap_platform.h
Wyświetl plik

@ -17,8 +17,9 @@
#include <freertos/FreeRTOS.h>
#include "sdkconfig.h"
#include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
@ -50,8 +51,8 @@ typedef portMUX_TYPE multi_heap_lock_t;
/* Not safe to use std i/o while in a portmux critical section,
can deadlock, so we use the ROM equivalent functions. */
#define MULTI_HEAP_PRINTF ets_printf
#define MULTI_HEAP_STDERR_PRINTF(MSG, ...) ets_printf(MSG, __VA_ARGS__)
#define MULTI_HEAP_PRINTF esp_rom_printf
#define MULTI_HEAP_STDERR_PRINTF(MSG, ...) esp_rom_printf(MSG, __VA_ARGS__)
inline static void multi_heap_assert(bool condition, const char *format, int line, intptr_t address)
{
@ -62,7 +63,7 @@ inline static void multi_heap_assert(bool condition, const char *format, int lin
#ifndef NDEBUG
if(!condition) {
#ifndef CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT
ets_printf(format, line, address);
esp_rom_printf(format, line, address);
#endif // CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT
abort();
}

25
components/log/include/esp_log.h
Wyświetl plik

@ -17,9 +17,10 @@
#include <stdint.h>
#include <stdarg.h>
#include "esp_rom_sys.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/ets_sys.h" // will be removed in idf v5.0
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/ets_sys.h"
#endif
@ -285,9 +286,9 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
/// macro to output logs in startup code at ``ESP_LOG_VERBOSE`` level. @see ``ESP_EARLY_LOGE``,``ESP_LOGE``, ``printf``
#define ESP_EARLY_LOGV( tag, format, ... ) ESP_LOG_EARLY_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__)
#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do { \
if (LOG_LOCAL_LEVEL >= log_level) { \
ets_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \
#define ESP_LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...) do { \
if (LOG_LOCAL_LEVEL >= log_level) { \
esp_rom_printf(LOG_FORMAT(log_tag_letter, format), esp_log_timestamp(), tag, ##__VA_ARGS__); \
}} while(0)
#ifndef BOOTLOADER_BUILD
@ -361,24 +362,24 @@ void esp_log_writev(esp_log_level_t level, const char* tag, const char* format,
*
* @note Placing log strings in DRAM reduces available DRAM, so only use when absolutely essential.
*
* @see ``ets_printf``,``ESP_LOGE``
* @see ``esp_rom_printf``,``ESP_LOGE``
*/
#define ESP_DRAM_LOGE( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_ERROR, E, ##__VA_ARGS__)
/// macro to output logs when the cache is disabled at ``ESP_LOG_WARN`` level. @see ``ESP_DRAM_LOGW``,``ESP_LOGW``, ``ets_printf``
/// macro to output logs when the cache is disabled at ``ESP_LOG_WARN`` level. @see ``ESP_DRAM_LOGW``,``ESP_LOGW``, ``esp_rom_printf``
#define ESP_DRAM_LOGW( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_WARN, W, ##__VA_ARGS__)
/// macro to output logs when the cache is disabled at ``ESP_LOG_INFO`` level. @see ``ESP_DRAM_LOGI``,``ESP_LOGI``, ``ets_printf``
/// macro to output logs when the cache is disabled at ``ESP_LOG_INFO`` level. @see ``ESP_DRAM_LOGI``,``ESP_LOGI``, ``esp_rom_printf``
#define ESP_DRAM_LOGI( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_INFO, I, ##__VA_ARGS__)
/// macro to output logs when the cache is disabled at ``ESP_LOG_DEBUG`` level. @see ``ESP_DRAM_LOGD``,``ESP_LOGD``, ``ets_printf``
/// macro to output logs when the cache is disabled at ``ESP_LOG_DEBUG`` level. @see ``ESP_DRAM_LOGD``,``ESP_LOGD``, ``esp_rom_printf``
#define ESP_DRAM_LOGD( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_DEBUG, D, ##__VA_ARGS__)
/// macro to output logs when the cache is disabled at ``ESP_LOG_VERBOSE`` level. @see ``ESP_DRAM_LOGV``,``ESP_LOGV``, ``ets_printf``
/// macro to output logs when the cache is disabled at ``ESP_LOG_VERBOSE`` level. @see ``ESP_DRAM_LOGV``,``ESP_LOGV``, ``esp_rom_printf``
#define ESP_DRAM_LOGV( tag, format, ... ) ESP_DRAM_LOG_IMPL(tag, format, ESP_LOG_VERBOSE, V, ##__VA_ARGS__)
/** @cond */
#define _ESP_LOG_DRAM_LOG_FORMAT(letter, format) DRAM_STR(#letter " %s: " format "\n")
#define ESP_DRAM_LOG_IMPL(tag, format, log_level, log_tag_letter, ...) do { \
if (LOG_LOCAL_LEVEL >= log_level) { \
ets_printf(_ESP_LOG_DRAM_LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \
#define ESP_DRAM_LOG_IMPL(tag, format, log_level, log_tag_letter, ...) do { \
if (LOG_LOCAL_LEVEL >= log_level) { \
esp_rom_printf(_ESP_LOG_DRAM_LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \
}} while(0)
/** @endcond */

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