From eb1fd7365e3d893f98dea51fed17154a5ff7708c Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Mon, 29 Jan 2024 18:17:26 +0800 Subject: [PATCH 1/3] ci(esp32c5): enable hello world build on ci --- examples/get-started/.build-test-rules.yml | 6 +++++- examples/get-started/hello_world/README.md | 4 ++-- tools/ci/build_template_app.sh | 4 ++-- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/examples/get-started/.build-test-rules.yml b/examples/get-started/.build-test-rules.yml index 44730e82b8..70ed6eb347 100644 --- a/examples/get-started/.build-test-rules.yml +++ b/examples/get-started/.build-test-rules.yml @@ -8,4 +8,8 @@ examples/get-started/blink: examples/get-started/hello_world: enable: - - if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "linux" + - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["linux", "esp32c5"] + disable_test: + - if: IDF_TARGET == "esp32c5" + temporary: true + reason: lack of runner diff --git a/examples/get-started/hello_world/README.md b/examples/get-started/hello_world/README.md index 29171c316c..dc47514a87 100644 --- a/examples/get-started/hello_world/README.md +++ b/examples/get-started/hello_world/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- | # Hello World Example diff --git a/tools/ci/build_template_app.sh b/tools/ci/build_template_app.sh index dae77fdd4f..4fb416f450 100755 --- a/tools/ci/build_template_app.sh +++ b/tools/ci/build_template_app.sh @@ -62,7 +62,7 @@ build_stage2() { --size-file size.json \ --keep-going \ --collect-size-info size_info.txt \ - --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c6 esp32h2 esp32p4 + --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 } build_stage1() { @@ -76,7 +76,7 @@ build_stage1() { --build-log ${BUILD_LOG_CMAKE} \ --size-file size.json \ --collect-size-info size_info.txt \ - --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c6 esp32h2 esp32p4 + --default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4 } # Default arguments From c0c6af99e97450b0a90225936f54adf043b1cf87 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Mon, 22 Jan 2024 22:50:07 +0800 Subject: [PATCH 2/3] fix(esp32c5): fixed the lack of crosscore ll on c5 --- .../include/esp_private/esp_pmu.h | 8 ++- .../port/esp32c5/CMakeLists.txt | 6 +++ .../port/esp32c5/private_include/pmu_param.h | 6 --- .../port/esp32c5/rtc_clk_init.c | 8 ++- .../port/soc/esp32c5/cache_err_int.c | 4 +- .../esp32c5/include/hal/crosscore_int_ll.h | 52 +++++++++++++++++++ .../esp32c5/include/soc/Kconfig.soc_caps.in | 4 -- components/soc/esp32c5/include/soc/soc_caps.h | 2 +- 8 files changed, 75 insertions(+), 15 deletions(-) create mode 100644 components/hal/esp32c5/include/hal/crosscore_int_ll.h diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 1d8d2c309b..5a92f65393 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -145,6 +145,12 @@ extern "C" { #define PMU_SLEEP_PD_RC32K BIT(13) #define PMU_SLEEP_PD_LP_PERIPH BIT(14) +/** + * This macro only used for detecting whether the enums are declared + * So that to avoid use the enum when PMU is not supported + */ +#define ESP_PMU_ENUMS_DECLARED + typedef struct { pmu_hal_context_t *hal; void *mc; diff --git a/components/esp_hw_support/port/esp32c5/CMakeLists.txt b/components/esp_hw_support/port/esp32c5/CMakeLists.txt index 49c9eb37b0..ca13f73723 100644 --- a/components/esp_hw_support/port/esp32c5/CMakeLists.txt +++ b/components/esp_hw_support/port/esp32c5/CMakeLists.txt @@ -6,6 +6,12 @@ set(srcs "rtc_clk_init.c" "chip_info.c" ) +# TODO: [ESP32C5] IDF-8667 +if(IDF_TARGET STREQUAL "esp32c5") + list(REMOVE_ITEM srcs "pmu_init.c" + "pmu_param.c") +endif() + if(NOT BOOTLOADER_BUILD) list(APPEND srcs "sar_periph_ctrl.c" "esp_crypto_lock.c") diff --git a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h index b4c14c0eaa..909a583215 100644 --- a/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h +++ b/components/esp_hw_support/port/esp32c5/private_include/pmu_param.h @@ -10,10 +10,8 @@ #include #include #include "soc/soc_caps.h" -#if SOC_PMU_SUPPORTED #include "soc/pmu_struct.h" #include "hal/pmu_hal.h" -#endif // TODO: [ESP32C5] IDF-8643 @@ -25,8 +23,6 @@ extern "C" { #define HP_CALI_DBIAS 25 #define LP_CALI_DBIAS 26 -#if SOC_PMU_SUPPORTED - // FOR XTAL FORCE PU IN SLEEP #define PMU_PD_CUR_SLEEP_ON 0 #define PMU_BIASSLP_SLEEP_ON 0 @@ -474,8 +470,6 @@ typedef struct pmu_sleep_machine_constant { } \ } -#endif // SOC_PMU_SUPPORTED - #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c index e7a8e53518..f5d78e850b 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c @@ -23,7 +23,6 @@ #include "hal/clk_tree_ll.h" #include "hal/modem_syscon_ll.h" #include "hal/modem_lpcon_ll.h" -#include "soc/pmu_reg.h" #include "pmu_param.h" static const char *TAG = "rtc_clk_init"; @@ -42,6 +41,10 @@ static const char *TAG = "rtc_clk_init"; */ static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void) { +// If PMU has not supported yet, the enum has not declared, use macro instead +#ifndef ESP_PMU_ENUMS_DECLARED +#define PMU_HP_ICG_MODEM_CODE_ACTIVE 2 +#endif /* Configure modem ICG code in PMU_ACTIVE state */ pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE); @@ -53,6 +56,9 @@ static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void) /* Software trigger force update modem ICG code and ICG switch */ pmu_ll_imm_update_dig_icg_modem_code(&PMU, true); pmu_ll_imm_update_dig_icg_switch(&PMU, true); +#ifndef ESP_PMU_ENUMS_DECLARED +#undef PMU_HP_ICG_MODEM_CODE_ACTIVE +#endif } diff --git a/components/esp_system/port/soc/esp32c5/cache_err_int.c b/components/esp_system/port/soc/esp32c5/cache_err_int.c index 4382ac2e7a..a2d4320741 100644 --- a/components/esp_system/port/soc/esp32c5/cache_err_int.c +++ b/components/esp_system/port/soc/esp32c5/cache_err_int.c @@ -57,8 +57,8 @@ void esp_cache_err_int_init(void) esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM); /* Set the type and priority to cache error interrupts. */ - esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); - esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); + esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL); + esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM); ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK); /* On the hardware side, start by clearing all the bits reponsible for cache access error */ diff --git a/components/hal/esp32c5/include/hal/crosscore_int_ll.h b/components/hal/esp32c5/include/hal/crosscore_int_ll.h new file mode 100644 index 0000000000..c76790d756 --- /dev/null +++ b/components/hal/esp32c5/include/hal/crosscore_int_ll.h @@ -0,0 +1,52 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_attr.h" +#include "soc/intpri_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Clear the crosscore interrupt that just occurred on the current core + */ +FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id) +{ + WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0); +} + + +/** + * @brief Trigger a crosscore interrupt on the given core + * + * @param core_id Core to trigger an interrupt on. Ignored on single core targets. + */ +FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id) +{ + WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0); +} + + +/** + * @brief Get the state of the crosscore interrupt register for the given core + * + * @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets. + * + * @return Non zero value if a software interrupt is pending on the given core, + * 0 if no software interrupt is pending. + */ +FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id) +{ + return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG); +} + + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 90bfb9df01..2294333d62 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -31,10 +31,6 @@ config SOC_FLASH_ENC_SUPPORTED bool default y -config SOC_PMU_SUPPORTED - bool - default y - config SOC_SPI_FLASH_SUPPORTED bool default y diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index dfd0fdc602..e9028f8478 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -56,7 +56,7 @@ // #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623 // #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647 // #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614 -#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 +// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667 // #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 // #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636 // #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640 From ea14b24048fa124daa1be6e7ba3485f4a9328779 Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 30 Jan 2024 14:19:54 +0800 Subject: [PATCH 3/3] ci(esp32c5): fix the build of the template app --- .gitlab/ci/default-build-test-rules.yml | 3 +- components/esp_driver_ledc/linker.lf | 3 +- .../include/esp_private/esp_pmu.h | 33 +++++++++---------- components/esp_hw_support/linker.lf | 2 +- .../port/esp32c5/rtc_clk_init.c | 7 ---- examples/get-started/.build-test-rules.yml | 4 --- 6 files changed, 20 insertions(+), 32 deletions(-) diff --git a/.gitlab/ci/default-build-test-rules.yml b/.gitlab/ci/default-build-test-rules.yml index 89024c5b73..4bd04da364 100644 --- a/.gitlab/ci/default-build-test-rules.yml +++ b/.gitlab/ci/default-build-test-rules.yml @@ -9,7 +9,8 @@ extra_default_build_targets: - esp32p4 -# bypass_check_test_targets: +bypass_check_test_targets: + - esp32c5 # - esp32p4 # # These lines would diff --git a/components/esp_driver_ledc/linker.lf b/components/esp_driver_ledc/linker.lf index 1bb52d58a1..c1307aebd1 100644 --- a/components/esp_driver_ledc/linker.lf +++ b/components/esp_driver_ledc/linker.lf @@ -9,4 +9,5 @@ entries: [mapping:ledc_hal] archive: libhal.a entries: - ledc_hal_iram (noflash) + if SOC_LEDC_SUPPORTED = y: + ledc_hal_iram (noflash) diff --git a/components/esp_hw_support/include/esp_private/esp_pmu.h b/components/esp_hw_support/include/esp_private/esp_pmu.h index 5a92f65393..fca1a53d97 100644 --- a/components/esp_hw_support/include/esp_private/esp_pmu.h +++ b/components/esp_hw_support/include/esp_private/esp_pmu.h @@ -13,13 +13,26 @@ #include "soc/soc_caps.h" +#if SOC_PMU_SUPPORTED +#include "hal/pmu_hal.h" +#include "pmu_param.h" +#endif + #ifdef __cplusplus extern "C" { #endif +/** + * @brief PMU ICG modem code of HP system + * @note This type is required in rtc_clk_init.c when PMU not fully supported + */ +typedef enum { + PMU_HP_ICG_MODEM_CODE_SLEEP = 0, + PMU_HP_ICG_MODEM_CODE_MODEM = 1, + PMU_HP_ICG_MODEM_CODE_ACTIVE = 2, +} pmu_hp_icg_modem_mode_t; + #if SOC_PMU_SUPPORTED -#include "hal/pmu_hal.h" -#include "pmu_param.h" #define RTC_SLEEP_PD_DIG PMU_SLEEP_PD_TOP //!< Deep sleep (power down digital domain, includes all power domains // except CPU, Modem, LP peripheral, AON，VDDSDIO, MEM and clock power domains) @@ -145,12 +158,6 @@ extern "C" { #define PMU_SLEEP_PD_RC32K BIT(13) #define PMU_SLEEP_PD_LP_PERIPH BIT(14) -/** - * This macro only used for detecting whether the enums are declared - * So that to avoid use the enum when PMU is not supported - */ -#define ESP_PMU_ENUMS_DECLARED - typedef struct { pmu_hal_context_t *hal; void *mc; @@ -179,16 +186,6 @@ typedef enum pmu_sleep_regdma_entry { PMU_SLEEP_REGDMA_ENTRY_MAX } pmu_sleep_regdma_entry_t; -/** - * @brief PMU ICG modem code of HP system - */ -typedef enum { - PMU_HP_ICG_MODEM_CODE_SLEEP = 0, - PMU_HP_ICG_MODEM_CODE_MODEM = 1, - PMU_HP_ICG_MODEM_CODE_ACTIVE = 2, -} pmu_hp_icg_modem_mode_t; - - /** * @brief Enable_regdma_backup. */ diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index 66f8618a5e..2e74701120 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -18,7 +18,7 @@ entries: if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED = y: rtc_init:rtc_vddsdio_get_config (noflash) rtc_init:rtc_vddsdio_set_config (noflash) - if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n && IDF_TARGET_ESP32P4 = n: # TODO: IDF-5645 + if SOC_PMU_SUPPORTED = n: rtc_sleep (noflash_text) rtc_time (noflash_text) if SOC_PMU_SUPPORTED = y: diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c index f5d78e850b..9a0efba6cb 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk_init.c @@ -41,10 +41,6 @@ static const char *TAG = "rtc_clk_init"; */ static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void) { -// If PMU has not supported yet, the enum has not declared, use macro instead -#ifndef ESP_PMU_ENUMS_DECLARED -#define PMU_HP_ICG_MODEM_CODE_ACTIVE 2 -#endif /* Configure modem ICG code in PMU_ACTIVE state */ pmu_ll_hp_set_icg_modem(&PMU, PMU_MODE_HP_ACTIVE, PMU_HP_ICG_MODEM_CODE_ACTIVE); @@ -56,9 +52,6 @@ static void rtc_clk_modem_clock_domain_active_state_icg_map_preinit(void) /* Software trigger force update modem ICG code and ICG switch */ pmu_ll_imm_update_dig_icg_modem_code(&PMU, true); pmu_ll_imm_update_dig_icg_switch(&PMU, true); -#ifndef ESP_PMU_ENUMS_DECLARED -#undef PMU_HP_ICG_MODEM_CODE_ACTIVE -#endif } diff --git a/examples/get-started/.build-test-rules.yml b/examples/get-started/.build-test-rules.yml index 70ed6eb347..2cf7304530 100644 --- a/examples/get-started/.build-test-rules.yml +++ b/examples/get-started/.build-test-rules.yml @@ -9,7 +9,3 @@ examples/get-started/blink: examples/get-started/hello_world: enable: - if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["linux", "esp32c5"] - disable_test: - - if: IDF_TARGET == "esp32c5" - temporary: true - reason: lack of runner