kopia lustrzana https://github.com/espressif/esp-idf
Merge branch 'bugfix/i2s_apll_clock_fix' into 'master'
driver/i2s: fix apll_clock_rate for different sample rates See merge request idf/esp-idf!5159pull/3717/head
commit
13d9c483b3
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@ -89,6 +89,7 @@ typedef struct {
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bool use_apll; /*!< I2S use APLL clock */
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bool use_apll; /*!< I2S use APLL clock */
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bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor on underflow */
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bool tx_desc_auto_clear; /*!< I2S auto clear tx descriptor on underflow */
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int fixed_mclk; /*!< I2S fixed MLCK clock */
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int fixed_mclk; /*!< I2S fixed MLCK clock */
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double real_rate;
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#ifdef CONFIG_PM_ENABLE
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#ifdef CONFIG_PM_ENABLE
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esp_pm_lock_handle_t pm_lock;
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esp_pm_lock_handle_t pm_lock;
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#endif
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#endif
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@ -178,6 +179,12 @@ esp_err_t i2s_enable_tx_intr(i2s_port_t i2s_num)
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return ESP_OK;
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return ESP_OK;
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}
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}
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float i2s_get_clk(i2s_port_t i2s_num)
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{
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I2S_CHECK((i2s_num < I2S_NUM_MAX), "i2s_num error", ESP_ERR_INVALID_ARG);
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return p_i2s_obj[i2s_num]->real_rate;
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}
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static esp_err_t i2s_isr_register(i2s_port_t i2s_num, int intr_alloc_flags, void (*fn)(void*), void * arg, i2s_isr_handle_t *handle)
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static esp_err_t i2s_isr_register(i2s_port_t i2s_num, int intr_alloc_flags, void (*fn)(void*), void * arg, i2s_isr_handle_t *handle)
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{
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{
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return esp_intr_alloc(ETS_I2S0_INTR_SOURCE + i2s_num, intr_alloc_flags, fn, arg, handle);
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return esp_intr_alloc(ETS_I2S0_INTR_SOURCE + i2s_num, intr_alloc_flags, fn, arg, handle);
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@ -268,6 +275,16 @@ static esp_err_t i2s_apll_calculate_fi2s(int rate, int bits_per_sample, int *sdm
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*odir = _odir;
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*odir = _odir;
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}
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}
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}
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}
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min_diff = APLL_MAX_FREQ;
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for (_sdm2 = 4; _sdm2 < 9; _sdm2 ++) {
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max_rate = i2s_apll_get_fi2s(bits_per_sample, 255, 255, _sdm2, *odir);
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min_rate = i2s_apll_get_fi2s(bits_per_sample, 0, 0, _sdm2, *odir);
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avg = (max_rate + min_rate)/2;
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if (abs(avg - rate) < min_diff) {
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min_diff = abs(avg - rate);
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*sdm2 = _sdm2;
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}
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}
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min_diff = APLL_MAX_FREQ;
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min_diff = APLL_MAX_FREQ;
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for (_sdm1 = 0; _sdm1 < 256; _sdm1 ++) {
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for (_sdm1 = 0; _sdm1 < 256; _sdm1 ++) {
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@ -455,6 +472,7 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
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I2S[i2s_num]->sample_rate_conf.rx_bck_div_num = m_scale;
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I2S[i2s_num]->sample_rate_conf.rx_bck_div_num = m_scale;
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I2S[i2s_num]->clkm_conf.clka_en = 1;
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I2S[i2s_num]->clkm_conf.clka_en = 1;
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double fi2s_rate = i2s_apll_get_fi2s(bits, sdm0, sdm1, sdm2, odir);
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double fi2s_rate = i2s_apll_get_fi2s(bits, sdm0, sdm1, sdm2, odir);
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p_i2s_obj[i2s_num]->real_rate = fi2s_rate/bits/channel/m_scale;
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ESP_LOGI(I2S_TAG, "APLL: Req RATE: %d, real rate: %0.3f, BITS: %u, CLKM: %u, BCK_M: %u, MCLK: %0.3f, SCLK: %f, diva: %d, divb: %d",
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ESP_LOGI(I2S_TAG, "APLL: Req RATE: %d, real rate: %0.3f, BITS: %u, CLKM: %u, BCK_M: %u, MCLK: %0.3f, SCLK: %f, diva: %d, divb: %d",
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rate, fi2s_rate/bits/channel/m_scale, bits, 1, m_scale, fi2s_rate, fi2s_rate/8, 1, 0);
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rate, fi2s_rate/bits/channel/m_scale, bits, 1, m_scale, fi2s_rate, fi2s_rate/8, 1, 0);
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} else {
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} else {
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@ -465,6 +483,7 @@ esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t b
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I2S[i2s_num]->sample_rate_conf.tx_bck_div_num = bck;
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I2S[i2s_num]->sample_rate_conf.tx_bck_div_num = bck;
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I2S[i2s_num]->sample_rate_conf.rx_bck_div_num = bck;
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I2S[i2s_num]->sample_rate_conf.rx_bck_div_num = bck;
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double real_rate = (double) (I2S_BASE_CLK / (bck * bits * clkmInteger) / 2);
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double real_rate = (double) (I2S_BASE_CLK / (bck * bits * clkmInteger) / 2);
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p_i2s_obj[i2s_num]->real_rate = real_rate;
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ESP_LOGI(I2S_TAG, "PLL_D2: Req RATE: %d, real rate: %0.3f, BITS: %u, CLKM: %u, BCK: %u, MCLK: %0.3f, SCLK: %f, diva: %d, divb: %d",
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ESP_LOGI(I2S_TAG, "PLL_D2: Req RATE: %d, real rate: %0.3f, BITS: %u, CLKM: %u, BCK: %u, MCLK: %0.3f, SCLK: %f, diva: %d, divb: %d",
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rate, real_rate, bits, clkmInteger, bck, (double)I2S_BASE_CLK / mclk, real_rate*bits*channel, 64, clkmDecimals);
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rate, real_rate, bits, clkmInteger, bck, (double)I2S_BASE_CLK / mclk, real_rate*bits*channel, 64, clkmDecimals);
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}
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}
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@ -501,6 +501,16 @@ esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num);
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*/
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*/
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esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t bits, i2s_channel_t ch);
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esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t bits, i2s_channel_t ch);
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/**
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* @brief get clock set on particular port number.
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*
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* @param i2s_num I2S_NUM_0, I2S_NUM_1
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*
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* @return
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* - actual clock set by i2s driver
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*/
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float i2s_get_clk(i2s_port_t i2s_num);
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/**
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/**
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* @brief Set built-in ADC mode for I2S DMA, this function will initialize ADC pad,
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* @brief Set built-in ADC mode for I2S DMA, this function will initialize ADC pad,
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* and set ADC parameters.
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* and set ADC parameters.
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@ -9,6 +9,7 @@
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#include "freertos/task.h"
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#include "freertos/task.h"
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#include "driver/i2s.h"
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#include "driver/i2s.h"
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#include "unity.h"
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#include "unity.h"
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#include "math.h"
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#define SAMPLE_RATE (36000)
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#define SAMPLE_RATE (36000)
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#define SAMPLE_BITS (16)
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#define SAMPLE_BITS (16)
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@ -18,6 +19,7 @@
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#define SLAVE_WS_IO 26
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#define SLAVE_WS_IO 26
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#define DATA_IN_IO 21
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#define DATA_IN_IO 21
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#define DATA_OUT_IO 22
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#define DATA_OUT_IO 22
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#define PERCENT_DIFF 0.0001
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/**
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/**
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* i2s initialize test
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* i2s initialize test
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@ -267,3 +269,54 @@ TEST_CASE("I2S memory leaking test", "[i2s]")
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vTaskDelay(100 / portTICK_PERIOD_MS);
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vTaskDelay(100 / portTICK_PERIOD_MS);
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TEST_ASSERT(initial_size == esp_get_free_heap_size());
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TEST_ASSERT(initial_size == esp_get_free_heap_size());
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}
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}
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/*
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* The I2S APLL clock variation test used to test the difference between the different sample rates, different bits per sample
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* and the APLL clock generate for it. The TEST_CASE passes PERCENT_DIFF variation from the provided sample rate in APLL generated clock
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* The percentage difference calculated as (mod((obtained clock rate - desired clock rate)/(desired clock rate))) * 100.
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*/
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TEST_CASE("I2S APLL clock variation test", "[i2s]")
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{
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i2s_pin_config_t pin_config = {
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.bck_io_num = MASTER_BCK_IO,
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.ws_io_num = MASTER_WS_IO,
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.data_out_num = DATA_OUT_IO,
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.data_in_num = -1
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};
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i2s_config_t i2s_config = {
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.mode = I2S_MODE_MASTER | I2S_MODE_TX,
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.sample_rate = SAMPLE_RATE,
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.bits_per_sample = SAMPLE_BITS,
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.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
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.communication_format = I2S_COMM_FORMAT_I2S,
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.dma_buf_count = 6,
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.dma_buf_len = 60,
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.use_apll = true,
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.intr_alloc_flags = 0,
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};
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TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
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TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
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TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
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int initial_size = esp_get_free_heap_size();
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uint32_t sample_rate_arr[8] = { 10675, 11025, 16000, 22050, 32000, 44100, 48000, 96000 };
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int bits_per_sample_arr[3] = { 16, 24, 32 };
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for (int i = 0; i < (sizeof(sample_rate_arr)/sizeof(sample_rate_arr[0])); i++) {
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for (int j = 0; j < (sizeof(bits_per_sample_arr)/sizeof(bits_per_sample_arr[0])); j++) {
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i2s_config.sample_rate = sample_rate_arr[i];
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i2s_config.bits_per_sample = bits_per_sample_arr[j];
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TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
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TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
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TEST_ASSERT((fabs((i2s_get_clk(I2S_NUM_0) - sample_rate_arr[i]))/(sample_rate_arr[i]))*100 < PERCENT_DIFF);
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TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
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TEST_ASSERT(initial_size == esp_get_free_heap_size());
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}
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}
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vTaskDelay(100 / portTICK_PERIOD_MS);
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TEST_ASSERT(initial_size == esp_get_free_heap_size());
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}
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