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Merge branch 'feature/i2c_support_esp32c5' into 'master' 

feat(i2c): Add I2C support on ESP32C5

Closes IDF-8694 and IDF-8696

See merge request espressif/esp-idf!29196
pull/13309/head
C.S.M 2024-02-29 21:51:45 +08:00
rodzic e18fd01d0d ddb0c21d4c
commit 1360f1b0a9
10 zmienionych plików z 1225 dodań i 32 usunięć
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7
components/driver/i2c/i2c.c
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@ -28,6 +28,7 @@
#include "esp_rom_sys.h"
#include <sys/param.h>
#include "soc/clk_tree_defs.h"
#include "esp_private/gpio.h"
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#include "esp_private/sleep_retention.h"
#endif
@ -967,7 +968,7 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool s
scl_in_sig = i2c_periph_signal[i2c_num].scl_in_sig;
if (sda_io_num >= 0) {
gpio_set_level(sda_io_num, I2C_IO_INIT_LEVEL);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[sda_io_num], PIN_FUNC_GPIO);
gpio_func_sel(sda_io_num, PIN_FUNC_GPIO);
gpio_set_direction(sda_io_num, GPIO_MODE_INPUT_OUTPUT_OD);
if (sda_pullup_en == GPIO_PULLUP_ENABLE) {
@ -981,11 +982,11 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, int sda_io_num, int scl_io_num, bool s
if (scl_io_num >= 0) {
if (mode == I2C_MODE_MASTER) {
gpio_set_level(scl_io_num, I2C_IO_INIT_LEVEL);
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[scl_io_num], PIN_FUNC_GPIO);
gpio_func_sel(scl_io_num, PIN_FUNC_GPIO);
gpio_set_direction(scl_io_num, GPIO_MODE_INPUT_OUTPUT_OD);
esp_rom_gpio_connect_out_signal(scl_io_num, scl_out_sig, 0, 0);
} else {
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[scl_io_num], PIN_FUNC_GPIO);
gpio_func_sel(scl_io_num, PIN_FUNC_GPIO);
gpio_set_direction(scl_io_num, GPIO_MODE_INPUT);
}
esp_rom_gpio_connect_in_signal(scl_io_num, scl_in_sig, 0);

5
components/esp_driver_i2c/i2c_common.c
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@ -26,6 +26,7 @@
#include "soc/i2c_periph.h"
#include "esp_clk_tree.h"
#include "clk_ctrl_os.h"
#include "esp_private/gpio.h"
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
#include "esp_private/sleep_retention.h"
#endif
@ -249,7 +250,7 @@ esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle)
};
ESP_RETURN_ON_ERROR(gpio_set_level(handle->sda_num, 1), TAG, "i2c sda pin set level failed");
ESP_RETURN_ON_ERROR(gpio_config(&sda_conf), TAG, "config GPIO failed");
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[handle->sda_num], PIN_FUNC_GPIO);
gpio_func_sel(handle->sda_num, PIN_FUNC_GPIO);
esp_rom_gpio_connect_out_signal(handle->sda_num, i2c_periph_signal[port_id].sda_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(handle->sda_num, i2c_periph_signal[port_id].sda_in_sig, 0);
@ -263,7 +264,7 @@ esp_err_t i2c_common_set_pins(i2c_bus_handle_t handle)
};
ESP_RETURN_ON_ERROR(gpio_set_level(handle->scl_num, 1), TAG, "i2c scl pin set level failed");
ESP_RETURN_ON_ERROR(gpio_config(&scl_conf), TAG, "config GPIO failed");
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[handle->scl_num], PIN_FUNC_GPIO);
gpio_func_sel(handle->scl_num, PIN_FUNC_GPIO);
esp_rom_gpio_connect_out_signal(handle->scl_num, i2c_periph_signal[port_id].scl_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(handle->scl_num, i2c_periph_signal[port_id].scl_in_sig, 0);
return ret;

1121
components/hal/esp32c5/include/hal/i2c_ll.h 100644
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Plik diff jest za duży Load Diff

22
components/soc/esp32c5/i2c_periph.c 100644
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@ -0,0 +1,22 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/i2c_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
*/
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
{
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
.irq = ETS_I2C_EXT0_INTR_SOURCE,
.module = PERIPH_I2C0_MODULE,
},
};

46
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -39,6 +39,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@ -197,7 +201,47 @@ config SOC_RTCIO_PIN_COUNT
config SOC_I2C_NUM
int
default 2
default 1
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_CMD_REG_NUM
int
default 8
config SOC_I2C_SUPPORT_SLAVE
bool
default y
config SOC_I2C_SUPPORT_HW_FSM_RST
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_XTAL
bool
default y
config SOC_I2C_SUPPORT_10BIT_ADDR
bool
default y
config SOC_I2C_SLAVE_SUPPORT_BROADCAST
bool
default y
config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool

2
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@ -332,7 +332,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8713 (inherit from C6)
/**
* @brief Type of I2C clock source.
*/
typedef enum { // TODO: [ESP32C5] IDF-8694, IDF-8696 (inherit from C6)
typedef enum {
I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */

11
components/soc/esp32c5/include/soc/i2c_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -1098,7 +1098,7 @@ typedef struct i2c_dev_t {
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
volatile i2c_filter_cfg_reg_t filter_cfg;
uint32_t reserved_054;
volatile i2c_comd_reg_t comd[8];
volatile i2c_comd_reg_t command[8];
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
@ -1106,16 +1106,15 @@ typedef struct i2c_dev_t {
uint32_t reserved_088[28];
volatile i2c_date_reg_t date;
uint32_t reserved_0fc;
volatile i2c_txfifo_start_addr_reg_t txfifo_start_addr;
uint32_t reserved_104[31];
volatile i2c_rxfifo_start_addr_reg_t rxfifo_start_addr;
volatile uint32_t txfifo_mem[32];
volatile uint32_t rxfifo_mem[32];
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifndef __cplusplus
_Static_assert(sizeof(i2c_dev_t) == 0x184, "Invalid size of i2c_dev_t structure");
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
#endif
#ifdef __cplusplus

12
components/soc/esp32c5/include/soc/pcr_struct.h
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@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -2124,6 +2124,13 @@ typedef union {
uint32_t val;
} pcr_date_reg_t;
/**
* @brief The struct of I2C configuration registers
*/
typedef struct {
pcr_i2c_conf_reg_t i2c_conf;
pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
} pcr_i2c_reg_t;
typedef struct pcr_dev_t {
volatile pcr_uart0_conf_reg_t uart0_conf;
@ -2134,8 +2141,7 @@ typedef struct pcr_dev_t {
volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl;
volatile pcr_mspi_conf_reg_t mspi_conf;
volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf;
volatile pcr_i2c_conf_reg_t i2c_conf;
volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf;
volatile pcr_i2c_reg_t i2c[1];
volatile pcr_twai0_conf_reg_t twai0_conf;
volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf;
volatile pcr_twai1_conf_reg_t twai1_conf;

30
components/soc/esp32c5/include/soc/soc_caps.h
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@ -43,7 +43,7 @@
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687
// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8698, IDF-8699
// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8684
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
// #define SOC_AES_SUPPORTED 1 // TODO: [ESP32C5] IDF-8627
// #define SOC_MPI_SUPPORTED 1
@ -227,23 +227,23 @@
// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C5 has 2 I2C
#define SOC_I2C_NUM (2)
// ESP32-C5 has 1 I2C
#define SOC_I2C_NUM (1UL)
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// #define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
#define SOC_I2C_SUPPORT_SLAVE (1)
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1) // TODO: [ESP32C5] IDF-8667
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1)
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
/*-------------------------- LP_I2C CAPS -------------------------------------*/
// ESP32-C5 has 1 LP_I2C

1
components/soc/esp32c5/ld/esp32c5.peripherals.ld
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@ -22,7 +22,6 @@ PROVIDE ( TWAI1 = 0x6000D000 );
PROVIDE ( APB_SARADC = 0x6000E000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6000F000 );
PROVIDE ( INTMTX = 0x60010000 );
PROVIDE ( I2C1 = 0x60011000 );
PROVIDE ( PCNT = 0x60012000 );
PROVIDE ( SOC_ETM = 0x60013000 );
PROVIDE ( MCPWM = 0x60014000 );