From 0f6f3c0eceeb8564351716823f43cb3fb1ce1bb7 Mon Sep 17 00:00:00 2001 From: Omar Chebib Date: Mon, 27 Sep 2021 13:52:58 +0800 Subject: [PATCH] RISC-V: fix usage of special register when interrupts are enabled --- components/riscv/vectors.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/components/riscv/vectors.S b/components/riscv/vectors.S index 2e1c7c477f..1006d5bea5 100644 --- a/components/riscv/vectors.S +++ b/components/riscv/vectors.S @@ -267,8 +267,8 @@ _interrupt_handler: #endif /* call the C dispatcher */ - mv a0, sp /* argument 1, stack pointer */ - csrr a1, mcause /* argument 2, interrupt number */ + mv a0, sp /* argument 1, stack pointer */ + mv a1, s1 /* argument 2, interrupt number (mcause) */ /* mask off the interrupt flag of mcause */ li t0, 0x7fffffff and a1, a1, t0 @@ -276,7 +276,7 @@ _interrupt_handler: /* After dispatch c handler, disable interrupt to make freertos make context switch */ - la t0, 0x8 + li t0, 0x8 csrrc t0, mstatus, t0 /* restore the interrupt threshold level */